[PATCH 00/65] drm/i915: finish the job of removing implicit dev_priv

[PATCH 00/65] drm/i915: finish the job of removing implicit dev_priv

[Jani Nikula]

Rip the band-aid. Finish the job of removing implicit dev_priv
usage. It's a lot, but it's straightforward.

BR,
Jani.

Jani Nikula (65):
  drm/i915: pass dev_priv explicitly to DPLL
  drm/i915: pass dev_priv explicitly to DPLL_MD
  drm/i915: pass dev_priv explicitly to TRANS_HTOTAL
  drm/i915: pass dev_priv explicitly to TRANS_HBLANK
  drm/i915: pass dev_priv explicitly to TRANS_HSYNC
  drm/i915: pass dev_priv explicitly to TRANS_VTOTAL
  drm/i915: pass dev_priv explicitly to TRANS_VBLANK
  drm/i915: pass dev_priv explicitly to TRANS_VSYNC
  drm/i915: pass dev_priv explicitly to BCLRPAT
  drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT
  drm/i915: pass dev_priv explicitly to PIPESRC
  drm/i915: pass dev_priv explicitly to TRANS_MULT
  drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN
  drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT
  drm/i915: pass dev_priv explicitly to PFIT_CONTROL
  drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS
  drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS
  drm/i915: pass dev_priv explicitly to TRANSCONF
  drm/i915: pass dev_priv explicitly to PIPEDSL
  drm/i915: pass dev_priv explicitly to PIPEFRAME
  drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL
  drm/i915: pass dev_priv explicitly to PIPESTAT
  drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL
  drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS
  drm/i915: pass dev_priv explicitly to DSPARB
  drm/i915: pass dev_priv explicitly to DSPFW1
  drm/i915: pass dev_priv explicitly to DSPFW2
  drm/i915: pass dev_priv explicitly to DSPFW3
  drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X
  drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X
  drm/i915: pass dev_priv explicitly to CHV_BLEND
  drm/i915: pass dev_priv explicitly to CHV_CANVAS
  drm/i915: pass dev_priv explicitly to SWF0
  drm/i915: pass dev_priv explicitly to SWF1
  drm/i915: pass dev_priv explicitly to SWF3
  drm/i915: pass dev_priv explicitly to _PIPEBDSL
  drm/i915: pass dev_priv explicitly to _TRANSBCONF
  drm/i915: pass dev_priv explicitly to _PIPEBSTAT
  drm/i915: pass dev_priv explicitly to _PIPEB_FRMCOUNT_G4X
  drm/i915: pass dev_priv explicitly to _PIPEB_FLIPCOUNT_G4X
  drm/i915: pass dev_priv explicitly to _DSPBCNTR
  drm/i915: pass dev_priv explicitly to _DSPBADDR
  drm/i915: pass dev_priv explicitly to _DSPBSTRIDE
  drm/i915: pass dev_priv explicitly to _DSPBPOS
  drm/i915: pass dev_priv explicitly to _DSPBSIZE
  drm/i915: pass dev_priv explicitly to _DSPBSURF
  drm/i915: pass dev_priv explicitly to _DSPBTILEOFF
  drm/i915: pass dev_priv explicitly to _DSPBOFFSET
  drm/i915: pass dev_priv explicitly to _DSPBSURFLIVE
  drm/i915: pass dev_priv explicitly to PIPE_DATA_M1
  drm/i915: pass dev_priv explicitly to PIPE_DATA_N1
  drm/i915: pass dev_priv explicitly to PIPE_DATA_M2
  drm/i915: pass dev_priv explicitly to PIPE_DATA_N2
  drm/i915: pass dev_priv explicitly to PIPE_LINK_M1
  drm/i915: pass dev_priv explicitly to PIPE_LINK_N1
  drm/i915: pass dev_priv explicitly to PIPE_LINK_M2
  drm/i915: pass dev_priv explicitly to PIPE_LINK_N2
  drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL
  drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL
  drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2
  drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL
  drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS
  drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC
  drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY
  drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS

 drivers/gpu/drm/i915/display/g4x_dp.c         |   2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c     |   2 +-
 drivers/gpu/drm/i915/display/i9xx_wm.c        |  87 ++++----
 drivers/gpu/drm/i915/display/icl_dsi.c        |  46 +++--
 drivers/gpu/drm/i915/display/intel_crt.c      |  50 +++--
 drivers/gpu/drm/i915/display/intel_ddi.c      |  47 +++--
 drivers/gpu/drm/i915/display/intel_display.c  | 193 ++++++++++--------
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |  17 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 .../i915/display/intel_display_power_well.c   |  14 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   5 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  63 +++---
 drivers/gpu/drm/i915/display/intel_drrs.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_dvo.c      |   5 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |  15 +-
 .../drm/i915/display/intel_fifo_underrun.c    |  13 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   5 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |  12 +-
 drivers/gpu/drm/i915/display/intel_lvds.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  |  10 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |  21 +-
 drivers/gpu/drm/i915/display/intel_pps.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   5 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  14 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   3 +-
 drivers/gpu/drm/i915/gvt/cmd_parser.c         |   2 +-
 drivers/gpu/drm/i915/gvt/display.c            |  59 +++---
 drivers/gpu/drm/i915/gvt/fb_decoder.c         |   6 +-
 drivers/gpu/drm/i915/gvt/handlers.c           |  28 +--
 drivers/gpu/drm/i915/i915_irq.c               |   5 +-
 drivers/gpu/drm/i915/i915_reg.h               | 130 ++++++------
 drivers/gpu/drm/i915/i915_suspend.c           |  48 +++--
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   | 180 ++++++++--------
 35 files changed, 610 insertions(+), 490 deletions(-)

-- 
2.39.2

[PATCH 01/65] drm/i915: pass dev_priv explicitly to DPLL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 21 ++++-----
 .../drm/i915/display/intel_display_power.c    |  2 +-
 .../i915/display/intel_display_power_well.c   |  6 +--
 drivers/gpu/drm/i915/display/intel_dpll.c     | 45 ++++++++++---------
 drivers/gpu/drm/i915/display/intel_dvo.c      |  5 ++-
 drivers/gpu/drm/i915/display/intel_pps.c      |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               |  2 +-
 7 files changed, 43 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7370acdd6b8b..42e2d884c98e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -382,11 +382,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 		fallthrough;
 	case PORT_B:
 		port_mask = DPLL_PORTB_READY_MASK;
-		dpll_reg = DPLL(0);
+		dpll_reg = DPLL(dev_priv, 0);
 		break;
 	case PORT_C:
 		port_mask = DPLL_PORTC_READY_MASK;
-		dpll_reg = DPLL(0);
+		dpll_reg = DPLL(dev_priv, 0);
 		expected_mask <<= 4;
 		break;
 	case PORT_D:
@@ -8212,11 +8212,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
 	 * dividers, even though the register value does change.
 	 */
-	intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
-	intel_de_write(dev_priv, DPLL(pipe), dpll);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+		       dpll & ~DPLL_VGA_MODE_DIS);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
 
 	/* Wait for the clocks to stabilize. */
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 	udelay(150);
 
 	/* The pixel multiplier can only be updated once the
@@ -8224,12 +8225,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 *
 	 * So write it again.
 	 */
-	intel_de_write(dev_priv, DPLL(pipe), dpll);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
 
 	/* We do this three times for luck */
 	for (i = 0; i < 3 ; i++) {
-		intel_de_write(dev_priv, DPLL(pipe), dpll);
-		intel_de_posting_read(dev_priv, DPLL(pipe));
+		intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
+		intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 		udelay(150); /* wait for warmup */
 	}
 
@@ -8262,8 +8263,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	intel_wait_for_pipe_scanline_stopped(crtc);
 
-	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 }
 
 void intel_hpd_poll_fini(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 34b6d843bc9e..3c5cb587f9bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1772,7 +1772,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
 	 * current lane status.
 	 */
 	if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
-		u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
+		u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
 		unsigned int mask;
 
 		mask = status & DPLL_PORTB_READY_MASK;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 83f616097a29..3b6cb237d80a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1196,13 +1196,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 	 * CHV DPLL B/C have some issues if VGA mode is enabled.
 	 */
 	for_each_pipe(dev_priv, pipe) {
-		u32 val = intel_de_read(dev_priv, DPLL(pipe));
+		u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe));
 
 		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 		if (pipe != PIPE_A)
 			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
-		intel_de_write(dev_priv, DPLL(pipe), val);
+		intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
 	}
 
 	vlv_init_display_clock_gating(dev_priv);
@@ -1355,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
 		 */
 		if (BITS_SET(phy_control,
 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
-		    (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
+		    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
 
 		if (BITS_SET(phy_control,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a981f45facb3..a007ca5208b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -403,7 +403,7 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
 		hw_state->dpll_md = tmp;
 	}
 
-	hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
+	hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe));
 
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
 		hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
@@ -1842,11 +1842,12 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
 	 * dividers, even though the register value does change.
 	 */
-	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
-	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
+		       hw_state->dpll & ~DPLL_VGA_MODE_DIS);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
 
 	/* Wait for the clocks to stabilize. */
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 	udelay(150);
 
 	if (DISPLAY_VER(dev_priv) >= 4) {
@@ -1857,13 +1858,13 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 		 *
 		 * So write it again.
 		 */
-		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+		intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
 	}
 
 	/* We do this three times for luck */
 	for (i = 0; i < 3; i++) {
-		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
-		intel_de_posting_read(dev_priv, DPLL(pipe));
+		intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
+		intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 		udelay(150); /* wait for warmup */
 	}
 }
@@ -1991,11 +1992,11 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	enum pipe pipe = crtc->pipe;
 
-	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 	udelay(150);
 
-	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
+	if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
 		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
 }
 
@@ -2012,7 +2013,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
 	assert_pps_unlocked(dev_priv, pipe);
 
 	/* Enable Refclk */
-	intel_de_write(dev_priv, DPLL(pipe),
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
 		       hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
 
 	if (hw_state->dpll & DPLL_VCO_ENABLE) {
@@ -2138,10 +2139,10 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
 	udelay(1);
 
 	/* Enable PLL */
-	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
 
 	/* Check PLL is locked */
-	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
+	if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
 		drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
 }
 
@@ -2158,7 +2159,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
 	assert_pps_unlocked(dev_priv, pipe);
 
 	/* Enable Refclk and SSC */
-	intel_de_write(dev_priv, DPLL(pipe),
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
 		       hw_state->dpll & ~DPLL_VCO_ENABLE);
 
 	if (hw_state->dpll & DPLL_VCO_ENABLE) {
@@ -2183,7 +2184,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
 		 * We should always have it disabled.
 		 */
 		drm_WARN_ON(&dev_priv->drm,
-			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &
+			    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
 			     DPLL_VGA_MODE_DIS) == 0);
 	} else {
 		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
@@ -2241,8 +2242,8 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
-	intel_de_write(dev_priv, DPLL(pipe), val);
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 }
 
 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -2259,8 +2260,8 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	if (pipe != PIPE_A)
 		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 
-	intel_de_write(dev_priv, DPLL(pipe), val);
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 
 	vlv_dpio_get(dev_priv);
 
@@ -2285,8 +2286,8 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
 	/* Make sure the pipe isn't still relying on us */
 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
-	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
-	intel_de_posting_read(dev_priv, DPLL(pipe));
+	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
+	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
 }
 
 
@@ -2312,7 +2313,7 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 {
 	bool cur_state;
 
-	cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
+	cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
 	I915_STATE_WARN(dev_priv, cur_state != state,
 			"PLL state assertion failure (expected %s, current %s)\n",
 			str_on_off(state), str_on_off(cur_state));
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 1840f5b59229..091824334f26 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -456,13 +456,14 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
 	 * the device.
 	 */
 	for_each_pipe(dev_priv, pipe)
-		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
+		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0,
+					  DPLL_DVO_2X_MODE);
 
 	ret = dvo->dev_ops->init(&intel_dvo->dev, i2c);
 
 	/* restore the DVO 2x clock state to original */
 	for_each_pipe(dev_priv, pipe) {
-		intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
+		intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]);
 	}
 
 	intel_gmbus_force_bit(i2c, false);
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 73046ef58d8e..42306bc4ba86 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -119,7 +119,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 	else
 		DP |= DP_PIPE_SEL(pipe);
 
-	pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
+	pll_enabled = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
 
 	/*
 	 * The DPLL for the pipe must be enabled for this to work.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6877e2f0fbc3..8ff04bb19cbe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -668,7 +668,7 @@
 #define _DPLL_A			0x6014
 #define _DPLL_B			0x6018
 #define _CHV_DPLL_C		0x6030
-#define DPLL(pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+#define DPLL(dev_priv, pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
 						 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
 
 #define VGA0	_MMIO(0x6000)
-- 
2.39.2

[PATCH 02/65] drm/i915: pass dev_priv explicitly to DPLL_MD

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DPLL_MD register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++++-------
 drivers/gpu/drm/i915/i915_reg.h           |  2 +-
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a007ca5208b8..d67d5e2fd570 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -398,7 +398,8 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
 			tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
 		else
-			tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
+			tmp = intel_de_read(dev_priv,
+					    DPLL_MD(dev_priv, crtc->pipe));
 
 		hw_state->dpll_md = tmp;
 	}
@@ -1851,7 +1852,8 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 	udelay(150);
 
 	if (DISPLAY_VER(dev_priv) >= 4) {
-		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
+		intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+			       hw_state->dpll_md);
 	} else {
 		/* The pixel multiplier can only be updated once the
 		 * DPLL is enabled and the clocks are stable.
@@ -2021,8 +2023,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
 		_vlv_enable_pll(crtc_state);
 	}
 
-	intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
-	intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+	intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
+	intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
 }
 
 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -2175,7 +2177,8 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
 		 * the value from DPLLBMD to either pipe B or C.
 		 */
 		intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
-		intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
+		intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B),
+			       hw_state->dpll_md);
 		intel_de_write(dev_priv, CBR4_VLV, 0);
 		dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
 
@@ -2187,8 +2190,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
 			    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
 			     DPLL_VGA_MODE_DIS) == 0);
 	} else {
-		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
-		intel_de_posting_read(dev_priv, DPLL_MD(pipe));
+		intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
+			       hw_state->dpll_md);
+		intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ff04bb19cbe..ea8181abf7fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -768,7 +768,7 @@
 #define _DPLL_A_MD		0x601c
 #define _DPLL_B_MD		0x6020
 #define _CHV_DPLL_C_MD		0x603c
-#define DPLL_MD(pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
+#define DPLL_MD(dev_priv, pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
 						 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
 
 /*
-- 
2.39.2

[PATCH 03/65] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HTOTAL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
 drivers/gpu/drm/i915/gvt/handlers.c              | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 79ecfc339430..af0d3159369e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -915,7 +915,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	/* program TRANS_HTOTAL register */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-		intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
+		intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
 			       HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 42e2d884c98e..481e076b17e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2710,7 +2710,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
 			       vsyncshift);
 
-	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
 		       HTOTAL(adjusted_mode->crtc_htotal - 1));
 	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
@@ -2811,7 +2811,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	u32 tmp;
 
-	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
+	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
 
@@ -8189,7 +8189,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		PLL_REF_INPUT_DREFCLK |
 		DPLL_VCO_ENABLE;
 
-	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
 	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 826e38a9e6a4..2bf00d5336e3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -224,7 +224,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 708b99be02ac..06ba39b2b103 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -677,7 +677,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
 
 	/* Get H/V total from transcoder timing */
-	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
+	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
 	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
 
 	if (dp_br && link_n && htotal && vtotal) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea8181abf7fd..8398826e9c2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1217,7 +1217,7 @@
 #define _TRANS_VSYNC_DSI1	0x6b814
 #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
 
-#define TRANS_HTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
+#define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
 #define TRANS_HBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index f5c4e4e2f11f..2bc90909d980 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -231,7 +231,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(SPRSCALE(PIPE_C));
 	MMIO_D(SPRSURFLIVE(PIPE_C));
 	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
-	MMIO_D(TRANS_HTOTAL(TRANSCODER_A));
+	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HBLANK(TRANSCODER_A));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
@@ -240,7 +240,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(BCLRPAT(TRANSCODER_A));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
 	MMIO_D(PIPESRC(TRANSCODER_A));
-	MMIO_D(TRANS_HTOTAL(TRANSCODER_B));
+	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HBLANK(TRANSCODER_B));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
@@ -249,7 +249,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(BCLRPAT(TRANSCODER_B));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
 	MMIO_D(PIPESRC(TRANSCODER_B));
-	MMIO_D(TRANS_HTOTAL(TRANSCODER_C));
+	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HBLANK(TRANSCODER_C));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
@@ -258,7 +258,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(BCLRPAT(TRANSCODER_C));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
 	MMIO_D(PIPESRC(TRANSCODER_C));
-	MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP));
+	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 04/65] drm/i915: pass dev_priv explicitly to TRANS_HBLANK

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HBLANK register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c     | 7 ++++---
 drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 481e076b17e6..997418fb7310 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2713,7 +2713,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
 		       HTOTAL(adjusted_mode->crtc_htotal - 1));
-	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
 	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
@@ -2816,7 +2816,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
 
 	if (!transcoder_is_dsi(cpu_transcoder)) {
-		tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_HBLANK(dev_priv, cpu_transcoder));
 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
 	}
@@ -8191,7 +8192,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
-	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
 	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 2bf00d5336e3..625b1fedd54c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8398826e9c2d..66e652119a7e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1218,7 +1218,7 @@
 #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
 
 #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
-#define TRANS_HBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
+#define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 2bc90909d980..47681fa69020 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -232,7 +232,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(SPRSURFLIVE(PIPE_C));
 	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_HBLANK(TRANSCODER_A));
+	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
@@ -241,7 +241,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
 	MMIO_D(PIPESRC(TRANSCODER_A));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_HBLANK(TRANSCODER_B));
+	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
@@ -250,7 +250,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
 	MMIO_D(PIPESRC(TRANSCODER_B));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_HBLANK(TRANSCODER_C));
+	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
@@ -259,7 +259,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
 	MMIO_D(PIPESRC(TRANSCODER_C));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
+	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 05/65] drm/i915: pass dev_priv explicitly to TRANS_HSYNC

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_HSYNC register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
 drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
 5 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index af0d3159369e..f87a2170ac91 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -938,7 +938,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
+			intel_de_write(dev_priv,
+				       TRANS_HSYNC(dev_priv, dsi_trans),
 				       HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 997418fb7310..111f2c400ecd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2716,7 +2716,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
-	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
 
@@ -2822,7 +2822,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
 	}
 
-	tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
+	tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
 
@@ -8194,7 +8194,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
 	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
-	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
 	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 625b1fedd54c..480c0e09434d 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -228,7 +228,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
 
 	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66e652119a7e..0d33815b91a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1219,7 +1219,7 @@
 
 #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
 #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
-#define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
+#define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 47681fa69020..09d8960f7398 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -233,7 +233,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
+	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
@@ -242,7 +242,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPESRC(TRANSCODER_A));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
+	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
@@ -251,7 +251,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPESRC(TRANSCODER_B));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
+	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
@@ -260,7 +260,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPESRC(TRANSCODER_C));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
+	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 06/65] drm/i915: pass dev_priv explicitly to TRANS_VTOTAL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VTOTAL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           |  2 +-
 drivers/gpu/drm/i915/display/intel_crt.c         |  3 ++-
 drivers/gpu/drm/i915/display/intel_display.c     | 10 +++++-----
 drivers/gpu/drm/i915/display/intel_pch_display.c |  2 +-
 drivers/gpu/drm/i915/gvt/handlers.c              |  2 +-
 drivers/gpu/drm/i915/i915_reg.h                  |  2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      |  8 ++++----
 7 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f87a2170ac91..f95709321ea6 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -953,7 +953,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		 * struct drm_display_mode.
 		 * For interlace mode: program required pixel minus 2
 		 */
-		intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
+		intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
 			       VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 10e95dc425a6..29ab5b112b86 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -708,7 +708,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 
 	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
-	save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+	save_vtotal = intel_de_read(dev_priv,
+				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
 	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
 
 	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 111f2c400ecd..c681a23be1eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2720,7 +2720,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
 
-	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
@@ -2736,7 +2736,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	 * bits. */
 	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
 	    (pipe == PIPE_B || pipe == PIPE_C))
-		intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
+		intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
 			       VACTIVE(crtc_vdisplay - 1) |
 			       VTOTAL(crtc_vtotal - 1));
 }
@@ -2767,7 +2767,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The double buffer latch point for TRANS_VTOTAL
 	 * is the transcoder's undelayed vblank.
 	 */
-	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 }
@@ -2826,7 +2826,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
 
-	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
 
@@ -8196,7 +8196,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
 	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
-	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
 	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 480c0e09434d..611a9cd2596f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -231,7 +231,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 		       intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
 
 	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 06ba39b2b103..00cf35a9669e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -678,7 +678,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 
 	/* Get H/V total from transcoder timing */
 	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
-	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
+	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
 
 	if (dp_br && link_n && htotal && vtotal) {
 		u64 pixel_clk = 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d33815b91a4..3b48022b29a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1220,7 +1220,7 @@
 #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
 #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
-#define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
+#define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 09d8960f7398..5dd85943e0a1 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -234,7 +234,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
+	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
 	MMIO_D(BCLRPAT(TRANSCODER_A));
@@ -243,7 +243,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
+	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
 	MMIO_D(BCLRPAT(TRANSCODER_B));
@@ -252,7 +252,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
+	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
 	MMIO_D(BCLRPAT(TRANSCODER_C));
@@ -261,7 +261,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
+	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
 	MMIO_D(BCLRPAT(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 07/65] drm/i915: pass dev_priv explicitly to TRANS_VBLANK

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VBLANK register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           |  3 ++-
 drivers/gpu/drm/i915/display/intel_crt.c         | 10 +++++++---
 drivers/gpu/drm/i915/display/intel_display.c     |  9 +++++----
 drivers/gpu/drm/i915/display/intel_pch_display.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h                  |  2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      |  8 ++++----
 6 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f95709321ea6..0ee42954054f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -995,7 +995,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
+			intel_de_write(dev_priv,
+				       TRANS_VBLANK(dev_priv, dsi_trans),
 				       VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 29ab5b112b86..54549d2cfcff 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -710,7 +710,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
 	save_vtotal = intel_de_read(dev_priv,
 				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
-	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
+	vblank = intel_de_read(dev_priv,
+			       TRANS_VBLANK(dev_priv, cpu_transcoder));
 
 	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
 	vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
@@ -749,7 +750,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 			u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
 
 			vblank_start = vsync_start;
-			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+			intel_de_write(dev_priv,
+				       TRANS_VBLANK(dev_priv, cpu_transcoder),
 				       VBLANK_START(vblank_start - 1) |
 				       VBLANK_END(vblank_end - 1));
 			restore_vblank = true;
@@ -782,7 +784,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 
 		/* restore vblank if necessary */
 		if (restore_vblank)
-			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
+			intel_de_write(dev_priv,
+				       TRANS_VBLANK(dev_priv, cpu_transcoder),
+				       vblank);
 		/*
 		 * If more than 3/4 of the scanline detected a monitor,
 		 * then it is assumed to be present. This works even on i830,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c681a23be1eb..87a690cf5808 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2723,7 +2723,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
-	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
 	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
@@ -2760,7 +2760,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
 	 * But let's write it anyway to keep the state checker happy.
 	 */
-	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
 	/*
@@ -2832,7 +2832,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 
 	/* FIXME TGL+ DSI transcoders have this! */
 	if (!transcoder_is_dsi(cpu_transcoder)) {
-		tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_VBLANK(dev_priv, cpu_transcoder));
 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
 	}
@@ -8198,7 +8199,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
 	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
-	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
 	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 611a9cd2596f..03a33ff2653a 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -233,7 +233,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b48022b29a7..155259c11c88 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1221,7 +1221,7 @@
 #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
-#define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
+#define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5dd85943e0a1..baeedcdfdcab 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -235,7 +235,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
+	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
 	MMIO_D(BCLRPAT(TRANSCODER_A));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
@@ -244,7 +244,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
+	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
 	MMIO_D(BCLRPAT(TRANSCODER_B));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
@@ -253,7 +253,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
+	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
 	MMIO_D(BCLRPAT(TRANSCODER_C));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
@@ -262,7 +262,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
+	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
 	MMIO_D(BCLRPAT(TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 08/65] drm/i915: pass dev_priv explicitly to TRANS_VSYNC

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VSYNC register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
 drivers/gpu/drm/i915/display/intel_crt.c         | 3 ++-
 drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
 drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
 6 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 0ee42954054f..b267099fde8a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -967,7 +967,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (is_vid_mode(intel_dsi)) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
+			intel_de_write(dev_priv,
+				       TRANS_VSYNC(dev_priv, dsi_trans),
 				       VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 54549d2cfcff..15569cf96c9c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -746,7 +746,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 		* Yes, this will flicker
 		*/
 		if (vblank_start <= vactive && vblank_end >= vtotal) {
-			u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
+			u32 vsync = intel_de_read(dev_priv,
+						  TRANS_VSYNC(dev_priv, cpu_transcoder));
 			u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
 
 			vblank_start = vsync_start;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 87a690cf5808..776e4450e4af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2726,7 +2726,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
 		       VBLANK_START(crtc_vblank_start - 1) |
 		       VBLANK_END(crtc_vblank_end - 1));
-	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
 
@@ -2837,7 +2837,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
 	}
-	tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
+	tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder));
 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
 
@@ -8201,7 +8201,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
 	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
-	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
 	intel_de_write(dev_priv, PIPESRC(pipe),
 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 03a33ff2653a..9f8269705171 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -235,7 +235,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 155259c11c88..c47aae3f70cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1222,7 +1222,7 @@
 #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
-#define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
+#define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index baeedcdfdcab..e618a16eafac 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
+	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(BCLRPAT(TRANSCODER_A));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
 	MMIO_D(PIPESRC(TRANSCODER_A));
@@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
+	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(BCLRPAT(TRANSCODER_B));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
 	MMIO_D(PIPESRC(TRANSCODER_B));
@@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
+	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(BCLRPAT(TRANSCODER_C));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
 	MMIO_D(PIPESRC(TRANSCODER_C));
@@ -263,7 +263,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
+	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(BCLRPAT(TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
-- 
2.39.2

[PATCH 09/65] drm/i915: pass dev_priv explicitly to BCLRPAT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the BCLRPAT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c     | 10 ++++++----
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h              |  2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  |  8 ++++----
 4 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 15569cf96c9c..2660c4a53e6f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -193,7 +193,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
 		adpa |= ADPA_PIPE_SEL(crtc->pipe);
 
 	if (!HAS_PCH_SPLIT(dev_priv))
-		intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
+		intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
 
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
@@ -707,7 +707,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 
 	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 
-	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
+	save_bclrpat = intel_de_read(dev_priv,
+				     BCLRPAT(dev_priv, cpu_transcoder));
 	save_vtotal = intel_de_read(dev_priv,
 				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
 	vblank = intel_de_read(dev_priv,
@@ -720,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 	vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
 
 	/* Set the border color to purple. */
-	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
+	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
 
 	if (DISPLAY_VER(dev_priv) != 2) {
 		u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
@@ -800,7 +801,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 	}
 
 	/* Restore previous settings */
-	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
+	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
+		       save_bclrpat);
 
 	return status;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 776e4450e4af..49f7ac0f7997 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1870,7 +1870,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 
 	/* Border color in case we don't scale up to the full screen. Black by
 	 * default, change to something else for debugging. */
-	intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
+	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
 }
 
 /* Prefer intel_encoder_is_combo() */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c47aae3f70cd..92d9e8cdf782 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1223,7 +1223,7 @@
 #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
 #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
-#define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
+#define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index e618a16eafac..5e1ef52922cc 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -237,7 +237,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
-	MMIO_D(BCLRPAT(TRANSCODER_A));
+	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
 	MMIO_D(PIPESRC(TRANSCODER_A));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
@@ -246,7 +246,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
-	MMIO_D(BCLRPAT(TRANSCODER_B));
+	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
 	MMIO_D(PIPESRC(TRANSCODER_B));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
@@ -255,7 +255,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
-	MMIO_D(BCLRPAT(TRANSCODER_C));
+	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
 	MMIO_D(PIPESRC(TRANSCODER_C));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
@@ -264,7 +264,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
-	MMIO_D(BCLRPAT(TRANSCODER_EDP));
+	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
-- 
2.39.2

[PATCH 10/65] drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VSYNCSHIFT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
 drivers/gpu/drm/i915/display/intel_display.c     | 3 ++-
 drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
 5 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b267099fde8a..0625c4d5ee0b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -982,7 +982,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	if (is_vid_mode(intel_dsi)) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
+			intel_de_write(dev_priv,
+				       TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
 				       vsync_shift);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 49f7ac0f7997..993eb0935f6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2707,7 +2707,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 4)
-		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
+		intel_de_write(dev_priv,
+			       TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
 			       vsyncshift);
 
 	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 9f8269705171..6a45bc1651c3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -237,7 +237,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
 		       intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
 	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
-		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
+		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));
 }
 
 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92d9e8cdf782..d961f3f70aaa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1224,7 +1224,7 @@
 #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
-#define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
+#define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5e1ef52922cc..5abae7df0bfe 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -238,7 +238,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
-	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
+	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPESRC(TRANSCODER_A));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
@@ -247,7 +247,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
-	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
+	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPESRC(TRANSCODER_B));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
@@ -256,7 +256,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
-	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
+	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPESRC(TRANSCODER_C));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
@@ -265,7 +265,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
-	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
+	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
-- 
2.39.2

[PATCH 11/65] drm/i915: pass dev_priv explicitly to PIPESRC

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPESRC register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c    | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
 drivers/gpu/drm/i915/gvt/fb_decoder.c        | 6 +++---
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 6 +++---
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 5c8778865156..864d94406894 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1053,7 +1053,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	drm_WARN_ON(&dev_priv->drm, offset != 0);
 
-	val = intel_de_read(dev_priv, PIPESRC(pipe));
+	val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe));
 	fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
 	fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 993eb0935f6b..81ae72648e8e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2784,7 +2784,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-	intel_de_write(dev_priv, PIPESRC(pipe),
+	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
 }
 
@@ -2878,7 +2878,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	u32 tmp;
 
-	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
+	tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
 
 	drm_rect_init(&pipe_config->pipe_src, 0, 0,
 		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
@@ -8204,7 +8204,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
 	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
-	intel_de_write(dev_priv, PIPESRC(pipe),
+	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
 
 	intel_de_write(dev_priv, FP0(pipe), fp);
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 0afde865a7de..c454e25b2b0f 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -267,11 +267,11 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
 		(_PRI_PLANE_STRIDE_MASK >> 6) :
 		_PRI_PLANE_STRIDE_MASK, plane->bpp);
 
-	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
+	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>
 		_PIPE_H_SRCSZ_SHIFT;
 	plane->width += 1;
-	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
-			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
+	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &
+			 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
 	plane->height += 1;	/* raw height is one minus the real value */
 
 	val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d961f3f70aaa..2e26464672f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1225,7 +1225,7 @@
 #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
-#define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
+#define PIPESRC(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
 /* VRR registers */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5abae7df0bfe..ff561a1e0fd3 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -239,7 +239,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPESRC(TRANSCODER_A));
+	MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
@@ -248,7 +248,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPESRC(TRANSCODER_B));
+	MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
@@ -257,7 +257,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPESRC(TRANSCODER_C));
+	MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
-- 
2.39.2

[PATCH 12/65] drm/i915: pass dev_priv explicitly to TRANS_MULT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_MULT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 6 +++---
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 81ae72648e8e..e7ee4970e306 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1646,7 +1646,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 		intel_vrr_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
-		intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
+		intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
 			       crtc_state->pixel_multiplier - 1);
 
 	hsw_set_frame_start_delay(crtc_state);
@@ -3861,7 +3861,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
 		pipe_config->pixel_multiplier =
 			intel_de_read(dev_priv,
-				      TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
+				      TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;
 	} else {
 		pipe_config->pixel_multiplier = 1;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2e26464672f7..3bb895d030ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1226,7 +1226,7 @@
 #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
 #define PIPESRC(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
-#define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
+#define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
 /* VRR registers */
 #define _TRANS_VRR_CTL_A		0x60420
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index ff561a1e0fd3..600e89148f77 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -506,9 +506,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(GAMMA_MODE(PIPE_A));
 	MMIO_D(GAMMA_MODE(PIPE_B));
 	MMIO_D(GAMMA_MODE(PIPE_C));
-	MMIO_D(TRANS_MULT(TRANSCODER_A));
-	MMIO_D(TRANS_MULT(TRANSCODER_B));
-	MMIO_D(TRANS_MULT(TRANSCODER_C));
+	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A));
+	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B));
+	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C));
 	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A));
 	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B));
 	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));
-- 
2.39.2

[PATCH 13/65] drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_HOTPLUG_EN register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 2660c4a53e6f..b7eab52b64b6 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -603,7 +603,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 					      CRT_HOTPLUG_FORCE_DETECT,
 					      CRT_HOTPLUG_FORCE_DETECT);
 		/* wait for FORCE_DETECT to go off */
-		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
+		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
 					    CRT_HOTPLUG_FORCE_DETECT, 1000))
 			drm_dbg_kms(&dev_priv->drm,
 				    "timed out waiting for FORCE_DETECT to go off");
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index d270bb7b9462..90fe5f8538e1 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -186,7 +186,8 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 	lockdep_assert_held(&dev_priv->irq_lock);
 	drm_WARN_ON(&dev_priv->drm, bits & ~mask);
 
-	intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits);
+	intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask,
+			 bits);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3bb895d030ab..4508c535f320 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1378,7 +1378,7 @@
 
 
 /* Hotplug control (945+ only) */
-#define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
+#define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
 #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
 #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
-- 
2.39.2

[PATCH 14/65] drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_HOTPLUG_STAT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c            | 2 +-
 drivers/gpu/drm/i915/display/intel_crt.c         | 5 +++--
 drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 9 ++++++---
 drivers/gpu/drm/i915/i915_irq.c                  | 5 +++--
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 6 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 06ec04e667e3..40fee8380a81 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1228,7 +1228,7 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder)
 		return false;
 	}
 
-	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
+	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)) & bit;
 }
 
 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index b7eab52b64b6..808fa8afb164 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -609,12 +609,13 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 				    "timed out waiting for FORCE_DETECT to go off");
 	}
 
-	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
+	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
 	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 		ret = true;
 
 	/* clear the interrupt we just generated, if any */
-	intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
+	intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
+		       CRT_HOTPLUG_INT_STATUS);
 
 	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 1674570dff1e..be5b48861baf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1377,7 +1377,7 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
 
 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
-	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0);
+	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 90fe5f8538e1..a1f07ee69a86 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -435,18 +435,21 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
 	 * bits can itself generate a new hotplug interrupt :(
 	 */
 	for (i = 0; i < 10; i++) {
-		u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
+		u32 tmp = intel_uncore_read(&dev_priv->uncore,
+					    PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask;
 
 		if (tmp == 0)
 			return hotplug_status;
 
 		hotplug_status |= tmp;
-		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
+		intel_uncore_write(&dev_priv->uncore,
+				   PORT_HOTPLUG_STAT(dev_priv),
+				   hotplug_status);
 	}
 
 	drm_WARN_ONCE(&dev_priv->drm, 1,
 		      "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
-		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
+		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv)));
 
 	return hotplug_status;
 }
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 678d632ed043..8059ac7e15fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1040,7 +1040,8 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 
 	if (I915_HAS_HOTPLUG(dev_priv)) {
 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-		intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0);
+		intel_uncore_rmw(&dev_priv->uncore,
+				 PORT_HOTPLUG_STAT(dev_priv), 0, 0);
 	}
 
 	i9xx_pipestat_irq_reset(dev_priv);
@@ -1149,7 +1150,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0);
+	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
 
 	i9xx_pipestat_irq_reset(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4508c535f320..166c7f4f9c6c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1408,7 +1408,7 @@
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 
-#define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
+#define PORT_HOTPLUG_STAT(dev_priv)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
 /* HDMI/DP bits are g4x+ */
 #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
 #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
-- 
2.39.2

[PATCH 15/65] drm/i915: pass dev_priv explicitly to PFIT_CONTROL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PFIT_CONTROL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++-----
 drivers/gpu/drm/i915/display/intel_lvds.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h              |  2 +-
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7ee4970e306..49672694293f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1861,12 +1861,13 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 	 * according to register description and PRM.
 	 */
 	drm_WARN_ON(&dev_priv->drm,
-		    intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
+		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
 	intel_de_write(dev_priv, PFIT_PGM_RATIOS,
 		       crtc_state->gmch_pfit.pgm_ratios);
-	intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
+	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
+		       crtc_state->gmch_pfit.control);
 
 	/* Border color in case we don't scale up to the full screen. Black by
 	 * default, change to something else for debugging. */
@@ -2195,8 +2196,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
 
 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
-		    intel_de_read(dev_priv, PFIT_CONTROL));
-	intel_de_write(dev_priv, PFIT_CONTROL, 0);
+		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
+	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
 }
 
 static void i9xx_crtc_disable(struct intel_atomic_state *state,
@@ -2974,7 +2975,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
 	if (!i9xx_has_pfit(dev_priv))
 		return;
 
-	tmp = intel_de_read(dev_priv, PFIT_CONTROL);
+	tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
 	if (!(tmp & PFIT_ENABLE))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 891777481dd9..9f018503d4fd 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
 	/* gen2/3 store dither state in pfit control, needs to match */
 	if (DISPLAY_VER(dev_priv) < 4) {
-		tmp = intel_de_read(dev_priv, PFIT_CONTROL);
+		tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
 
 		crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1c2099ed5514..e41881f08d1f 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -950,7 +950,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 	} else {
 		u32 tmp;
 
-		if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
+		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
 			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
 		else
 			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 166c7f4f9c6c..b0dbe6113bbc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1588,7 +1588,7 @@
 #define   VIDEO_DIP_ENABLE_AS_ADL	REG_BIT(23)
 
 /* Panel fitting */
-#define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
+#define PFIT_CONTROL(dev_priv)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
 #define   PFIT_ENABLE			REG_BIT(31)
 #define   PFIT_PIPE_MASK		REG_GENMASK(30, 29) /* 965+ */
 #define   PFIT_PIPE(pipe)		REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
-- 
2.39.2

[PATCH 16/65] drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PFIT_PGM_RATIOS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_overlay.c | 5 +++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 49672694293f..1e2ddae5ba94 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1864,7 +1864,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
 
-	intel_de_write(dev_priv, PFIT_PGM_RATIOS,
+	intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
 		       crtc_state->gmch_pfit.pgm_ratios);
 	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
 		       crtc_state->gmch_pfit.control);
@@ -2990,7 +2990,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
 
 	crtc_state->gmch_pfit.control = tmp;
 	crtc_state->gmch_pfit.pgm_ratios =
-		intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+		intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
 }
 
 static enum intel_output_format
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index e41881f08d1f..117120ce5a1d 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -943,7 +943,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 	 * line with the intel documentation for the i965
 	 */
 	if (DISPLAY_VER(dev_priv) >= 4) {
-		u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+		u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
 
 		/* on i965 use the PGM reg to read out the autoscaler values */
 		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
@@ -953,7 +953,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
 			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
 		else
-			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
+			tmp = intel_de_read(dev_priv,
+					    PFIT_PGM_RATIOS(dev_priv));
 
 		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b0dbe6113bbc..094e693c40bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1609,7 +1609,7 @@
 #define   PFIT_HORIZ_AUTO_SCALE		REG_BIT(5) /* pre-965 */
 #define   PFIT_PANEL_8TO6_DITHER_ENABLE	REG_BIT(3) /* pre-965 */
 
-#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
+#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
 #define   PFIT_VERT_SCALE_MASK		REG_GENMASK(31, 20) /* pre-965 */
 #define   PFIT_VERT_SCALE(x)		REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
 #define   PFIT_HORIZ_SCALE_MASK		REG_GENMASK(15, 4) /* pre-965 */
-- 
2.39.2

[PATCH 17/65] drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PFIT_AUTO_RATIOS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_overlay.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 117120ce5a1d..d3d0e22cdd34 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -951,7 +951,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 		u32 tmp;
 
 		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
-			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
+			tmp = intel_de_read(dev_priv,
+					    PFIT_AUTO_RATIOS(dev_priv));
 		else
 			tmp = intel_de_read(dev_priv,
 					    PFIT_PGM_RATIOS(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 094e693c40bf..cd6eda1b6bef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1617,7 +1617,7 @@
 #define   PFIT_VERT_SCALE_MASK_965	REG_GENMASK(28, 16) /* 965+ */
 #define   PFIT_HORIZ_SCALE_MASK_965	REG_GENMASK(12, 0) /* 965+ */
 
-#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
+#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
 
 #define PCH_GTC_CTL		_MMIO(0xe7000)
 #define   PCH_GTC_ENABLE	(1 << 31)
-- 
2.39.2

[PATCH 18/65] drm/i915: pass dev_priv explicitly to TRANSCONF

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANSCONF register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 12 +++--
 drivers/gpu/drm/i915/display/intel_crt.c      | 11 ++--
 drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++--------
 .../i915/display/intel_display_power_well.c   |  8 +--
 drivers/gpu/drm/i915/display/intel_drrs.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |  6 +--
 .../gpu/drm/i915/display/intel_pch_display.c  |  7 +--
 drivers/gpu/drm/i915/display/vlv_dsi.c        |  3 +-
 drivers/gpu/drm/i915/gvt/display.c            | 12 ++---
 drivers/gpu/drm/i915/gvt/handlers.c           | 12 +++--
 drivers/gpu/drm/i915/i915_reg.h               |  2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  8 +--
 12 files changed, 76 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 0625c4d5ee0b..9beb94494b2b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1013,10 +1013,11 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-		intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
+		intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
+			     TRANSCONF_ENABLE);
 
 		/* wait for transcoder to be enabled */
-		if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
+		if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
 					  TRANSCONF_STATE_ENABLE, 10))
 			drm_err(&dev_priv->drm,
 				"DSI transcoder not enabled\n");
@@ -1279,10 +1280,11 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
 		dsi_trans = dsi_port_to_transcoder(port);
 
 		/* disable transcoder */
-		intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
+		intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+			     TRANSCONF_ENABLE, 0);
 
 		/* wait for transcoder to be disabled */
-		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
+		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
 					    TRANSCONF_STATE_ENABLE, 50))
 			drm_err(&dev_priv->drm,
 				"DSI trancoder not disabled\n");
@@ -1714,7 +1716,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
 			goto out;
 		}
 
-		tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
+		tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
 		ret = tmp & TRANSCONF_ENABLE;
 	}
 out:
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 808fa8afb164..d4f16d894eda 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -725,11 +725,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
 
 	if (DISPLAY_VER(dev_priv) != 2) {
-		u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+		u32 transconf = intel_de_read(dev_priv,
+					      TRANSCONF(dev_priv, cpu_transcoder));
 
-		intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
+		intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
 			       transconf | TRANSCONF_FORCE_BORDER);
-		intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+		intel_de_posting_read(dev_priv,
+				      TRANSCONF(dev_priv, cpu_transcoder));
 		/* Wait for next Vblank to substitue
 		 * border color for Color info */
 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
@@ -738,7 +740,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 			connector_status_connected :
 			connector_status_disconnected;
 
-		intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
+		intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+			       transconf);
 	} else {
 		bool restore_vblank = false;
 		int count, detect;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e2ddae5ba94..9434eba91839 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -307,7 +307,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 
 		/* Wait for the Pipe State to go off */
-		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
+		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
 					    TRANSCONF_STATE_ENABLE, 100))
 			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 	} else {
@@ -329,7 +329,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 	if (wakeref) {
-		u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+		u32 val = intel_de_read(dev_priv,
+					TRANSCONF(dev_priv, cpu_transcoder));
 		cur_state = !!(val & TRANSCONF_ENABLE);
 
 		intel_display_power_put(dev_priv, power_domain, wakeref);
@@ -453,7 +454,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 			     clear, set);
 	}
 
-	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 	if (val & TRANSCONF_ENABLE) {
 		/* we keep both pipes enabled on 830 */
 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
@@ -468,9 +469,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
 	}
 
-	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
 		       val | TRANSCONF_ENABLE);
-	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 
 	/*
 	 * Until the pipe starts PIPEDSL reads will return a stale value,
@@ -499,7 +500,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 	 */
 	assert_planes_disabled(crtc);
 
-	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 	if ((val & TRANSCONF_ENABLE) == 0)
 		return;
 
@@ -519,7 +520,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 	    old_crtc_state->dsc.compression_enable)
 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 
-	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
 
 	if (DISPLAY_VER(dev_priv) >= 12)
 		intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
@@ -2799,9 +2800,11 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 
 	if (DISPLAY_VER(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
+		return intel_de_read(dev_priv,
+				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
 	else
-		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
+		return intel_de_read(dev_priv,
+				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
 }
 
 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
@@ -2952,8 +2955,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 
-	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
-	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 }
 
 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
@@ -3035,7 +3038,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	ret = false;
 
-	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+	tmp = intel_de_read(dev_priv,
+			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
 	if (!(tmp & TRANSCONF_ENABLE))
 		goto out;
 
@@ -3182,8 +3186,8 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
 
-	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
-	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 }
 
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
@@ -3212,8 +3216,8 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
 		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
 
-	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
-	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
 }
 
 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
@@ -3408,7 +3412,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->shared_dpll = NULL;
 
 	ret = false;
-	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+	tmp = intel_de_read(dev_priv,
+			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
 	if (!(tmp & TRANSCONF_ENABLE))
 		goto out;
 
@@ -3721,7 +3726,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 			pipe_config->pch_pfit.force_thru = true;
 	}
 
-	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+	tmp = intel_de_read(dev_priv,
+			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
 
 	return tmp & TRANSCONF_ENABLE;
 }
@@ -3827,7 +3833,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 
 	if (IS_HASWELL(dev_priv)) {
 		u32 tmp = intel_de_read(dev_priv,
-					TRANSCONF(pipe_config->cpu_transcoder));
+					TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
 
 		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
@@ -8238,8 +8244,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 		udelay(150); /* wait for warmup */
 	}
 
-	intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
-	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
 
 	intel_wait_for_pipe_scanline_moving(crtc);
 }
@@ -8262,8 +8268,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
 	drm_WARN_ON(&dev_priv->drm,
 		    intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
 
-	intel_de_write(dev_priv, TRANSCONF(pipe), 0);
-	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
+	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
+	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
 
 	intel_wait_for_pipe_scanline_stopped(crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 3b6cb237d80a..919f712fef13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1044,9 +1044,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
-	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
+	if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
 		i830_enable_pipe(dev_priv, PIPE_A);
-	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
+	if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
 		i830_enable_pipe(dev_priv, PIPE_B);
 }
 
@@ -1060,8 +1060,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
-	return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
-		intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
+	return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
+		intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
 }
 
 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 597f8bd6aa1a..5250622f1479 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -85,7 +85,7 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,
 	else
 		bit = TRANSCONF_REFRESH_RATE_ALT_ILK;
 
-	intel_de_rmw(dev_priv, TRANSCONF(cpu_transcoder),
+	intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
 		     bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 295a0f24ebbf..8b17b8ad71c3 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -1034,7 +1034,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
 	temp = intel_de_read(dev_priv, reg);
 	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
 	temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
-	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
+	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
 	intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
 
 	intel_de_posting_read(dev_priv, reg);
@@ -1090,7 +1090,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
 	reg = FDI_RX_CTL(pipe);
 	temp = intel_de_read(dev_priv, reg);
 	temp &= ~(0x7 << 16);
-	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
+	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
 	intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
 
 	intel_de_posting_read(dev_priv, reg);
@@ -1116,7 +1116,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
 	}
 	/* BPC in FDI rx is consistent with that in TRANSCONF */
 	temp &= ~(0x07 << 16);
-	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
+	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
 	intel_de_write(dev_priv, reg, temp);
 
 	intel_de_posting_read(dev_priv, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 6a45bc1651c3..0d48b9bec29c 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -271,7 +271,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 
 	reg = PCH_TRANSCONF(pipe);
 	val = intel_de_read(dev_priv, reg);
-	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe));
+	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
 
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* Configure frame start delay to match the CPU */
@@ -413,7 +413,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 	    intel_crtc_has_dp_encoder(crtc_state)) {
 		const struct drm_display_mode *adjusted_mode =
 			&crtc_state->hw.adjusted_mode;
-		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5;
+		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
 		enum port port;
 
@@ -557,7 +557,8 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
 
 	val = TRANS_ENABLE;
-	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+	pipeconf_val = intel_de_read(dev_priv,
+				     TRANSCONF(dev_priv, cpu_transcoder));
 
 	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
 		val |= TRANS_INTERLACE_INTERLACED;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index ee9923c7b115..eae5b5e09aa8 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -972,7 +972,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 		 */
 		if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 		    port == PORT_C)
-			enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
+			enabled = intel_de_read(display,
+						TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
 
 		/* Try command mode if video mode not enabled */
 		if (!enabled) {
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index eaa92d392189..ad21b8f65d6b 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 
-	if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE))
+	if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
 		return 0;
 
 	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
@@ -83,7 +83,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 			pipe < PIPE_A || pipe >= I915_MAX_PIPES))
 		return -EINVAL;
 
-	if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE)
+	if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE)
 		return 1;
 
 	if (edp_pipe_is_enabled(vgpu) &&
@@ -191,7 +191,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
 
 		for_each_pipe(dev_priv, pipe) {
-			vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &=
+			vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &=
 				~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
 			vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;
 			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
@@ -252,8 +252,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
 		 *   setup_virtual_dp_monitor.
 		 */
-		vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
-		vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
+		vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
+		vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
 
 		/*
 		 * Golden M/N are calculated based on:
@@ -510,7 +510,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;
 	}
 
-	vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
+	vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
 }
 
 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 00cf35a9669e..039d2cb273df 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2270,10 +2270,14 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
 
 	/* display */
-	MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write);
-	MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write);
-	MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write);
-	MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write);
+	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,
+		pipeconf_mmio_write);
+	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,
+		pipeconf_mmio_write);
+	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,
+		pipeconf_mmio_write);
+	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,
+		pipeconf_mmio_write);
 	MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
 	MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
 		reg50080_mmio_write);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd6eda1b6bef..72f5140cf109 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1876,7 +1876,7 @@
 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
 
-#define TRANSCONF(trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
+#define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
 #define PIPEDSL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
 #define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 600e89148f77..436d4a2eccd7 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -130,10 +130,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPEDSL(PIPE_B));
 	MMIO_D(PIPEDSL(PIPE_C));
 	MMIO_D(PIPEDSL(_PIPE_EDP));
-	MMIO_D(TRANSCONF(TRANSCODER_A));
-	MMIO_D(TRANSCONF(TRANSCODER_B));
-	MMIO_D(TRANSCONF(TRANSCODER_C));
-	MMIO_D(TRANSCONF(TRANSCODER_EDP));
+	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
+	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
+	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
+	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPESTAT(PIPE_A));
 	MMIO_D(PIPESTAT(PIPE_B));
 	MMIO_D(PIPESTAT(PIPE_C));
-- 
2.39.2

[PATCH 19/65] drm/i915: pass dev_priv explicitly to PIPEDSL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPEDSL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c    | 6 +++---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 3 ++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 7 ++++---
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
 5 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index d4f16d894eda..835c8b844494 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -771,9 +771,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 		/*
 		 * Wait for the border to be displayed
 		 */
-		while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
+		while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
 			;
-		while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
+		while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
 			;
 		/*
 		 * Watch ST00 for an entire scanline
@@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 			st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
 			if (st00 & (1 << 4))
 				detect++;
-		} while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
+		} while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
 
 		/* restore vblank if necessary */
 		if (restore_vblank)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 06ec9ce7fe1c..7704ead5002d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1476,7 +1476,8 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
 	int ret;
 
 	for (;;) {
-		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
+		scanline = intel_de_read(dev_priv,
+					 PIPEDSL(dev_priv, crtc->pipe));
 		if (scanline > 100 && scanline < 200)
 			break;
 		usleep_range(25, 50);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index eb80952b0cfd..e2d20064e68d 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -247,7 +247,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 
 	vtotal = intel_mode_vtotal(mode);
 
-	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
+	position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
 
 	/*
 	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
@@ -266,7 +266,8 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 
 		for (i = 0; i < 100; i++) {
 			udelay(1);
-			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
+			temp = intel_de_read_fw(dev_priv,
+						PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
 			if (temp != position) {
 				position = temp;
 				break;
@@ -473,7 +474,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
-	i915_reg_t reg = PIPEDSL(pipe);
+	i915_reg_t reg = PIPEDSL(dev_priv, pipe);
 	u32 line1, line2;
 
 	line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 72f5140cf109..fbd004bd1992 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1877,7 +1877,7 @@
 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
 
 #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
-#define PIPEDSL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
+#define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
 #define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
 #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 436d4a2eccd7..6a37f790c753 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -126,10 +126,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(_MMIO(0x650b4));
 	MMIO_D(_MMIO(0xc4040));
 	MMIO_D(DERRMR);
-	MMIO_D(PIPEDSL(PIPE_A));
-	MMIO_D(PIPEDSL(PIPE_B));
-	MMIO_D(PIPEDSL(PIPE_C));
-	MMIO_D(PIPEDSL(_PIPE_EDP));
+	MMIO_D(PIPEDSL(dev_priv, PIPE_A));
+	MMIO_D(PIPEDSL(dev_priv, PIPE_B));
+	MMIO_D(PIPEDSL(dev_priv, PIPE_C));
+	MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
-- 
2.39.2

[PATCH 20/65] drm/i915: pass dev_priv explicitly to PIPEFRAME

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPEFRAME register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index e2d20064e68d..ac8ad3ebf4a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -102,7 +102,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 	 * we get a low value that's stable across two reads of the high
 	 * register.
 	 */
-	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe));
+	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe),
+				     PIPEFRAME(dev_priv, pipe));
 
 	pixel = frame & PIPE_PIXEL_MASK;
 	frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbd004bd1992..c4f8c50f61d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1878,7 +1878,7 @@
 
 #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
 #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
-#define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
+#define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
 #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
 #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
 
-- 
2.39.2

[PATCH 21/65] drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPEFRAMEPIXEL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index ac8ad3ebf4a4..c6e68c0604b3 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -102,7 +102,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 	 * we get a low value that's stable across two reads of the high
 	 * register.
 	 */
-	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe),
+	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
 				     PIPEFRAME(dev_priv, pipe));
 
 	pixel = frame & PIPE_PIXEL_MASK;
@@ -386,7 +386,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 		 * We can split this into vertical and horizontal
 		 * scanout position.
 		 */
-		position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
+		position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 
 		/* convert to pixel counts */
 		vbl_start *= htotal;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4f8c50f61d4..a6dff480bd0b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1879,7 +1879,7 @@
 #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
 #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
 #define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
-#define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
+#define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
 #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
 
 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
-- 
2.39.2

[PATCH 22/65] drm/i915: pass dev_priv explicitly to PIPESTAT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPESTAT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c   | 9 +++++----
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h                    | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c        | 8 ++++----
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index be5b48861baf..76bba95410e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -224,7 +224,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, u32 status_mask)
 {
-	i915_reg_t reg = PIPESTAT(pipe);
+	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
 	u32 enable_mask;
 
 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -247,7 +247,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, u32 status_mask)
 {
-	i915_reg_t reg = PIPESTAT(pipe);
+	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
 	u32 enable_mask;
 
 	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
@@ -400,7 +400,8 @@ void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
 	enum pipe pipe;
 
 	for_each_pipe(dev_priv, pipe) {
-		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
+		intel_uncore_write(&dev_priv->uncore,
+				   PIPESTAT(dev_priv, pipe),
 				   PIPESTAT_INT_STATUS_MASK |
 				   PIPE_FIFO_UNDERRUN_STATUS);
 
@@ -453,7 +454,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 		if (!status_mask)
 			continue;
 
-		reg = PIPESTAT(pipe);
+		reg = PIPESTAT(dev_priv, pipe);
 		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
 		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
 
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 09a7fa6c0c37..401726f466c0 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -94,7 +94,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
 static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	i915_reg_t reg = PIPESTAT(crtc->pipe);
+	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
 	u32 enable_mask;
 
 	lockdep_assert_held(&dev_priv->irq_lock);
@@ -115,7 +115,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 					     bool enable, bool old)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	i915_reg_t reg = PIPESTAT(pipe);
+	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6dff480bd0b..0aaceedf77dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1880,7 +1880,7 @@
 #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
 #define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
 #define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
-#define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
+#define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
 
 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
 #define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 6a37f790c753..00ee588fab39 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -134,10 +134,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
 	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPESTAT(PIPE_A));
-	MMIO_D(PIPESTAT(PIPE_B));
-	MMIO_D(PIPESTAT(PIPE_C));
-	MMIO_D(PIPESTAT(_PIPE_EDP));
+	MMIO_D(PIPESTAT(dev_priv, PIPE_A));
+	MMIO_D(PIPESTAT(dev_priv, PIPE_B));
+	MMIO_D(PIPESTAT(dev_priv, PIPE_C));
+	MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A));
 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
-- 
2.39.2

[PATCH 23/65] drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_ARB_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9434eba91839..48ee8aee21be 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -439,7 +439,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 
 	/* Wa_22012358565:adl-p */
 	if (DISPLAY_VER(dev_priv) == 13)
-		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
+		intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
 			     0, PIPE_ARB_USE_PROG_SLOTS);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0aaceedf77dc..1b2c0d650bff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1883,7 +1883,7 @@
 #define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
 
 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
-#define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
+#define PIPE_ARB_CTL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
 #define   PIPE_ARB_USE_PROG_SLOTS	REG_BIT(13)
 
 #define _PIPE_MISC_A			0x70030
-- 
2.39.2

[PATCH 24/65] drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ICL_PIPESTATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 9 ++++++---
 drivers/gpu/drm/i915/i915_reg.h                    | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 401726f466c0..e5e4ca7cc499 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -209,7 +209,8 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
 
 	if (enable) {
 		if (DISPLAY_VER(dev_priv) >= 11)
-			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),
+			intel_de_write(dev_priv,
+				       ICL_PIPESTATUS(dev_priv, pipe),
 				       icl_pipe_status_underrun_mask(dev_priv));
 
 		bdw_enable_pipe_irq(dev_priv, pipe, mask);
@@ -418,9 +419,11 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 	 * the underrun was caused by the downstream port.
 	 */
 	if (DISPLAY_VER(dev_priv) >= 11) {
-		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
+		underruns = intel_de_read(dev_priv,
+					  ICL_PIPESTATUS(dev_priv, pipe)) &
 			icl_pipe_status_underrun_mask(dev_priv);
-		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
+		intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe),
+			       underruns);
 	}
 
 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b2c0d650bff..cbe109973f57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1927,7 +1927,7 @@
 #define PIPE_MISC2(pipe)		_MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
 
 #define _ICL_PIPE_A_STATUS			0x70058
-#define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
+#define ICL_PIPESTATUS(dev_priv, pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
 #define   PIPE_STATUS_UNDERRUN				REG_BIT(31)
 #define   PIPE_STATUS_SOFT_UNDERRUN_XELPD		REG_BIT(28)
 #define   PIPE_STATUS_HARD_UNDERRUN_XELPD		REG_BIT(27)
-- 
2.39.2

[PATCH 25/65] drm/i915: pass dev_priv explicitly to DSPARB

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPARB register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 22 ++++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h        |  2 +-
 drivers/gpu/drm/i915/i915_suspend.c    |  6 ++++--
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 628e7192ebc9..fd14010b4cc3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 
 	switch (pipe) {
 	case PIPE_A:
-		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb = intel_uncore_read(&dev_priv->uncore,
+					   DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 		break;
 	case PIPE_B:
-		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb = intel_uncore_read(&dev_priv->uncore,
+					   DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
@@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x7f;
@@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x1ff;
@@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x7f;
@@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 
 	switch (crtc->pipe) {
 	case PIPE_A:
-		dsparb = intel_uncore_read_fw(uncore, DSPARB);
+		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
 
 		dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
@@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
 			   VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
 
-		intel_uncore_write_fw(uncore, DSPARB, dsparb);
+		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
 		break;
 	case PIPE_B:
-		dsparb = intel_uncore_read_fw(uncore, DSPARB);
+		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
 
 		dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
@@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
 			   VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
 
-		intel_uncore_write_fw(uncore, DSPARB, dsparb);
+		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
 		break;
 	case PIPE_C:
@@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		break;
 	}
 
-	intel_uncore_posting_read_fw(uncore, DSPARB);
+	intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
 
 	spin_unlock(&uncore->lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbe109973f57..75223b8cb575 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1984,7 +1984,7 @@
 #define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
 #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
 
-#define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
+#define DSPARB(dev_priv)			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 81def10eb58f..bc449613c848 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration control */
 	if (GRAPHICS_VER(dev_priv) <= 4)
-		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
+		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
+							     DSPARB(dev_priv));
 
 	if (GRAPHICS_VER(dev_priv) == 4)
 		pci_read_config_word(pdev, GCDGMBUS,
@@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration */
 	if (GRAPHICS_VER(dev_priv) <= 4)
-		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
+		intel_de_write(dev_priv, DSPARB(dev_priv),
+			       dev_priv->regfile.saveDSPARB);
 
 	intel_vga_redisable(dev_priv);
 
-- 
2.39.2

[PATCH 26/65] drm/i915: pass dev_priv explicitly to DSPFW1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPFW1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 25 +++++++++++++------------
 drivers/gpu/drm/i915/i915_reg.h        |  2 +-
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index fd14010b4cc3..e39415fb1c19 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -657,10 +657,10 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 					&pnv_display_wm,
 					pnv_display_wm.fifo_size,
 					cpp, latency->display_sr);
-		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
 		reg &= ~DSPFW_SR_MASK;
 		reg |= FW_WM(wm, SR);
-		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), reg);
 		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 
 		/* cursor SR */
@@ -720,7 +720,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 	for_each_pipe(dev_priv, pipe)
 		trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm);
 
-	intel_uncore_write(&dev_priv->uncore, DSPFW1,
+	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
 			   FW_WM(wm->sr.plane, SR) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
@@ -738,7 +738,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 			   FW_WM(wm->hpll.plane, HPLL_SR));
 
-	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
+	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
 }
 
 #define FW_WM_VLV(value, plane) \
@@ -770,7 +770,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
 	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
 
-	intel_uncore_write(&dev_priv->uncore, DSPFW1,
+	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
 			   FW_WM(wm->sr.plane, SR) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
@@ -817,7 +817,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 				   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
 	}
 
-	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
+	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
 }
 
 #undef FW_WM_VLV
@@ -2067,10 +2067,11 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
 		    srwm);
 
 	/* 965 has limitations... */
-	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
-		   FW_WM(8, CURSORB) |
-		   FW_WM(8, PLANEB) |
-		   FW_WM(8, PLANEA));
+	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
+		           FW_WM(srwm, SR) |
+		           FW_WM(8, CURSORB) |
+		           FW_WM(8, PLANEB) |
+		           FW_WM(8, PLANEA));
 	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
 		   FW_WM(8, PLANEC_OLD));
 	/* update cursor SR watermark */
@@ -3521,7 +3522,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
 {
 	u32 tmp;
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
 	wm->sr.plane = _FW_WM(tmp, SR);
 	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
@@ -3561,7 +3562,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
 	}
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
 	wm->sr.plane = _FW_WM(tmp, SR);
 	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75223b8cb575..5f1db52ee773 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2019,7 +2019,7 @@
 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
 
 /* pnv/gen4/g4x/vlv/chv */
-#define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
+#define DSPFW1(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
 #define   DSPFW_SR_SHIFT		23
 #define   DSPFW_SR_MASK			(0x1ff << 23)
 #define   DSPFW_CURSORB_SHIFT		16
-- 
2.39.2

[PATCH 27/65] drm/i915: pass dev_priv explicitly to DSPFW2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPFW2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 13 +++++++------
 drivers/gpu/drm/i915/i915_reg.h        |  2 +-
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index e39415fb1c19..1e11d66d1a7e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -725,7 +725,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-	intel_uncore_write(&dev_priv->uncore, DSPFW2,
+	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
 			   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 			   FW_WM(wm->sr.fbc, FBC_SR) |
 			   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
@@ -775,7 +775,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-	intel_uncore_write(&dev_priv->uncore, DSPFW2,
+	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
 			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
@@ -2072,8 +2072,9 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
 		           FW_WM(8, CURSORB) |
 		           FW_WM(8, PLANEB) |
 		           FW_WM(8, PLANEA));
-	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
-		   FW_WM(8, PLANEC_OLD));
+	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
+		           FW_WM(8, CURSORA) |
+		           FW_WM(8, PLANEC_OLD));
 	/* update cursor SR watermark */
 	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
 
@@ -3528,7 +3529,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
 	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
 	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
 	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
 	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
@@ -3568,7 +3569,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
 	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
 	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f1db52ee773..8b642cb0d9b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2030,7 +2030,7 @@
 #define   DSPFW_PLANEA_SHIFT		0
 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
-#define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
+#define DSPFW2(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
 #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
 #define   DSPFW_FBC_SR_SHIFT		28
 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
-- 
2.39.2

[PATCH 28/65] drm/i915: pass dev_priv explicitly to DSPFW3

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPFW3 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        | 27 ++++++++++---------
 .../drm/i915/display/intel_display_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               |  2 +-
 3 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 1e11d66d1a7e..3fe24bae0728 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -149,14 +149,14 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
 		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 	} else if (IS_PINEVIEW(dev_priv)) {
-		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
+		val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
 		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 		if (enable)
 			val |= PINEVIEW_SELF_REFRESH_EN;
 		else
 			val &= ~PINEVIEW_SELF_REFRESH_EN;
-		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
-		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), val);
+		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3(dev_priv));
 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
@@ -668,7 +668,8 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 					&pnv_cursor_wm,
 					pnv_display_wm.fifo_size,
 					4, latency->cursor_sr);
-		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK,
+		intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
+				 DSPFW_CURSOR_SR_MASK,
 				 FW_WM(wm, CURSOR_SR));
 
 		/* Display HPLL off SR */
@@ -676,17 +677,18 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
 					&pnv_display_hplloff_wm,
 					pnv_display_hplloff_wm.fifo_size,
 					cpp, latency->display_hpll_disable);
-		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
+		intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
+				 DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
 
 		/* cursor HPLL off SR */
 		wm = intel_calculate_wm(dev_priv, pixel_rate,
 					&pnv_cursor_hplloff_wm,
 					pnv_display_hplloff_wm.fifo_size,
 					4, latency->cursor_hpll_disable);
-		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
+		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
 		reg &= ~DSPFW_HPLL_CURSOR_MASK;
 		reg |= FW_WM(wm, HPLL_CURSOR);
-		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
+		intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
 		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 
 		intel_set_memory_cxsr(dev_priv, true);
@@ -732,7 +734,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
-	intel_uncore_write(&dev_priv->uncore, DSPFW3,
+	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
 			   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 			   FW_WM(wm->sr.cursor, CURSOR_SR) |
 			   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
@@ -779,7 +781,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
-	intel_uncore_write(&dev_priv->uncore, DSPFW3,
+	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
 			   FW_WM(wm->sr.cursor, CURSOR_SR));
 
 	if (IS_CHERRYVIEW(dev_priv)) {
@@ -2076,7 +2078,8 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
 		           FW_WM(8, CURSORA) |
 		           FW_WM(8, PLANEC_OLD));
 	/* update cursor SR watermark */
-	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
+	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
+		           FW_WM(cursor_sr, CURSOR_SR));
 
 	if (cxsr_enabled)
 		intel_set_memory_cxsr(dev_priv, true);
@@ -3537,7 +3540,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
 	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
 	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
 	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
 	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
@@ -3574,7 +3577,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
 	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
 	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
 
-	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
+	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
 	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 86d9900c40af..b538a8204124 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -77,7 +77,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	else if (IS_I915GM(dev_priv))
 		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+		sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b642cb0d9b7..05e0013813f8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2046,7 +2046,7 @@
 #define   DSPFW_SPRITEA_SHIFT		0
 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
-#define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
+#define DSPFW3(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
 #define   DSPFW_HPLL_SR_EN		(1 << 31)
 #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
 #define   DSPFW_CURSOR_SR_SHIFT		24
-- 
2.39.2

[PATCH 29/65] drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_FRMCOUNT_G4X register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 drivers/gpu/drm/i915/gvt/display.c          | 2 +-
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index c6e68c0604b3..4f3b80cd1674 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -125,7 +125,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 	if (!vblank->max_vblank_count)
 		return 0;
 
-	return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe));
+	return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
 }
 
 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index ad21b8f65d6b..3681dca165c6 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -647,7 +647,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
 	}
 
 	if (pipe_is_enabled(vgpu, pipe)) {
-		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
+		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++;
 		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05e0013813f8..d62da57afda7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2257,7 +2257,7 @@
 /* GM45+ just has to be different */
 #define _PIPEA_FRMCOUNT_G4X	0x70040
 #define _PIPEA_FLIPCOUNT_G4X	0x70044
-#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
+#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
 
 /* CHV pipe B blender */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 00ee588fab39..2e027f3ee750 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -142,10 +142,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
 	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
 	MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP));
-	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A));
-	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B));
-	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C));
-	MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP));
+	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
+	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
+	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
+	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));
 	MMIO_D(CURCNTR(dev_priv, PIPE_A));
 	MMIO_D(CURCNTR(dev_priv, PIPE_B));
 	MMIO_D(CURCNTR(dev_priv, PIPE_C));
-- 
2.39.2

[PATCH 30/65] drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_FLIPCOUNT_G4X register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c       | 2 +-
 drivers/gpu/drm/i915/gvt/handlers.c         | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h             | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 9cdb53015d16..2f4c9c66b40b 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1437,7 +1437,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
 	}
 
 	if (info->plane == PLANE_PRIMARY)
-		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
+		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
 
 	if (info->async_flip)
 		intel_vgpu_trigger_virtual_event(vgpu, info->event);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 039d2cb273df..bb904266c3cd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1021,7 +1021,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	write_vreg(vgpu, offset, p_data, bytes);
 	vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
 
-	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
+	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
 
 	if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP)
 		intel_vgpu_trigger_virtual_event(vgpu, event);
@@ -1063,7 +1063,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu,
 	write_vreg(vgpu, offset, p_data, bytes);
 	if (plane == PLANE_PRIMARY) {
 		vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
-		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
+		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
 	} else {
 		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d62da57afda7..5d9429bf17a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2258,7 +2258,7 @@
 #define _PIPEA_FRMCOUNT_G4X	0x70040
 #define _PIPEA_FLIPCOUNT_G4X	0x70044
 #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
-#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
+#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
 
 /* CHV pipe B blender */
 #define _CHV_BLEND_A		0x60a00
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 2e027f3ee750..ba3f734ced0b 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -138,10 +138,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPESTAT(dev_priv, PIPE_B));
 	MMIO_D(PIPESTAT(dev_priv, PIPE_C));
 	MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
-	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A));
-	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
-	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
-	MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP));
+	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A));
+	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B));
+	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C));
+	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP));
 	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
 	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
 	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
-- 
2.39.2

[PATCH 31/65] drm/i915: pass dev_priv explicitly to CHV_BLEND

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CHV_BLEND register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 48ee8aee21be..a6d7928fbe37 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2108,7 +2108,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
 
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
-		intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
+		intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
+			       CHV_BLEND_LEGACY);
 		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d9429bf17a8..ddfa77231426 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2271,7 +2271,7 @@
 #define   CHV_CANVAS_GREEN_MASK	REG_GENMASK(19, 10)
 #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
 
-#define CHV_BLEND(pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
+#define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
 #define CHV_CANVAS(pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
 
 /* Display/Sprite base address macros */
-- 
2.39.2

[PATCH 32/65] drm/i915: pass dev_priv explicitly to CHV_CANVAS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CHV_CANVAS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a6d7928fbe37..241121b0b3ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2110,7 +2110,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
 		intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
 			       CHV_BLEND_LEGACY);
-		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
+		intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0);
 	}
 
 	crtc->active = true;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddfa77231426..8aa35bbb2e1b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2272,7 +2272,7 @@
 #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
 
 #define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
-#define CHV_CANVAS(pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
+#define CHV_CANVAS(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
 
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK	(0xfffff000)
-- 
2.39.2

[PATCH 33/65] drm/i915: pass dev_priv explicitly to SWF0

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the SWF0 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8aa35bbb2e1b..8b379ff60070 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2290,7 +2290,7 @@
  * [10:1f] all
  * [30:32] all
  */
-#define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
+#define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bc449613c848..ac8221ae97f3 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -40,7 +40,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 	/* Scratch space */
 	if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
-			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
+								      SWF0(dev_priv, i));
 			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 		}
 		for (i = 0; i < 3; i++)
@@ -50,7 +51,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
-			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
+								      SWF0(dev_priv, i));
 			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
 		}
 		for (i = 0; i < 3; i++)
@@ -65,7 +67,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 	/* Scratch space */
 	if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
-			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			intel_de_write(dev_priv, SWF0(dev_priv, i),
+				       dev_priv->regfile.saveSWF0[i]);
 			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
@@ -75,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
-			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
+			intel_de_write(dev_priv, SWF0(dev_priv, i),
+				       dev_priv->regfile.saveSWF0[i]);
 			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
-- 
2.39.2

[PATCH 34/65] drm/i915: pass dev_priv explicitly to SWF1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the SWF1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/i915_suspend.c | 18 ++++++++++++------
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b379ff60070..81f1b491d7af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2291,7 +2291,7 @@
  * [30:32] all
  */
 #define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
-#define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
+#define SWF1(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index ac8221ae97f3..8a71c1f52cb4 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -42,18 +42,21 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 		for (i = 0; i < 7; i++) {
 			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
 								      SWF0(dev_priv, i));
-			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
+								      SWF1(dev_priv, i));
 		}
 		for (i = 0; i < 3; i++)
 			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
 	} else if (GRAPHICS_VER(dev_priv) == 2) {
 		for (i = 0; i < 7; i++)
-			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
+								      SWF1(dev_priv, i));
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
 			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
 								      SWF0(dev_priv, i));
-			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
+								      SWF1(dev_priv, i));
 		}
 		for (i = 0; i < 3; i++)
 			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
@@ -69,18 +72,21 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 		for (i = 0; i < 7; i++) {
 			intel_de_write(dev_priv, SWF0(dev_priv, i),
 				       dev_priv->regfile.saveSWF0[i]);
-			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF1(dev_priv, i),
+				       dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
 			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
 	} else if (GRAPHICS_VER(dev_priv) == 2) {
 		for (i = 0; i < 7; i++)
-			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF1(dev_priv, i),
+				       dev_priv->regfile.saveSWF1[i]);
 	} else if (HAS_GMCH(dev_priv)) {
 		for (i = 0; i < 16; i++) {
 			intel_de_write(dev_priv, SWF0(dev_priv, i),
 				       dev_priv->regfile.saveSWF0[i]);
-			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
+			intel_de_write(dev_priv, SWF1(dev_priv, i),
+				       dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
 			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
-- 
2.39.2

[PATCH 35/65] drm/i915: pass dev_priv explicitly to SWF3

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the SWF3 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1b491d7af..2f942882e7ed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2292,7 +2292,7 @@
  */
 #define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
 #define SWF1(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
-#define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
+#define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
 /* Pipe B */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8a71c1f52cb4..f8373a461f17 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -46,7 +46,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 								      SWF1(dev_priv, i));
 		}
 		for (i = 0; i < 3; i++)
-			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv,
+								      SWF3(dev_priv, i));
 	} else if (GRAPHICS_VER(dev_priv) == 2) {
 		for (i = 0; i < 7; i++)
 			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
@@ -59,7 +60,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
 								      SWF1(dev_priv, i));
 		}
 		for (i = 0; i < 3; i++)
-			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv,
+								      SWF3(dev_priv, i));
 	}
 }
 
@@ -76,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 				       dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
-			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
+			intel_de_write(dev_priv, SWF3(dev_priv, i),
+				       dev_priv->regfile.saveSWF3[i]);
 	} else if (GRAPHICS_VER(dev_priv) == 2) {
 		for (i = 0; i < 7; i++)
 			intel_de_write(dev_priv, SWF1(dev_priv, i),
@@ -89,7 +92,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
 				       dev_priv->regfile.saveSWF1[i]);
 		}
 		for (i = 0; i < 3; i++)
-			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
+			intel_de_write(dev_priv, SWF3(dev_priv, i),
+				       dev_priv->regfile.saveSWF3[i]);
 	}
 }
 
-- 
2.39.2

[PATCH 36/65] drm/i915: pass dev_priv explicitly to _PIPEBDSL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _PIPEBDSL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f942882e7ed..0a2111b0cd98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2296,7 +2296,7 @@
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
 /* Pipe B */
-#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
+#define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
 #define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
-- 
2.39.2

[PATCH 37/65] drm/i915: pass dev_priv explicitly to _TRANSBCONF

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _TRANSBCONF register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a2111b0cd98..8dd4b5a72b22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2297,7 +2297,7 @@
 
 /* Pipe B */
 #define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
-#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
+#define _TRANSBCONF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-- 
2.39.2

[PATCH 38/65] drm/i915: pass dev_priv explicitly to _PIPEBSTAT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _PIPEBSTAT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8dd4b5a72b22..0bbe2f8aff4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2298,7 +2298,7 @@
 /* Pipe B */
 #define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
 #define _TRANSBCONF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
-#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
+#define _PIPEBSTAT(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
-- 
2.39.2

[PATCH 39/65] drm/i915: pass dev_priv explicitly to _PIPEB_FRMCOUNT_G4X

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _PIPEB_FRMCOUNT_G4X register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bbe2f8aff4b..f5367ec58400 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2301,7 +2301,7 @@
 #define _PIPEBSTAT(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
-#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
+#define _PIPEB_FRMCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
 
 
-- 
2.39.2

[PATCH 40/65] drm/i915: pass dev_priv explicitly to _PIPEB_FLIPCOUNT_G4X

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _PIPEB_FLIPCOUNT_G4X register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5367ec58400..fb1dc6f5e903 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2302,7 +2302,7 @@
 #define _PIPEBFRAMEHIGH		0x71040
 #define _PIPEBFRAMEPIXEL	0x71044
 #define _PIPEB_FRMCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
-#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
+#define _PIPEB_FLIPCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
 
 
 /* Display B control */
-- 
2.39.2

[PATCH 41/65] drm/i915: pass dev_priv explicitly to _DSPBCNTR

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBCNTR register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb1dc6f5e903..8390294aea5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2306,7 +2306,7 @@
 
 
 /* Display B control */
-#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
+#define _DSPBCNTR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
 #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
-- 
2.39.2

[PATCH 42/65] drm/i915: pass dev_priv explicitly to _DSPBADDR

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBADDR register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8390294aea5b..bcaa7c5b0c40 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2309,7 +2309,7 @@
 #define _DSPBCNTR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
 #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
-#define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
+#define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
-- 
2.39.2

[PATCH 43/65] drm/i915: pass dev_priv explicitly to _DSPBSTRIDE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBSTRIDE register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcaa7c5b0c40..7fd2d5e07b48 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2310,7 +2310,7 @@
 #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
 #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
-#define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
+#define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
-- 
2.39.2

[PATCH 44/65] drm/i915: pass dev_priv explicitly to _DSPBPOS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBPOS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7fd2d5e07b48..38c8b98d95c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2311,7 +2311,7 @@
 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
 #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
 #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
-#define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
+#define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-- 
2.39.2

[PATCH 45/65] drm/i915: pass dev_priv explicitly to _DSPBSIZE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBSIZE register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38c8b98d95c3..36ed23b93475 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2312,7 +2312,7 @@
 #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
 #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
 #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
-#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
+#define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-- 
2.39.2

[PATCH 46/65] drm/i915: pass dev_priv explicitly to _DSPBSURF

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBSURF register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index bb904266c3cd..88ef8b7b9ab4 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1009,7 +1009,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
 }
 
 #define DSPSURF_TO_PIPE(offset) \
-	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C))
+	calc_index(offset, _DSPASURF, _DSPBSURF(dev_priv), 0, DSPSURF(dev_priv, PIPE_C))
 
 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		void *p_data, unsigned int bytes)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 36ed23b93475..9bb840895baa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2313,7 +2313,7 @@
 #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
 #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
 #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
-#define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
+#define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
-- 
2.39.2

[PATCH 47/65] drm/i915: pass dev_priv explicitly to _DSPBTILEOFF

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBTILEOFF register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9bb840895baa..7c4251f62411 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2314,7 +2314,7 @@
 #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
 #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
 #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
-#define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
+#define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
 
-- 
2.39.2

[PATCH 48/65] drm/i915: pass dev_priv explicitly to _DSPBOFFSET

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBOFFSET register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c4251f62411..03c7b55e1bd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2315,7 +2315,7 @@
 #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
 #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
 #define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-#define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
+#define _DSPBOFFSET(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
 
 /* ICL DSI 0 and 1 */
-- 
2.39.2

[PATCH 49/65] drm/i915: pass dev_priv explicitly to _DSPBSURFLIVE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _DSPBSURFLIVE register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03c7b55e1bd3..62cb456568e5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2316,7 +2316,7 @@
 #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
 #define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
 #define _DSPBOFFSET(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
-#define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
+#define _DSPBSURFLIVE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
 
 /* ICL DSI 0 and 1 */
 #define _PIPEDSI0CONF		0x7b008
-- 
2.39.2

[PATCH 50/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_M1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_M1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 drivers/gpu/drm/i915/display/intel_fdi.c     | 6 +++---
 drivers/gpu/drm/i915/gvt/display.c           | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 5 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 241121b0b3ff..7fd65e3b018d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2641,7 +2641,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 
 	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_set_m_n(dev_priv, m_n,
-			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+			      PIPE_DATA_M1(dev_priv, transcoder),
+			      PIPE_DATA_N1(transcoder),
 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 	else
 		intel_set_m_n(dev_priv, m_n,
@@ -3337,7 +3338,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 
 	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_get_m_n(dev_priv, m_n,
-			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
+			      PIPE_DATA_M1(dev_priv, transcoder),
+			      PIPE_DATA_N1(transcoder),
 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 	else
 		intel_get_m_n(dev_priv, m_n,
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 8b17b8ad71c3..007e0f9e9304 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -514,7 +514,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
 	 * detection works.
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
-		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
 
 	/* FDI needs bits from pipe first */
 	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
@@ -616,7 +616,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
 	 * detection works.
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
-		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
@@ -754,7 +754,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
 	 * detection works.
 	 */
 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
-		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
 
 	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
 	   for train result */
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 3681dca165c6..ce6f20b1dabc 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -261,8 +261,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   DP link clk 1620 MHz and non-constant_n.
 		 * TODO: calculate DP link symbol clk and stream clk m/n.
 		 */
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
@@ -395,8 +395,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 *   DP link clk 1620 MHz and non-constant_n.
 		 * TODO: calculate DP link symbol clk and stream clk m/n.
 		 */
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
-		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62cb456568e5..96bfa5620989 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2379,7 +2379,7 @@
 #define _PIPEB_LINK_M2		0x61048
 #define _PIPEB_LINK_N2		0x6104c
 
-#define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
+#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index ba3f734ced0b..977d695fbdff 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -266,7 +266,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
+	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
@@ -274,7 +274,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
-	MMIO_D(PIPE_DATA_M1(TRANSCODER_B));
+	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
@@ -282,7 +282,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
-	MMIO_D(PIPE_DATA_M1(TRANSCODER_C));
+	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
@@ -290,7 +290,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
-	MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP));
+	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 51/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_N1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_N1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7fd65e3b018d..5eb4ad261c21 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2642,7 +2642,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_set_m_n(dev_priv, m_n,
 			      PIPE_DATA_M1(dev_priv, transcoder),
-			      PIPE_DATA_N1(transcoder),
+			      PIPE_DATA_N1(dev_priv, transcoder),
 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 	else
 		intel_set_m_n(dev_priv, m_n,
@@ -3339,7 +3339,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 	if (DISPLAY_VER(dev_priv) >= 5)
 		intel_get_m_n(dev_priv, m_n,
 			      PIPE_DATA_M1(dev_priv, transcoder),
-			      PIPE_DATA_N1(transcoder),
+			      PIPE_DATA_N1(dev_priv, transcoder),
 			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
 	else
 		intel_get_m_n(dev_priv, m_n,
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index ce6f20b1dabc..5f3ee57b5982 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -263,7 +263,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 */
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
-		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
+		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 
@@ -397,7 +397,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		 */
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
-		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
+		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96bfa5620989..70c5fe687254 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2380,7 +2380,7 @@
 #define _PIPEB_LINK_N2		0x6104c
 
 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
-#define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
+#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 977d695fbdff..b9ad4eec4740 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -267,7 +267,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
+	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
@@ -275,7 +275,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_DATA_N1(TRANSCODER_B));
+	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
@@ -283,7 +283,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_DATA_N1(TRANSCODER_C));
+	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
@@ -291,7 +291,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP));
+	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 52/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_M2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_M2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5eb4ad261c21..c2a2061a467d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2660,7 +2660,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 		return;
 
 	intel_set_m_n(dev_priv, m_n,
-		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+		      PIPE_DATA_M2(dev_priv, transcoder),
+		      PIPE_DATA_N2(transcoder),
 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 }
 
@@ -3357,7 +3358,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 		return;
 
 	intel_get_m_n(dev_priv, m_n,
-		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
+		      PIPE_DATA_M2(dev_priv, transcoder),
+		      PIPE_DATA_N2(transcoder),
 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70c5fe687254..9c56df4c1f9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2381,7 +2381,7 @@
 
 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
-#define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
+#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index b9ad4eec4740..4199106f7202 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -268,7 +268,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
+	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
@@ -276,7 +276,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
+	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
@@ -284,7 +284,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
+	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
@@ -292,7 +292,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
+	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 53/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_N2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_DATA_N2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c2a2061a467d..7bf5b2559143 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2661,7 +2661,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 
 	intel_set_m_n(dev_priv, m_n,
 		      PIPE_DATA_M2(dev_priv, transcoder),
-		      PIPE_DATA_N2(transcoder),
+		      PIPE_DATA_N2(dev_priv, transcoder),
 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 }
 
@@ -3359,7 +3359,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 
 	intel_get_m_n(dev_priv, m_n,
 		      PIPE_DATA_M2(dev_priv, transcoder),
-		      PIPE_DATA_N2(transcoder),
+		      PIPE_DATA_N2(dev_priv, transcoder),
 		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c56df4c1f9f..465d73ef43e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2382,7 +2382,7 @@
 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
-#define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
+#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 4199106f7202..829196c665c6 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -269,7 +269,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
+	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
@@ -277,7 +277,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
+	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
@@ -285,7 +285,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
+	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
@@ -293,7 +293,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
+	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 54/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_M1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_M1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
 drivers/gpu/drm/i915/gvt/handlers.c          | 2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 5 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7bf5b2559143..a3249d782a8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2643,7 +2643,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 		intel_set_m_n(dev_priv, m_n,
 			      PIPE_DATA_M1(dev_priv, transcoder),
 			      PIPE_DATA_N1(dev_priv, transcoder),
-			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+			      PIPE_LINK_M1(dev_priv, transcoder),
+			      PIPE_LINK_N1(transcoder));
 	else
 		intel_set_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -3341,7 +3342,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 		intel_get_m_n(dev_priv, m_n,
 			      PIPE_DATA_M1(dev_priv, transcoder),
 			      PIPE_DATA_N1(dev_priv, transcoder),
-			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
+			      PIPE_LINK_M1(dev_priv, transcoder),
+			      PIPE_LINK_N1(transcoder));
 	else
 		intel_get_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 5f3ee57b5982..eea956603cc8 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
-		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
+		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 
 		/* Enable per-DDI/PORT vreg */
@@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
-		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
+		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 	}
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 88ef8b7b9ab4..ae5a3e2a5c50 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -673,7 +673,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 		dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
 
 	/* Get DP link symbol clock M/N */
-	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A));
+	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
 	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
 
 	/* Get H/V total from transcoder timing */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 465d73ef43e2..a9f3c4a85318 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2383,7 +2383,7 @@
 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
-#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
+#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 829196c665c6..c08b8e755377 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -270,7 +270,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
+	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
@@ -278,7 +278,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
+	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
@@ -286,7 +286,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
+	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
@@ -294,7 +294,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
+	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
-- 
2.39.2

[PATCH 55/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_N1

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_N1 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
 drivers/gpu/drm/i915/gvt/handlers.c          | 2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a3249d782a8b..eef317984564 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2644,7 +2644,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
 			      PIPE_DATA_M1(dev_priv, transcoder),
 			      PIPE_DATA_N1(dev_priv, transcoder),
 			      PIPE_LINK_M1(dev_priv, transcoder),
-			      PIPE_LINK_N1(transcoder));
+			      PIPE_LINK_N1(dev_priv, transcoder));
 	else
 		intel_set_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
@@ -3343,7 +3343,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
 			      PIPE_DATA_M1(dev_priv, transcoder),
 			      PIPE_DATA_N1(dev_priv, transcoder),
 			      PIPE_LINK_M1(dev_priv, transcoder),
-			      PIPE_LINK_N1(transcoder));
+			      PIPE_LINK_N1(dev_priv, transcoder));
 	else
 		intel_get_m_n(dev_priv, m_n,
 			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index eea956603cc8..95b4b76d3b45 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -265,7 +265,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
-		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
+		vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
 
 		/* Enable per-DDI/PORT vreg */
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
@@ -399,7 +399,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
-		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
+		vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
 	}
 
 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ae5a3e2a5c50..f2af234769bf 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -674,7 +674,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 
 	/* Get DP link symbol clock M/N */
 	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
-	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
+	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
 
 	/* Get H/V total from transcoder timing */
 	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9f3c4a85318..ac9ef4bd176e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2384,7 +2384,7 @@
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
-#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
+#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
 
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c08b8e755377..00ce7147a9b6 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -271,7 +271,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
+	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
@@ -279,7 +279,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
+	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
@@ -287,7 +287,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
+	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
@@ -295,7 +295,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
+	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
 	MMIO_D(PF_CTL(PIPE_A));
-- 
2.39.2

[PATCH 56/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_M2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_M2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eef317984564..9df8e486a86e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2663,7 +2663,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 	intel_set_m_n(dev_priv, m_n,
 		      PIPE_DATA_M2(dev_priv, transcoder),
 		      PIPE_DATA_N2(dev_priv, transcoder),
-		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
+		      PIPE_LINK_M2(dev_priv, transcoder),
+		      PIPE_LINK_N2(transcoder));
 }
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3362,7 +3363,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 	intel_get_m_n(dev_priv, m_n,
 		      PIPE_DATA_M2(dev_priv, transcoder),
 		      PIPE_DATA_N2(dev_priv, transcoder),
-		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
+		      PIPE_LINK_M2(dev_priv, transcoder),
+		      PIPE_LINK_N2(transcoder));
 }
 
 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac9ef4bd176e..2a73ad779e26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2385,7 +2385,7 @@
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
-#define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
+#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
 
 /* CPU panel fitter */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 00ce7147a9b6..d1a51ae042f1 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -272,7 +272,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
+	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
@@ -280,7 +280,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
+	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
@@ -288,7 +288,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
+	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
@@ -296,7 +296,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
+	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
 	MMIO_D(PF_CTL(PIPE_A));
 	MMIO_D(PF_WIN_SZ(PIPE_A));
-- 
2.39.2

[PATCH 57/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_N2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_N2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9df8e486a86e..952780028630 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2664,7 +2664,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
 		      PIPE_DATA_M2(dev_priv, transcoder),
 		      PIPE_DATA_N2(dev_priv, transcoder),
 		      PIPE_LINK_M2(dev_priv, transcoder),
-		      PIPE_LINK_N2(transcoder));
+		      PIPE_LINK_N2(dev_priv, transcoder));
 }
 
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3364,7 +3364,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 		      PIPE_DATA_M2(dev_priv, transcoder),
 		      PIPE_DATA_N2(dev_priv, transcoder),
 		      PIPE_LINK_M2(dev_priv, transcoder),
-		      PIPE_LINK_N2(transcoder));
+		      PIPE_LINK_N2(dev_priv, transcoder));
 }
 
 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a73ad779e26..70e549b38984 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2386,7 +2386,7 @@
 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
 #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
-#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
+#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
 
 /* CPU panel fitter */
 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index d1a51ae042f1..955c9a33212a 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -273,7 +273,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
-	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
+	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
@@ -281,7 +281,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
-	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
+	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
@@ -289,7 +289,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
-	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
+	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));
 	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
@@ -297,7 +297,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
 	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
-	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
+	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));
 	MMIO_D(PF_CTL(PIPE_A));
 	MMIO_D(PF_WIN_SZ(PIPE_A));
 	MMIO_D(PF_WIN_POS(PIPE_A));
-- 
2.39.2

[PATCH 58/65] drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the HSW_STEREO_3D_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70e549b38984..c8488877dd68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3493,7 +3493,7 @@
 #define   S3D_ENABLE			(1 << 31)
 #define _HSW_STEREO_3D_CTL_B		0x71020
 
-#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
+#define HSW_STEREO_3D_CTL(dev_priv, trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
 
 #define _PCH_TRANS_HTOTAL_B          0xe1000
 #define _PCH_TRANS_HBLANK_B          0xe1004
-- 
2.39.2

[PATCH 59/65] drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_DDI_FUNC_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 12 +++++---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 29 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_display.c  |  9 ++++--
 .../gpu/drm/i915/display/intel_display_irq.c  |  3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  5 ++--
 drivers/gpu/drm/i915/display/intel_fdi.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  3 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
 drivers/gpu/drm/i915/gvt/display.c            | 25 +++++++++-------
 drivers/gpu/drm/i915/gvt/handlers.c           |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               |  2 +-
 11 files changed, 58 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9beb94494b2b..acc80d439352 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -796,7 +796,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		dsi_trans = dsi_port_to_transcoder(port);
 
 		/* select data lane width */
-		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
 		tmp &= ~DDI_PORT_WIDTH_MASK;
 		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 
@@ -822,7 +823,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 
 		/* enable DDI buffer */
 		tmp |= TRANS_DDI_FUNC_ENABLE;
-		intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+		intel_de_write(dev_priv,
+			       TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
 	}
 
 	/* wait for link ready */
@@ -1333,7 +1335,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	/* disable ddi function */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-		intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans),
+		intel_de_rmw(dev_priv,
+			     TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
 			     TRANS_DDI_FUNC_ENABLE, 0);
 	}
 
@@ -1697,7 +1700,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		dsi_trans = dsi_port_to_transcoder(port);
-		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 		case TRANS_DDI_EDP_INPUT_A_ON:
 			*pipe = PIPE_A;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c3fc53376ce..c5571be3c66e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -606,7 +606,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 	}
 
-	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
+	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
 		       intel_ddi_transcoder_func_reg_val_get(encoder,
 							     crtc_state));
 }
@@ -626,7 +626,8 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 
 	ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 	ctl &= ~TRANS_DDI_FUNC_ENABLE;
-	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
+	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
+		       ctl);
 }
 
 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
@@ -641,7 +642,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 		intel_de_write(dev_priv,
 			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 
-	ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+	ctl = intel_de_read(dev_priv,
+			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 
 	drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 
@@ -660,7 +662,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 		ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 	}
 
-	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
+	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
+		       ctl);
 
 	if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -684,7 +687,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 	if (drm_WARN_ON(dev, !wakeref))
 		return -ENXIO;
 
-	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
+	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
 		     hdcp_mask, enable ? hdcp_mask : 0);
 	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 	return ret;
@@ -718,7 +721,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 	else
 		cpu_transcoder = (enum transcoder) pipe;
 
-	tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+	tmp = intel_de_read(dev_priv,
+			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 
 	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 	case TRANS_DDI_MODE_SELECT_HDMI:
@@ -782,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 
 	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 		tmp = intel_de_read(dev_priv,
-				    TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
+				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP));
 
 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 		default:
@@ -823,7 +827,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 		}
 
 		tmp = intel_de_read(dev_priv,
-				    TRANS_DDI_FUNC_CTL(cpu_transcoder));
+				    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 		intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 					trans_wakeref);
 
@@ -3025,7 +3029,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 		if (is_mst) {
 			enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 
-			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
+			intel_de_rmw(dev_priv,
+				     TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
 				     TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
 				     0);
 		}
@@ -3759,7 +3764,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de
 
 		master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
 	} else {
-		u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+		u32 ctl = intel_de_read(dev_priv,
+				        TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 
 		if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
 			return INVALID_TRANSCODER;
@@ -3815,7 +3821,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	u32 temp, flags = 0;
 
-	temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+	temp = intel_de_read(dev_priv,
+			     TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 	if (temp & TRANS_DDI_PHSYNC)
 		flags |= DRM_MODE_FLAG_PHSYNC;
 	else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 952780028630..62f8300c73a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3507,7 +3507,8 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
 	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 
 	with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
-		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 
 	return tmp & TRANS_DDI_FUNC_ENABLE;
 }
@@ -3622,7 +3623,8 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
 
 		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
-			tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
+			tmp = intel_de_read(dev_priv,
+					    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
 
 		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
 			continue;
@@ -3729,7 +3731,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 		return false;
 
 	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
-		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
+		tmp = intel_de_read(dev_priv,
+				    TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));
 
 		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
 			pipe_config->pch_pfit.force_thru = true;
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 76bba95410e7..036f77c2702d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -934,7 +934,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	}
 
 	/* Get PIPE for handling VBLANK event */
-	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
+	val = intel_uncore_read(&dev_priv->uncore,
+				TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
 	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
 	case TRANS_DDI_EDP_INPUT_A_ON:
 		pipe = PIPE_A;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 715d2f59f565..00fdcbc28e9b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1009,7 +1009,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 
 	clear_act_sent(encoder, old_crtc_state);
 
-	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
+	intel_de_rmw(dev_priv,
+		     TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),
 		     TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
 
 	wait_for_act_sent(encoder, old_crtc_state);
@@ -1230,7 +1231,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 
 	clear_act_sent(encoder, pipe_config);
 
-	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
+	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0,
 		     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 
 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 007e0f9e9304..d33befd7994d 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -34,7 +34,8 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 		 * so pipe->transcoder cast is fine here.
 		 */
 		enum transcoder cpu_transcoder = (enum transcoder)pipe;
-		cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
+		cur_state = intel_de_read(dev_priv,
+					  TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
 	} else {
 		cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ba3eca919900..3ebe035f382e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -47,7 +47,8 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
 				     0, HDCP_LINE_REKEY_DISABLE);
 		else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
 			 IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
-			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder),
+			intel_de_rmw(dev_priv,
+				     TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder),
 				     0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7704ead5002d..19498ee455fa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -83,7 +83,7 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
 				     enum transcoder cpu_transcoder)
 {
 	drm_WARN(&dev_priv->drm,
-		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
+		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) &
 		 TRANS_DDI_FUNC_ENABLE,
 		 "HDMI transcoder function enabled, expecting disabled\n");
 }
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 95b4b76d3b45..c66d6d3177c8 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -200,11 +200,11 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		}
 
 		for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
-			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
+			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &=
 				~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 				  TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
 		}
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 			  TRANS_DDI_PORT_MASK);
 
@@ -287,7 +287,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 				(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
 				~DDI_BUF_IS_IDLE;
-			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
+			vgpu_vreg_t(vgpu,
+				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |=
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 TRANS_DDI_FUNC_ENABLE);
 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
@@ -316,7 +317,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 				DDI_BUF_CTL_ENABLE;
 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
 				~DDI_BUF_IS_IDLE;
-			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
+			vgpu_vreg_t(vgpu,
+				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
@@ -346,7 +348,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 				DDI_BUF_CTL_ENABLE;
 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
 				~DDI_BUF_IS_IDLE;
-			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
+			vgpu_vreg_t(vgpu,
+				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
@@ -410,10 +413,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 			TRANS_DDI_PORT_MASK);
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 			(PORT_B << TRANS_DDI_PORT_SHIFT) |
 			TRANS_DDI_FUNC_ENABLE);
@@ -436,10 +439,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 			TRANS_DDI_PORT_MASK);
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 			(PORT_C << TRANS_DDI_PORT_SHIFT) |
 			TRANS_DDI_FUNC_ENABLE);
@@ -462,10 +465,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 			TRANS_DDI_PORT_MASK);
-		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
 			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 			(PORT_D << TRANS_DDI_PORT_SHIFT) |
 			TRANS_DDI_FUNC_ENABLE);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index f2af234769bf..24abe70afe46 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -657,7 +657,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 	u32 dp_br, link_m, link_n, htotal, vtotal;
 
 	/* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
-	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &
+	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &
 		TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 	if (port != PORT_B && port != PORT_D) {
 		gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8488877dd68..14f4060dd573 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3953,7 +3953,7 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
-#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
+#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
 
 #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-- 
2.39.2

[PATCH 60/65] drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_DDI_FUNC_CTL2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c           | 6 ++++--
 drivers/gpu/drm/i915/display/intel_ddi.c         | 9 ++++++---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
 4 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index acc80d439352..ae8f6617aa70 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -784,7 +784,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 	if (intel_dsi->dual_link) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
+			intel_de_rmw(dev_priv,
+				     TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
 				     0, PORT_SYNC_MODE_ENABLE);
 		}
 
@@ -1344,7 +1345,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
 	if (intel_dsi->dual_link) {
 		for_each_dsi_port(port, intel_dsi->ports) {
 			dsi_trans = dsi_port_to_transcoder(port);
-			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
+			intel_de_rmw(dev_priv,
+				     TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
 				     PORT_SYNC_MODE_ENABLE, 0);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c5571be3c66e..515996c49f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -603,7 +603,8 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 		}
 
 		intel_de_write(dev_priv,
-			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
+			       TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
+			       ctl2);
 	}
 
 	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
@@ -640,7 +641,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
 
 	if (DISPLAY_VER(dev_priv) >= 11)
 		intel_de_write(dev_priv,
-			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
+			       TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
+			       0);
 
 	ctl = intel_de_read(dev_priv,
 			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
@@ -3757,7 +3759,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de
 	u32 master_select;
 
 	if (DISPLAY_VER(dev_priv) >= 11) {
-		u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
+		u32 ctl2 = intel_de_read(dev_priv,
+				         TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder));
 
 		if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
 			return INVALID_TRANSCODER;
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 036f77c2702d..bf55c9064b76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -913,7 +913,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
 	 * Incase of dual link, TE comes from DSI_1
 	 * this is to check if dual link is enabled
 	 */
-	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val = intel_uncore_read(&dev_priv->uncore,
+				TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0));
 	val &= PORT_SYNC_MODE_ENABLE;
 
 	/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 14f4060dd573..f330953e71cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4009,7 +4009,7 @@ enum skl_power_gate {
 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
-#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
+#define TRANS_DDI_FUNC_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
 #define  PORT_SYNC_MODE_ENABLE			REG_BIT(4)
 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
 #define  PORT_SYNC_MODE_MASTER_SELECT(x)	REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
-- 
2.39.2

[PATCH 61/65] drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TGL_DP_TP_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 515996c49f5a..135c2e7964fc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2184,7 +2184,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (DISPLAY_VER(dev_priv) >= 12)
-		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
+		return TGL_DP_TP_CTL(dev_priv,
+				     tgl_dp_tp_transcoder(crtc_state));
 	else
 		return DP_TP_CTL(encoder->port);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f330953e71cf..c1547ecdc352 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4022,7 +4022,7 @@ enum skl_power_gate {
 #define _DP_TP_CTL_B			0x64140
 #define _TGL_DP_TP_CTL_A		0x60540
 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
-#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
+#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
 #define  DP_TP_CTL_ENABLE			(1 << 31)
 #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
 #define  DP_TP_CTL_MODE_SST			(0 << 27)
-- 
2.39.2

[PATCH 62/65] drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TGL_DP_TP_STATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 135c2e7964fc..368cd1312d8a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2196,7 +2196,8 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (DISPLAY_VER(dev_priv) >= 12)
-		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
+		return TGL_DP_TP_STATUS(dev_priv,
+				        tgl_dp_tp_transcoder(crtc_state));
 	else
 		return DP_TP_STATUS(encoder->port);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1547ecdc352..3de6e4f54bc0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4048,7 +4048,7 @@ enum skl_power_gate {
 #define _DP_TP_STATUS_B			0x64144
 #define _TGL_DP_TP_STATUS_A		0x60544
 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
-#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
+#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
 #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
-- 
2.39.2

[PATCH 63/65] drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_MSA_MISC register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 368cd1312d8a..327f748d3774 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -440,7 +440,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 
-	intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
+	intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder),
+		       temp);
 }
 
 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3de6e4f54bc0..3fcebccb9f3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4229,7 +4229,7 @@ enum skl_power_gate {
 #define _TRANSB_MSA_MISC		0x61410
 #define _TRANSC_MSA_MISC		0x62410
 #define _TRANS_EDP_MSA_MISC		0x6f410
-#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
+#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
 /* See DP_MSA_MISC_* for the bit definitions */
 
 #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
-- 
2.39.2

[PATCH 64/65] drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_SET_CONTEXT_LATENCY register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 drivers/gpu/drm/i915/i915_reg.h              | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 62f8300c73a5..c608329dac42 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2703,7 +2703,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
 	 */
 	if (DISPLAY_VER(dev_priv) >= 13) {
-		intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
+		intel_de_write(dev_priv,
+			       TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder),
 			       crtc_vblank_start - crtc_vdisplay);
 
 		/*
@@ -2860,7 +2861,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 	if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
 		adjusted_mode->crtc_vblank_start =
 			adjusted_mode->crtc_vdisplay +
-			intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
+			intel_de_read(dev_priv,
+				      TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
 }
 
 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3fcebccb9f3c..8a1414ae72cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4236,7 +4236,7 @@ enum skl_power_gate {
 #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
 #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
 #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
-#define TRANS_SET_CONTEXT_LATENCY(tran)		_MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
+#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
 #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
 #define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)	REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
 
-- 
2.39.2

[PATCH 65/65] drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the MTL_CLKGATE_DIS_TRANS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
 drivers/gpu/drm/i915/i915_reg.h          | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4a4124a92a0d..21f6a4fa86a4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1716,7 +1716,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		if (!intel_dp->psr.panel_replay_enabled &&
 		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
-				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
+				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
+				     0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
 		else if (IS_ALDERLAKE_P(dev_priv))
 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
@@ -1897,7 +1898,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		if (!intel_dp->psr.panel_replay_enabled &&
 		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
 			intel_de_rmw(dev_priv,
-				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
+				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
 		else if (IS_ALDERLAKE_P(dev_priv))
 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8a1414ae72cb..7049a5ccefd9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4718,7 +4718,7 @@ enum skl_power_gate {
 
 #define _MTL_CLKGATE_DIS_TRANS_A			0x604E8
 #define _MTL_CLKGATE_DIS_TRANS_B			0x614E8
-#define MTL_CLKGATE_DIS_TRANS(trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
+#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
 #define  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS		REG_BIT(7)
 
 #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
-- 
2.39.2

✗ Fi.CI.CHECKPATCH: warning for drm/i915: finish the job of removing implicit dev_priv

[Patchwork]

== Series Details ==

Series: drm/i915: finish the job of removing implicit dev_priv
URL   : https://patchwork.freedesktop.org/series/134451/
State : warning

== Summary ==

Error: dim checkpatch failed
301fdadb6527 drm/i915: pass dev_priv explicitly to DPLL
f37456cf6a7c drm/i915: pass dev_priv explicitly to DPLL_MD
bd7912ce3034 drm/i915: pass dev_priv explicitly to TRANS_HTOTAL
f728f29b82a3 drm/i915: pass dev_priv explicitly to TRANS_HBLANK
e4dc6336bcbd drm/i915: pass dev_priv explicitly to TRANS_HSYNC
4e67dbb56ed6 drm/i915: pass dev_priv explicitly to TRANS_VTOTAL
9dfa4dd6653f drm/i915: pass dev_priv explicitly to TRANS_VBLANK
92615829c03b drm/i915: pass dev_priv explicitly to TRANS_VSYNC
50b932b61a7e drm/i915: pass dev_priv explicitly to BCLRPAT
3e70b784a2d4 drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT
2fa652d1271c drm/i915: pass dev_priv explicitly to PIPESRC
5e53aaac3af9 drm/i915: pass dev_priv explicitly to TRANS_MULT
b25ffcfc105a drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN
cbdee1b701e3 drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT
34fce7d287cf drm/i915: pass dev_priv explicitly to PFIT_CONTROL
a9fc052426c9 drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS
1af8cbd2f3ef drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS
0283b622ec17 drm/i915: pass dev_priv explicitly to TRANSCONF
-:151: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#151: FILE: drivers/gpu/drm/i915/display/intel_display.c:2804:
+				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;

-:155: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#155: FILE: drivers/gpu/drm/i915/display/intel_display.c:2807:
+				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;

-:342: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#342: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:416:
+		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;

total: 0 errors, 3 warnings, 0 checks, 378 lines checked
477fa5587d8b drm/i915: pass dev_priv explicitly to PIPEDSL
9dac0910a7e9 drm/i915: pass dev_priv explicitly to PIPEFRAME
8cd79ec7d473 drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL
-:29: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#29: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:389:
+		position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
bf398e7bbaca drm/i915: pass dev_priv explicitly to PIPESTAT
3d28129b88a7 drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL
1e74371f31ab drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS
-:48: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#48: FILE: drivers/gpu/drm/i915/i915_reg.h:1930:
+#define ICL_PIPESTATUS(dev_priv, pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)

total: 0 errors, 1 warnings, 0 checks, 30 lines checked
90edd5cc6639 drm/i915: pass dev_priv explicitly to DSPARB
-:123: CHECK:CAMELCASE: Avoid CamelCase: <saveDSPARB>
#123: FILE: drivers/gpu/drm/i915/i915_suspend.c:95:
+		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,

total: 0 errors, 0 warnings, 1 checks, 104 lines checked
e0277b8f5042 drm/i915: pass dev_priv explicitly to DSPFW1
-:73: ERROR:CODE_INDENT: code indent should use tabs where possible
#73: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2071:
+^I^I           FW_WM(srwm, SR) |$

-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2071:
+	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
+		           FW_WM(srwm, SR) |

-:74: ERROR:CODE_INDENT: code indent should use tabs where possible
#74: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2072:
+^I^I           FW_WM(8, CURSORB) |$

-:75: ERROR:CODE_INDENT: code indent should use tabs where possible
#75: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2073:
+^I^I           FW_WM(8, PLANEB) |$

-:76: ERROR:CODE_INDENT: code indent should use tabs where possible
#76: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2074:
+^I^I           FW_WM(8, PLANEA));$

total: 4 errors, 0 warnings, 1 checks, 83 lines checked
c6badbb03211 drm/i915: pass dev_priv explicitly to DSPFW2
-:40: ERROR:CODE_INDENT: code indent should use tabs where possible
#40: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2076:
+^I^I           FW_WM(8, CURSORA) |$

-:40: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#40: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2076:
+	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
+		           FW_WM(8, CURSORA) |

-:41: ERROR:CODE_INDENT: code indent should use tabs where possible
#41: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2077:
+^I^I           FW_WM(8, PLANEC_OLD));$

total: 2 errors, 0 warnings, 1 checks, 51 lines checked
d445b791484c drm/i915: pass dev_priv explicitly to DSPFW3
-:89: ERROR:CODE_INDENT: code indent should use tabs where possible
#89: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2082:
+^I^I           FW_WM(cursor_sr, CURSOR_SR));$

-:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#89: FILE: drivers/gpu/drm/i915/display/i9xx_wm.c:2082:
+	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
+		           FW_WM(cursor_sr, CURSOR_SR));

total: 1 errors, 0 warnings, 1 checks, 104 lines checked
a5be892a21be drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X
4ac941106983 drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X
d9589992ade4 drm/i915: pass dev_priv explicitly to CHV_BLEND
0133051e4b51 drm/i915: pass dev_priv explicitly to CHV_CANVAS
6ceef72a943a drm/i915: pass dev_priv explicitly to SWF0
-:33: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF0>
#33: FILE: drivers/gpu/drm/i915/i915_suspend.c:43:
+			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,

total: 0 errors, 0 warnings, 1 checks, 44 lines checked
597a06e475e8 drm/i915: pass dev_priv explicitly to SWF1
-:33: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF1>
#33: FILE: drivers/gpu/drm/i915/i915_suspend.c:45:
+			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,

total: 0 errors, 0 warnings, 1 checks, 56 lines checked
07ecea50cf43 drm/i915: pass dev_priv explicitly to SWF3
-:33: CHECK:CAMELCASE: Avoid CamelCase: <saveSWF3>
#33: FILE: drivers/gpu/drm/i915/i915_suspend.c:49:
+			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv,

total: 0 errors, 0 warnings, 1 checks, 44 lines checked
a3b180280198 drm/i915: pass dev_priv explicitly to _PIPEBDSL
29a03188b1f9 drm/i915: pass dev_priv explicitly to _TRANSBCONF
be5ffe5a05c7 drm/i915: pass dev_priv explicitly to _PIPEBSTAT
20a83089316c drm/i915: pass dev_priv explicitly to _PIPEB_FRMCOUNT_G4X
3c774852fe45 drm/i915: pass dev_priv explicitly to _PIPEB_FLIPCOUNT_G4X
2c2ba9a89d94 drm/i915: pass dev_priv explicitly to _DSPBCNTR
24cb8b68d492 drm/i915: pass dev_priv explicitly to _DSPBADDR
fdc2c0838276 drm/i915: pass dev_priv explicitly to _DSPBSTRIDE
46d61bb14dae drm/i915: pass dev_priv explicitly to _DSPBPOS
0567c36f35cb drm/i915: pass dev_priv explicitly to _DSPBSIZE
7e74f9199ee2 drm/i915: pass dev_priv explicitly to _DSPBSURF
4779fce49c4f drm/i915: pass dev_priv explicitly to _DSPBTILEOFF
5eaf764fe254 drm/i915: pass dev_priv explicitly to _DSPBOFFSET
7eef8e8bc0f2 drm/i915: pass dev_priv explicitly to _DSPBSURFLIVE
b3d2ae738152 drm/i915: pass dev_priv explicitly to PIPE_DATA_M1
2736ffa451cb drm/i915: pass dev_priv explicitly to PIPE_DATA_N1
ef9c2dc4adf2 drm/i915: pass dev_priv explicitly to PIPE_DATA_M2
bf8773957e68 drm/i915: pass dev_priv explicitly to PIPE_DATA_N2
13113c81c208 drm/i915: pass dev_priv explicitly to PIPE_LINK_M1
468988ff967b drm/i915: pass dev_priv explicitly to PIPE_LINK_N1
db78525d2f7b drm/i915: pass dev_priv explicitly to PIPE_LINK_M2
1bd5af50348a drm/i915: pass dev_priv explicitly to PIPE_LINK_N2
7c81e2008d0b drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL
7d5ccd404138 drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL
-:151: ERROR:CODE_INDENT: code indent should use tabs where possible
#151: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3768:
+^I^I^I^I        TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));$

-:246: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#246: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:38:
+					  TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;

total: 1 errors, 1 warnings, 0 checks, 302 lines checked
d3026ea2523c drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2
-:65: ERROR:CODE_INDENT: code indent should use tabs where possible
#65: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3763:
+^I^I^I^I         TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder));$

total: 1 errors, 0 warnings, 0 checks, 62 lines checked
5e360600eba3 drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL
5e5bdf3599e0 drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS
-:21: ERROR:CODE_INDENT: code indent should use tabs where possible
#21: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:2200:
+^I^I^I^I        tgl_dp_tp_transcoder(crtc_state));$

total: 1 errors, 0 warnings, 0 checks, 17 lines checked
901faa07bfcc drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC
76c16b9d1c11 drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY
-:45: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:4239:
+#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)

total: 0 errors, 1 warnings, 0 checks, 26 lines checked
faeacabf283f drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS
-:43: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:4721:
+#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)

total: 0 errors, 1 warnings, 0 checks, 25 lines checked

✓ Fi.CI.BAT: success for drm/i915: finish the job of removing implicit dev_priv

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2539 bytes --]

== Series Details ==

Series: drm/i915: finish the job of removing implicit dev_priv
URL   : https://patchwork.freedesktop.org/series/134451/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14874 -> Patchwork_134451v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/index.html

Participating hosts (40 -> 31)
------------------------------

  Missing    (9): bat-dg1-7 bat-adlp-9 fi-snb-2520m bat-adlp-6 fi-kbl-8809g bat-dg2-14 bat-dg2-13 bat-dg2-11 bat-mtlp-6 

Known issues
------------

  Here are the changes found in Patchwork_134451v1 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-atsm-1:         [FAIL][1] ([i915#10378]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/bat-atsm-1/igt@gem_lmem_swapping@basic@lmem0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/bat-atsm-1/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [ABORT][3] ([i915#10594]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hangcheck:
    - bat-rplp-1:         [ABORT][5] ([i915#10021]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/bat-rplp-1/igt@i915_selftest@live@hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/bat-rplp-1/igt@i915_selftest@live@hangcheck.html

  
  [i915#10021]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10021
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594


Build changes
-------------

  * Linux: CI_DRM_14874 -> Patchwork_134451v1

  CI-20190529: 20190529
  CI_DRM_14874: 77588a3e3e58917a9b1d992aeef6f02a6b85ded5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7877: 23b8b8a0168e1b5141e29346be1f83fdbed31037 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_134451v1: 77588a3e3e58917a9b1d992aeef6f02a6b85ded5 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/index.html

[-- Attachment #2: Type: text/html, Size: 3189 bytes --]

✗ Fi.CI.IGT: failure for drm/i915: finish the job of removing implicit dev_priv

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 64708 bytes --]

== Series Details ==

Series: drm/i915: finish the job of removing implicit dev_priv
URL   : https://patchwork.freedesktop.org/series/134451/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14874_full -> Patchwork_134451v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_134451v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_134451v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/index.html

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_134451v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a3:
    - shard-dg1:          NOTRUN -> [FAIL][1] +9 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a3.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-dg2:          NOTRUN -> [FAIL][2] +7 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-8/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-4-size-256:
    - shard-dg1:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg1-17/igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-4-size-256.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-17/igt@kms_plane_cursor@overlay@pipe-b-hdmi-a-4-size-256.html

  
Known issues
------------

  Here are the changes found in Patchwork_134451v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg1:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#6230])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@api_intel_bb@crc32.html

  * igt@debugfs_test@basic-hwmon:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#9318])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@debugfs_test@basic-hwmon.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][8] ([i915#5507])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@device_reset@unbind-reset-rebind.html
    - shard-mtlp:         NOTRUN -> [ABORT][9] ([i915#5507])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-6/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy-idle@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][10] ([i915#8414]) +9 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@drm_fdinfo@busy-idle@vcs1.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#9323]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-rkl:          NOTRUN -> [SKIP][13] ([i915#6335])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#8562])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][15] -> [FAIL][16] ([i915#6268])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#8555])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg1:          NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#4525]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@many-4k-zero:
    - shard-rkl:          NOTRUN -> [FAIL][21] ([i915#9606])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_exec_capture@many-4k-zero.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][22] ([i915#2842])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][23] ([i915#2842])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk9/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [PASS][24] -> [FAIL][25] ([i915#2842])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglu:         NOTRUN -> [FAIL][26] ([i915#2842]) +4 other tests fail
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [PASS][27] -> [FAIL][28] ([i915#2842])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-2/igt@gem_exec_fair@basic-pace@vecs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#3539]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-dg1:          NOTRUN -> [SKIP][31] ([i915#3281]) +8 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#3281]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-dg1:          NOTRUN -> [SKIP][33] ([i915#4812])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg1:          NOTRUN -> [SKIP][34] ([i915#4860]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          NOTRUN -> [SKIP][35] ([i915#4613] / [i915#7582])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-tglu:         NOTRUN -> [SKIP][36] ([i915#4613])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-random@lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][37] ([i915#10378])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_lmem_swapping@heavy-random@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][38] ([i915#4565]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
    - shard-dg2:          [PASS][39] -> [FAIL][40] ([i915#10378])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          NOTRUN -> [SKIP][41] ([i915#4613]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_lmem_swapping@verify.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-glk:          NOTRUN -> [SKIP][42] ([i915#4613]) +3 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk9/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_mmap_wc@copy:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#4083]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@gem_mmap_wc@copy.html

  * igt@gem_pread@snoop:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#3282]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_pread@snoop.html

  * igt@gem_pwrite@basic-self:
    - shard-dg1:          NOTRUN -> [SKIP][45] ([i915#3282]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@gem_pwrite@basic-self.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#4270]) +4 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#8411]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4885])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_unfence_active_buffers:
    - shard-dg1:          NOTRUN -> [SKIP][49] ([i915#4879])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-glk:          NOTRUN -> [SKIP][50] ([i915#3323])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#3282] / [i915#3297])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#3297]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg1:          NOTRUN -> [SKIP][53] ([i915#3297] / [i915#4880])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][54] ([i915#3297])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-dg1:          NOTRUN -> [SKIP][55] ([i915#3297]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-rkl:          NOTRUN -> [SKIP][56] ([i915#2527]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_module_load@load:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#6227])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-tglu:         [PASS][58] -> [INCOMPLETE][59] ([i915#10047] / [i915#10887] / [i915#9820])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-tglu-4/igt@i915_module_load@reload-with-fault-injection.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rps@thresholds@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#8925])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@i915_pm_rps@thresholds@gt0.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#5723])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@i915_query@test-query-geometry-subslices.html
    - shard-tglu:         NOTRUN -> [SKIP][62] ([i915#5723])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@debugfs-reader:
    - shard-dg1:          NOTRUN -> [FAIL][63] ([i915#10031]) +1 other test fail
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@i915_suspend@debugfs-reader.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#4215])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg1:          NOTRUN -> [SKIP][65] ([i915#4212])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#8709]) +7 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#8709]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#8709]) +11 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#9531])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#1769] / [i915#3555])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#4538] / [i915#5286]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
    - shard-tglu:         NOTRUN -> [SKIP][72] ([i915#5286]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][73] -> [DMESG-FAIL][74] ([i915#2017])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#5286]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#3638]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][77] ([i915#3638]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         [PASS][78] -> [FAIL][79] ([i915#3743])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#4538]) +5 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_joiner@basic:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#10656]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][82] ([i915#6095]) +71 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#6095]) +15 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#10307] / [i915#6095]) +206 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#6095]) +75 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#10278])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#10278])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][89] ([i915#10278])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][90] +192 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk9/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#7213]) +3 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-a-dp-4.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#3742])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#7828]) +5 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
    - shard-dg1:          NOTRUN -> [SKIP][94] ([i915#7828]) +6 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#7828]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_color@deep-color:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#3555] / [i915#9979])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#7118] / [i915#9424])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-dg1:          NOTRUN -> [SKIP][98] ([i915#7116] / [i915#9424])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm:
    - shard-dg1:          NOTRUN -> [SKIP][99] ([i915#7116])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@srm@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][100] ([i915#7173])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][101] ([i915#3555]) +5 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_cursor_crc@cursor-onscreen-32x32.html
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#3555]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#3359])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-dg1:          NOTRUN -> [SKIP][104] ([i915#3359]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#4103]) +1 other test skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([i915#9227])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#9723])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#3555] / [i915#3840])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_dsc@dsc-basic.html
    - shard-tglu:         NOTRUN -> [SKIP][109] ([i915#3555] / [i915#3840])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#3555] / [i915#3840])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg1:          NOTRUN -> [SKIP][111] ([i915#3469])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_fbcon_fbt@psr.html
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#3469])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#1839])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          NOTRUN -> [SKIP][114] +29 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][115] ([i915#9934]) +2 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
    - shard-rkl:          [PASS][116] -> [FAIL][117] ([i915#2122]) +1 other test fail
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2:
    - shard-dg2:          NOTRUN -> [FAIL][118] ([i915#10545]) +3 other tests fail
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-2/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#2587] / [i915#2672]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#2672]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][121] ([i915#2587] / [i915#2672]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2:          [PASS][122] -> [FAIL][123] ([i915#6880]) +1 other test fail
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-snb:          [PASS][124] -> [SKIP][125] +2 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#3023]) +18 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][127] ([i915#3458]) +16 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#1825]) +27 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][129] ([i915#8708]) +7 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#5439])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#8708])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][132] +16 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][133] +18 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-dg1:          NOTRUN -> [SKIP][134] ([i915#433])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][135] ([i915#3555] / [i915#8228]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#3555] / [i915#8228])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#3555] / [i915#8228])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_hdr@static-toggle.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][138] ([i915#4816])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][139] ([i915#7862]) +1 other test fail
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][140] ([i915#10647]) +1 other test fail
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-glk9/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][141] ([i915#8292])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#9423]) +7 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#9423]) +11 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][144] ([i915#9423]) +9 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][145] ([i915#5176] / [i915#9423]) +3 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#5176] / [i915#9423]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#5235]) +5 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][149] ([i915#5235] / [i915#9423]) +15 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#3361])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@fences:
    - shard-dg1:          NOTRUN -> [SKIP][151] ([i915#4077]) +12 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_pm_rpm@fences.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [PASS][152] -> [SKIP][153] ([i915#9519]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#6524])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
    - shard-dg1:          NOTRUN -> [SKIP][155] +29 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#9683]) +1 other test skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@pr-sprite-plane-move:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#9732]) +5 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@kms_psr@pr-sprite-plane-move.html

  * igt@kms_psr@pr-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#1072] / [i915#9732]) +12 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_psr@pr-sprite-render.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][159] ([i915#1072] / [i915#9732]) +16 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#5289])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([i915#5289])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-13/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-dg1:          [PASS][162] -> [DMESG-WARN][163] ([i915#1982])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg1-14/igt@kms_rotation_crc@sprite-rotation-90.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-16/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#3555]) +4 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#3555] / [i915#9906])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-10/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#9906])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-check-output:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#2437])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@kms_writeback@writeback-check-output.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          NOTRUN -> [SKIP][168] ([i915#8516])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#3708])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@prime_vgem@fence-flip-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#9917]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-dg1:          NOTRUN -> [FAIL][171] ([i915#9781])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@syncobj_timeline@invalid-wait-zero-handles.html
    - shard-tglu:         NOTRUN -> [FAIL][172] ([i915#9781])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-rkl:          NOTRUN -> [FAIL][173] ([i915#9779])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@syncobj_wait@invalid-wait-zero-handles.html

  * igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
    - shard-dg1:          NOTRUN -> [SKIP][174] ([i915#2575]) +7 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html

  * igt@v3d/v3d_submit_cl@bad-multisync-pad:
    - shard-tglu:         NOTRUN -> [SKIP][175] ([i915#2575]) +4 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-9/igt@v3d/v3d_submit_cl@bad-multisync-pad.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#7711]) +4 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-4/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done:
    - shard-dg1:          NOTRUN -> [SKIP][177] ([i915#7711]) +6 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-15/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-rkl:          [FAIL][178] ([i915#2842]) -> [PASS][179]
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-3/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          [FAIL][180] ([i915#10446]) -> [PASS][181]
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-4/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
    - shard-dg1:          [FAIL][182] ([i915#10378]) -> [PASS][183] +1 other test pass
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-17/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [ABORT][184] ([i915#9697] / [i915#9820]) -> [PASS][185]
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
    - shard-mtlp:         [ABORT][186] ([i915#10131] / [i915#10887] / [i915#9820]) -> [PASS][187]
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][188] ([i915#7790]) -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-snb2/igt@i915_pm_rps@reset.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb6/igt@i915_pm_rps@reset.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [SKIP][190] ([i915#7984]) -> [PASS][191]
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-mtlp-6/igt@i915_power@sanity.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-2/igt@i915_power@sanity.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [FAIL][192] ([i915#10031]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@torture-move@pipe-a:
    - shard-dg2:          [DMESG-WARN][194] ([i915#10166]) -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-1/igt@kms_cursor_legacy@torture-move@pipe-a.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-3/igt@kms_cursor_legacy@torture-move@pipe-a.html

  * igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1:
    - shard-snb:          [FAIL][196] ([i915#2122]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb7/igt@kms_flip@2x-wf_vblank-ts-check@ab-vga1-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
    - shard-snb:          [INCOMPLETE][198] ([i915#4839]) -> [PASS][199]
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-mtlp:         [FAIL][200] -> [PASS][201]
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-mtlp-3/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-mtlp-5/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][202] ([i915#9295]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][204] ([i915#4281]) -> [PASS][205]
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-tglu-3/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][206] ([i915#9519]) -> [PASS][207] +1 other test pass
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2:          [SKIP][208] ([i915#9519]) -> [PASS][209] +2 other tests pass
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-10/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_sysfs_edid_timing:
    - shard-snb:          [FAIL][210] ([IGT#2] / [i915#6493]) -> [PASS][211]
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-snb7/igt@kms_sysfs_edid_timing.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-snb7/igt@kms_sysfs_edid_timing.html

  
#### Warnings ####

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-dg2:          [INCOMPLETE][212] ([i915#9364]) -> [ABORT][213] ([i915#9846])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-8/igt@gem_create@create-ext-cpu-access-big.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [INCOMPLETE][214] ([i915#1982] / [i915#9820] / [i915#9849]) -> [ABORT][215] ([i915#9820])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-4/igt@i915_module_load@reload-with-fault-injection.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][216] ([i915#9433]) -> [SKIP][217] ([i915#9424])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg1-13/igt@kms_content_protection@mei-interface.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg1-14/igt@kms_content_protection@mei-interface.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][218] ([i915#3458]) -> [SKIP][219] ([i915#10433] / [i915#3458]) +4 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-dg2:          [SKIP][220] ([i915#10433] / [i915#3458]) -> [SKIP][221] ([i915#3458])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-rkl:          [SKIP][222] ([i915#3361]) -> [SKIP][223] ([i915#3828])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-rkl-6/igt@kms_pm_dc@deep-pkgc.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-rkl-5/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr@fbc-pr-primary-mmap-gtt:
    - shard-dg2:          [SKIP][224] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][225] ([i915#1072] / [i915#9732]) +9 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-5/igt@kms_psr@fbc-pr-primary-mmap-gtt.html

  * igt@kms_psr@fbc-psr2-sprite-blt:
    - shard-dg2:          [SKIP][226] ([i915#1072] / [i915#9732]) -> [SKIP][227] ([i915#1072] / [i915#9673] / [i915#9732]) +13 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14874/shard-dg2-6/igt@kms_psr@fbc-psr2-sprite-blt.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-blt.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
  [i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
  [i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
  [i915#10545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10545
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2017
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3743]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3743
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6493
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
  [i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
  [i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9697
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
  [i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_14874 -> Patchwork_134451v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_14874: 77588a3e3e58917a9b1d992aeef6f02a6b85ded5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7877: 23b8b8a0168e1b5141e29346be1f83fdbed31037 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_134451v1: 77588a3e3e58917a9b1d992aeef6f02a6b85ded5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134451v1/index.html

[-- Attachment #2: Type: text/html, Size: 77417 bytes --]

Re: [PATCH 01/65] drm/i915: pass dev_priv explicitly to DPLL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:19PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DPLL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

(
even though it is a big series and overall it looks all right,
I will put one by one for 2 reasons:
- so I ensure I don't miss details and I know where I stopped
- so you can use dim b4 directly without extra rebase and adding my rv-b one by one...
)

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 21 ++++-----
>  .../drm/i915/display/intel_display_power.c    |  2 +-
>  .../i915/display/intel_display_power_well.c   |  6 +--
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 45 ++++++++++---------
>  drivers/gpu/drm/i915/display/intel_dvo.c      |  5 ++-
>  drivers/gpu/drm/i915/display/intel_pps.c      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +-
>  7 files changed, 43 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7370acdd6b8b..42e2d884c98e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -382,11 +382,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  		fallthrough;
>  	case PORT_B:
>  		port_mask = DPLL_PORTB_READY_MASK;
> -		dpll_reg = DPLL(0);
> +		dpll_reg = DPLL(dev_priv, 0);
>  		break;
>  	case PORT_C:
>  		port_mask = DPLL_PORTC_READY_MASK;
> -		dpll_reg = DPLL(0);
> +		dpll_reg = DPLL(dev_priv, 0);
>  		expected_mask <<= 4;
>  		break;
>  	case PORT_D:
> @@ -8212,11 +8212,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
>  	 * dividers, even though the register value does change.
>  	 */
> -	intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
> -	intel_de_write(dev_priv, DPLL(pipe), dpll);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
> +		       dpll & ~DPLL_VGA_MODE_DIS);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
>  
>  	/* Wait for the clocks to stabilize. */
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  	udelay(150);
>  
>  	/* The pixel multiplier can only be updated once the
> @@ -8224,12 +8225,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	 *
>  	 * So write it again.
>  	 */
> -	intel_de_write(dev_priv, DPLL(pipe), dpll);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
>  
>  	/* We do this three times for luck */
>  	for (i = 0; i < 3 ; i++) {
> -		intel_de_write(dev_priv, DPLL(pipe), dpll);
> -		intel_de_posting_read(dev_priv, DPLL(pipe));
> +		intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll);
> +		intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  		udelay(150); /* wait for warmup */
>  	}
>  
> @@ -8262,8 +8263,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  	intel_wait_for_pipe_scanline_stopped(crtc);
>  
> -	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  }
>  
>  void intel_hpd_poll_fini(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 34b6d843bc9e..3c5cb587f9bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1772,7 +1772,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
>  	 * current lane status.
>  	 */
>  	if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
> -		u32 status = intel_de_read(dev_priv, DPLL(PIPE_A));
> +		u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A));
>  		unsigned int mask;
>  
>  		mask = status & DPLL_PORTB_READY_MASK;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 83f616097a29..3b6cb237d80a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1196,13 +1196,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
>  	 * CHV DPLL B/C have some issues if VGA mode is enabled.
>  	 */
>  	for_each_pipe(dev_priv, pipe) {
> -		u32 val = intel_de_read(dev_priv, DPLL(pipe));
> +		u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe));
>  
>  		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
>  		if (pipe != PIPE_A)
>  			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  
> -		intel_de_write(dev_priv, DPLL(pipe), val);
> +		intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
>  	}
>  
>  	vlv_init_display_clock_gating(dev_priv);
> @@ -1355,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
>  		 */
>  		if (BITS_SET(phy_control,
>  			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
> -		    (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
> +		    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
>  			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
>  
>  		if (BITS_SET(phy_control,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a981f45facb3..a007ca5208b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -403,7 +403,7 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
>  		hw_state->dpll_md = tmp;
>  	}
>  
> -	hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
> +	hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe));
>  
>  	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
>  		hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe));
> @@ -1842,11 +1842,12 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
>  	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
>  	 * dividers, even though the register value does change.
>  	 */
> -	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
> -	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
> +		       hw_state->dpll & ~DPLL_VGA_MODE_DIS);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
>  
>  	/* Wait for the clocks to stabilize. */
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  	udelay(150);
>  
>  	if (DISPLAY_VER(dev_priv) >= 4) {
> @@ -1857,13 +1858,13 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
>  		 *
>  		 * So write it again.
>  		 */
> -		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
> +		intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
>  	}
>  
>  	/* We do this three times for luck */
>  	for (i = 0; i < 3; i++) {
> -		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
> -		intel_de_posting_read(dev_priv, DPLL(pipe));
> +		intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
> +		intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  		udelay(150); /* wait for warmup */
>  	}
>  }
> @@ -1991,11 +1992,11 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
>  	enum pipe pipe = crtc->pipe;
>  
> -	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  	udelay(150);
>  
> -	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
> +	if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
>  		drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
>  }
>  
> @@ -2012,7 +2013,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	assert_pps_unlocked(dev_priv, pipe);
>  
>  	/* Enable Refclk */
> -	intel_de_write(dev_priv, DPLL(pipe),
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
>  		       hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
>  
>  	if (hw_state->dpll & DPLL_VCO_ENABLE) {
> @@ -2138,10 +2139,10 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	udelay(1);
>  
>  	/* Enable PLL */
> -	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll);
>  
>  	/* Check PLL is locked */
> -	if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
> +	if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1))
>  		drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
>  }
>  
> @@ -2158,7 +2159,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	assert_pps_unlocked(dev_priv, pipe);
>  
>  	/* Enable Refclk and SSC */
> -	intel_de_write(dev_priv, DPLL(pipe),
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe),
>  		       hw_state->dpll & ~DPLL_VCO_ENABLE);
>  
>  	if (hw_state->dpll & DPLL_VCO_ENABLE) {
> @@ -2183,7 +2184,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  		 * We should always have it disabled.
>  		 */
>  		drm_WARN_ON(&dev_priv->drm,
> -			    (intel_de_read(dev_priv, DPLL(PIPE_B)) &
> +			    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
>  			     DPLL_VGA_MODE_DIS) == 0);
>  	} else {
>  		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
> @@ -2241,8 +2242,8 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  
> -	intel_de_write(dev_priv, DPLL(pipe), val);
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  }
>  
>  void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> @@ -2259,8 +2260,8 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  
> -	intel_de_write(dev_priv, DPLL(pipe), val);
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), val);
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  
>  	vlv_dpio_get(dev_priv);
>  
> @@ -2285,8 +2286,8 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
>  	/* Make sure the pipe isn't still relying on us */
>  	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
>  
> -	intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
> -	intel_de_posting_read(dev_priv, DPLL(pipe));
> +	intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS);
> +	intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe));
>  }
>  
>  
> @@ -2312,7 +2313,7 @@ static void assert_pll(struct drm_i915_private *dev_priv,
>  {
>  	bool cur_state;
>  
> -	cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
> +	cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
>  	I915_STATE_WARN(dev_priv, cur_state != state,
>  			"PLL state assertion failure (expected %s, current %s)\n",
>  			str_on_off(state), str_on_off(cur_state));
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 1840f5b59229..091824334f26 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -456,13 +456,14 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
>  	 * the device.
>  	 */
>  	for_each_pipe(dev_priv, pipe)
> -		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE);
> +		dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0,
> +					  DPLL_DVO_2X_MODE);
>  
>  	ret = dvo->dev_ops->init(&intel_dvo->dev, i2c);
>  
>  	/* restore the DVO 2x clock state to original */
>  	for_each_pipe(dev_priv, pipe) {
> -		intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
> +		intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]);
>  	}
>  
>  	intel_gmbus_force_bit(i2c, false);
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index 73046ef58d8e..42306bc4ba86 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -119,7 +119,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
>  	else
>  		DP |= DP_PIPE_SEL(pipe);
>  
> -	pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
> +	pll_enabled = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
>  
>  	/*
>  	 * The DPLL for the pipe must be enabled for this to work.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6877e2f0fbc3..8ff04bb19cbe 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -668,7 +668,7 @@
>  #define _DPLL_A			0x6014
>  #define _DPLL_B			0x6018
>  #define _CHV_DPLL_C		0x6030
> -#define DPLL(pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> +#define DPLL(dev_priv, pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
>  						 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
>  
>  #define VGA0	_MMIO(0x6000)
> -- 
> 2.39.2
> 

Re: [PATCH 02/65] drm/i915: pass dev_priv explicitly to DPLL_MD

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:20PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DPLL_MD register macro.
> 

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++++-------
>  drivers/gpu/drm/i915/i915_reg.h           |  2 +-
>  2 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a007ca5208b8..d67d5e2fd570 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -398,7 +398,8 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
>  		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
>  			tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
>  		else
> -			tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
> +			tmp = intel_de_read(dev_priv,
> +					    DPLL_MD(dev_priv, crtc->pipe));
>  
>  		hw_state->dpll_md = tmp;
>  	}
> @@ -1851,7 +1852,8 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
>  	udelay(150);
>  
>  	if (DISPLAY_VER(dev_priv) >= 4) {
> -		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
> +		intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
> +			       hw_state->dpll_md);
>  	} else {
>  		/* The pixel multiplier can only be updated once the
>  		 * DPLL is enabled and the clocks are stable.
> @@ -2021,8 +2023,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
>  		_vlv_enable_pll(crtc_state);
>  	}
>  
> -	intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
> -	intel_de_posting_read(dev_priv, DPLL_MD(pipe));
> +	intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md);
> +	intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
>  }
>  
>  static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
> @@ -2175,7 +2177,8 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  		 * the value from DPLLBMD to either pipe B or C.
>  		 */
>  		intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
> -		intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md);
> +		intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B),
> +			       hw_state->dpll_md);
>  		intel_de_write(dev_priv, CBR4_VLV, 0);
>  		dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md;
>  
> @@ -2187,8 +2190,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  			    (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) &
>  			     DPLL_VGA_MODE_DIS) == 0);
>  	} else {
> -		intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md);
> -		intel_de_posting_read(dev_priv, DPLL_MD(pipe));
> +		intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe),
> +			       hw_state->dpll_md);
> +		intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe));
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8ff04bb19cbe..ea8181abf7fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -768,7 +768,7 @@
>  #define _DPLL_A_MD		0x601c
>  #define _DPLL_B_MD		0x6020
>  #define _CHV_DPLL_C_MD		0x603c
> -#define DPLL_MD(pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
> +#define DPLL_MD(dev_priv, pipe)		_MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
>  						 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
>  
>  /*
> -- 
> 2.39.2
> 

Re: [PATCH 03/65] drm/i915: pass dev_priv explicitly to TRANS_HTOTAL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:21PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_HTOTAL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
>  drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
>  drivers/gpu/drm/i915/gvt/handlers.c              | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
>  6 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 79ecfc339430..af0d3159369e 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -915,7 +915,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	/* program TRANS_HTOTAL register */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);
> -		intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
> +		intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
>  			       HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 42e2d884c98e..481e076b17e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2710,7 +2710,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
>  			       vsyncshift);
>  
> -	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
>  		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
>  		       HTOTAL(adjusted_mode->crtc_htotal - 1));
>  	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
> @@ -2811,7 +2811,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
>  	u32 tmp;
>  
> -	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
> +	tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder));
>  	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
>  	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>  
> @@ -8189,7 +8189,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		PLL_REF_INPUT_DREFCLK |
>  		DPLL_VCO_ENABLE;
>  
> -	intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
>  		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
>  	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
>  		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 826e38a9e6a4..2bf00d5336e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -224,7 +224,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 708b99be02ac..06ba39b2b103 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -677,7 +677,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
>  	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
>  
>  	/* Get H/V total from transcoder timing */
> -	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
> +	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
>  	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
>  
>  	if (dp_br && link_n && htotal && vtotal) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ea8181abf7fd..8398826e9c2d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1217,7 +1217,7 @@
>  #define _TRANS_VSYNC_DSI1	0x6b814
>  #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
>  
> -#define TRANS_HTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
> +#define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
>  #define TRANS_HBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
>  #define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
>  #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index f5c4e4e2f11f..2bc90909d980 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -231,7 +231,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(SPRSCALE(PIPE_C));
>  	MMIO_D(SPRSURFLIVE(PIPE_C));
>  	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
> -	MMIO_D(TRANS_HTOTAL(TRANSCODER_A));
> +	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HBLANK(TRANSCODER_A));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
> @@ -240,7 +240,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(BCLRPAT(TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
>  	MMIO_D(PIPESRC(TRANSCODER_A));
> -	MMIO_D(TRANS_HTOTAL(TRANSCODER_B));
> +	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HBLANK(TRANSCODER_B));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
> @@ -249,7 +249,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(BCLRPAT(TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
>  	MMIO_D(PIPESRC(TRANSCODER_B));
> -	MMIO_D(TRANS_HTOTAL(TRANSCODER_C));
> +	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HBLANK(TRANSCODER_C));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
> @@ -258,7 +258,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(BCLRPAT(TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
>  	MMIO_D(PIPESRC(TRANSCODER_C));
> -	MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP));
> +	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 04/65] drm/i915: pass dev_priv explicitly to TRANS_HBLANK

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:22PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_HBLANK register macro.
> 

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c     | 7 ++++---
>  drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
>  4 files changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 481e076b17e6..997418fb7310 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2713,7 +2713,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
>  		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
>  		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> -	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
>  		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
>  		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
>  	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
> @@ -2816,7 +2816,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>  
>  	if (!transcoder_is_dsi(cpu_transcoder)) {
> -		tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_HBLANK(dev_priv, cpu_transcoder));
>  		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
>  		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
>  	}
> @@ -8191,7 +8192,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
>  		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
> -	intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
>  		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
>  	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
>  		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 2bf00d5336e3..625b1fedd54c 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8398826e9c2d..66e652119a7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1218,7 +1218,7 @@
>  #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
>  
>  #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
> -#define TRANS_HBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
> +#define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
>  #define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
>  #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
>  #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 2bc90909d980..47681fa69020 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -232,7 +232,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(SPRSURFLIVE(PIPE_C));
>  	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_HBLANK(TRANSCODER_A));
> +	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
> @@ -241,7 +241,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
>  	MMIO_D(PIPESRC(TRANSCODER_A));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_HBLANK(TRANSCODER_B));
> +	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
> @@ -250,7 +250,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
>  	MMIO_D(PIPESRC(TRANSCODER_B));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_HBLANK(TRANSCODER_C));
> +	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
> @@ -259,7 +259,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
>  	MMIO_D(PIPESRC(TRANSCODER_C));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
> +	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 05/65] drm/i915: pass dev_priv explicitly to TRANS_HSYNC

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:23PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_HSYNC register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
>  drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
>  5 files changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index af0d3159369e..f87a2170ac91 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -938,7 +938,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
> +			intel_de_write(dev_priv,
> +				       TRANS_HSYNC(dev_priv, dsi_trans),
>  				       HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 997418fb7310..111f2c400ecd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2716,7 +2716,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
>  		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
>  		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> -	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
>  		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>  		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>  
> @@ -2822,7 +2822,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
>  	}
>  
> -	tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
> +	tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder));
>  	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
>  	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
>  
> @@ -8194,7 +8194,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
>  	intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder),
>  		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
> -	intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
>  		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
>  	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
>  		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 625b1fedd54c..480c0e09434d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -228,7 +228,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
>  
>  	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 66e652119a7e..0d33815b91a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1219,7 +1219,7 @@
>  
>  #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
>  #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
> -#define TRANS_HSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
> +#define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
>  #define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
>  #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
>  #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 47681fa69020..09d8960f7398 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -233,7 +233,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_HSYNC(TRANSCODER_A));
> +	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
> @@ -242,7 +242,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPESRC(TRANSCODER_A));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_HSYNC(TRANSCODER_B));
> +	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
> @@ -251,7 +251,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPESRC(TRANSCODER_B));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_HSYNC(TRANSCODER_C));
> +	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
> @@ -260,7 +260,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPESRC(TRANSCODER_C));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
> +	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 06/65] drm/i915: pass dev_priv explicitly to TRANS_VTOTAL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:24PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VTOTAL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           |  2 +-
>  drivers/gpu/drm/i915/display/intel_crt.c         |  3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c     | 10 +++++-----
>  drivers/gpu/drm/i915/display/intel_pch_display.c |  2 +-
>  drivers/gpu/drm/i915/gvt/handlers.c              |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  |  2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      |  8 ++++----
>  7 files changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f87a2170ac91..f95709321ea6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -953,7 +953,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  		 * struct drm_display_mode.
>  		 * For interlace mode: program required pixel minus 2
>  		 */
> -		intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
> +		intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
>  			       VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 10e95dc425a6..29ab5b112b86 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -708,7 +708,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
>  
>  	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
> -	save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> +	save_vtotal = intel_de_read(dev_priv,
> +				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
>  	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
>  
>  	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 111f2c400ecd..c681a23be1eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2720,7 +2720,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>  		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>  
> -	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
>  	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> @@ -2736,7 +2736,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	 * bits. */
>  	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
>  	    (pipe == PIPE_B || pipe == PIPE_C))
> -		intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
> +		intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
>  			       VACTIVE(crtc_vdisplay - 1) |
>  			       VTOTAL(crtc_vtotal - 1));
>  }
> @@ -2767,7 +2767,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	 * The double buffer latch point for TRANS_VTOTAL
>  	 * is the transcoder's undelayed vblank.
>  	 */
> -	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
>  }
> @@ -2826,7 +2826,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
>  	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
>  
> -	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> +	tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
>  	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
>  	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>  
> @@ -8196,7 +8196,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
>  	intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
>  		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
> -	intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>  		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
>  	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
>  		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 480c0e09434d..611a9cd2596f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -231,7 +231,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  		       intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
>  
>  	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 06ba39b2b103..00cf35a9669e 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -678,7 +678,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
>  
>  	/* Get H/V total from transcoder timing */
>  	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
> -	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
> +	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
>  
>  	if (dp_br && link_n && htotal && vtotal) {
>  		u64 pixel_clk = 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0d33815b91a4..3b48022b29a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1220,7 +1220,7 @@
>  #define TRANS_HTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
>  #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
>  #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
> -#define TRANS_VTOTAL(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
> +#define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
>  #define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
>  #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
>  #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 09d8960f7398..5dd85943e0a1 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -234,7 +234,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
> +	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
>  	MMIO_D(BCLRPAT(TRANSCODER_A));
> @@ -243,7 +243,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
> +	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
>  	MMIO_D(BCLRPAT(TRANSCODER_B));
> @@ -252,7 +252,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
> +	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
>  	MMIO_D(BCLRPAT(TRANSCODER_C));
> @@ -261,7 +261,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
> +	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
>  	MMIO_D(BCLRPAT(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 07/65] drm/i915: pass dev_priv explicitly to TRANS_VBLANK

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:25PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VBLANK register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           |  3 ++-
>  drivers/gpu/drm/i915/display/intel_crt.c         | 10 +++++++---
>  drivers/gpu/drm/i915/display/intel_display.c     |  9 +++++----
>  drivers/gpu/drm/i915/display/intel_pch_display.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  |  2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      |  8 ++++----
>  6 files changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f95709321ea6..0ee42954054f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -995,7 +995,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	if (DISPLAY_VER(dev_priv) >= 12) {
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
> +			intel_de_write(dev_priv,
> +				       TRANS_VBLANK(dev_priv, dsi_trans),
>  				       VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 29ab5b112b86..54549d2cfcff 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -710,7 +710,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
>  	save_vtotal = intel_de_read(dev_priv,
>  				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
> -	vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> +	vblank = intel_de_read(dev_priv,
> +			       TRANS_VBLANK(dev_priv, cpu_transcoder));
>  
>  	vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
>  	vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
> @@ -749,7 +750,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  			u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
>  
>  			vblank_start = vsync_start;
> -			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> +			intel_de_write(dev_priv,
> +				       TRANS_VBLANK(dev_priv, cpu_transcoder),
>  				       VBLANK_START(vblank_start - 1) |
>  				       VBLANK_END(vblank_end - 1));
>  			restore_vblank = true;
> @@ -782,7 +784,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  
>  		/* restore vblank if necessary */
>  		if (restore_vblank)
> -			intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
> +			intel_de_write(dev_priv,
> +				       TRANS_VBLANK(dev_priv, cpu_transcoder),
> +				       vblank);
>  		/*
>  		 * If more than 3/4 of the scanline detected a monitor,
>  		 * then it is assumed to be present. This works even on i830,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c681a23be1eb..87a690cf5808 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2723,7 +2723,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
> -	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
>  	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> @@ -2760,7 +2760,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
>  	 * But let's write it anyway to keep the state checker happy.
>  	 */
> -	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
>  	/*
> @@ -2832,7 +2832,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  
>  	/* FIXME TGL+ DSI transcoders have this! */
>  	if (!transcoder_is_dsi(cpu_transcoder)) {
> -		tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_VBLANK(dev_priv, cpu_transcoder));
>  		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
>  		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
>  	}
> @@ -8198,7 +8199,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
>  	intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
>  		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
> -	intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
>  		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
>  	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
>  		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 611a9cd2596f..03a33ff2653a 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -233,7 +233,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b48022b29a7..155259c11c88 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1221,7 +1221,7 @@
>  #define TRANS_HBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
>  #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
>  #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
> -#define TRANS_VBLANK(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
> +#define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
>  #define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
>  #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
>  #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 5dd85943e0a1..baeedcdfdcab 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -235,7 +235,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_VBLANK(TRANSCODER_A));
> +	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
>  	MMIO_D(BCLRPAT(TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
> @@ -244,7 +244,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_VBLANK(TRANSCODER_B));
> +	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
>  	MMIO_D(BCLRPAT(TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
> @@ -253,7 +253,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_VBLANK(TRANSCODER_C));
> +	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
>  	MMIO_D(BCLRPAT(TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
> @@ -262,7 +262,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
> +	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
>  	MMIO_D(BCLRPAT(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 09/65] drm/i915: pass dev_priv explicitly to BCLRPAT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:27PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the BCLRPAT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c     | 10 ++++++----
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h              |  2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  |  8 ++++----
>  4 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 15569cf96c9c..2660c4a53e6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -193,7 +193,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  		adpa |= ADPA_PIPE_SEL(crtc->pipe);
>  
>  	if (!HAS_PCH_SPLIT(dev_priv))
> -		intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
> +		intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
>  
>  	switch (mode) {
>  	case DRM_MODE_DPMS_ON:
> @@ -707,7 +707,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  
>  	drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
>  
> -	save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
> +	save_bclrpat = intel_de_read(dev_priv,
> +				     BCLRPAT(dev_priv, cpu_transcoder));
>  	save_vtotal = intel_de_read(dev_priv,
>  				    TRANS_VTOTAL(dev_priv, cpu_transcoder));
>  	vblank = intel_de_read(dev_priv,
> @@ -720,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  	vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
>  
>  	/* Set the border color to purple. */
> -	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
> +	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
>  
>  	if (DISPLAY_VER(dev_priv) != 2) {
>  		u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> @@ -800,7 +801,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  	}
>  
>  	/* Restore previous settings */
> -	intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
> +	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
> +		       save_bclrpat);
>  
>  	return status;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 776e4450e4af..49f7ac0f7997 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1870,7 +1870,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
>  
>  	/* Border color in case we don't scale up to the full screen. Black by
>  	 * default, change to something else for debugging. */
> -	intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
> +	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
>  }
>  
>  /* Prefer intel_encoder_is_combo() */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c47aae3f70cd..92d9e8cdf782 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1223,7 +1223,7 @@
>  #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
>  #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
>  #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
> -#define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
> +#define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
>  #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
>  #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
>  #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index e618a16eafac..5e1ef52922cc 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -237,7 +237,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
> -	MMIO_D(BCLRPAT(TRANSCODER_A));
> +	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
>  	MMIO_D(PIPESRC(TRANSCODER_A));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
> @@ -246,7 +246,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
> -	MMIO_D(BCLRPAT(TRANSCODER_B));
> +	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
>  	MMIO_D(PIPESRC(TRANSCODER_B));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
> @@ -255,7 +255,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
> -	MMIO_D(BCLRPAT(TRANSCODER_C));
> +	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
>  	MMIO_D(PIPESRC(TRANSCODER_C));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
> @@ -264,7 +264,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(BCLRPAT(TRANSCODER_EDP));
> +	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
> -- 
> 2.39.2
> 

Re: [PATCH 08/65] drm/i915: pass dev_priv explicitly to TRANS_VSYNC

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:26PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VSYNC register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
>  drivers/gpu/drm/i915/display/intel_crt.c         | 3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c     | 6 +++---
>  drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
>  6 files changed, 13 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 0ee42954054f..b267099fde8a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -967,7 +967,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	if (is_vid_mode(intel_dsi)) {
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
> +			intel_de_write(dev_priv,
> +				       TRANS_VSYNC(dev_priv, dsi_trans),
>  				       VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 54549d2cfcff..15569cf96c9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -746,7 +746,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  		* Yes, this will flicker
>  		*/
>  		if (vblank_start <= vactive && vblank_end >= vtotal) {
> -			u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
> +			u32 vsync = intel_de_read(dev_priv,
> +						  TRANS_VSYNC(dev_priv, cpu_transcoder));
>  			u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
>  
>  			vblank_start = vsync_start;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 87a690cf5808..776e4450e4af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2726,7 +2726,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
>  		       VBLANK_START(crtc_vblank_start - 1) |
>  		       VBLANK_END(crtc_vblank_end - 1));
> -	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
>  		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
>  		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
>  
> @@ -2837,7 +2837,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
>  		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
>  	}
> -	tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
> +	tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder));
>  	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
>  	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
>  
> @@ -8201,7 +8201,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
>  	intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
>  		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
> -	intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
>  		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
>  	intel_de_write(dev_priv, PIPESRC(pipe),
>  		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 03a33ff2653a..9f8269705171 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -235,7 +235,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 155259c11c88..c47aae3f70cd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1222,7 +1222,7 @@
>  #define TRANS_HSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
>  #define TRANS_VTOTAL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
>  #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
> -#define TRANS_VSYNC(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
> +#define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
>  #define BCLRPAT(trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
>  #define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
>  #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index baeedcdfdcab..e618a16eafac 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_VSYNC(TRANSCODER_A));
> +	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(BCLRPAT(TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
>  	MMIO_D(PIPESRC(TRANSCODER_A));
> @@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_VSYNC(TRANSCODER_B));
> +	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(BCLRPAT(TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
>  	MMIO_D(PIPESRC(TRANSCODER_B));
> @@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_VSYNC(TRANSCODER_C));
> +	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(BCLRPAT(TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
>  	MMIO_D(PIPESRC(TRANSCODER_C));
> @@ -263,7 +263,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
> +	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(BCLRPAT(TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
> -- 
> 2.39.2
> 

Re: [PATCH 11/65] drm/i915: pass dev_priv explicitly to PIPESRC

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:29PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPESRC register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_plane.c    | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
>  drivers/gpu/drm/i915/gvt/fb_decoder.c        | 6 +++---
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 6 +++---
>  5 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 5c8778865156..864d94406894 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -1053,7 +1053,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	drm_WARN_ON(&dev_priv->drm, offset != 0);
>  
> -	val = intel_de_read(dev_priv, PIPESRC(pipe));
> +	val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe));
>  	fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
>  	fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 993eb0935f6b..81ae72648e8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2784,7 +2784,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
>  	/* pipesrc controls the size that is scaled from, which should
>  	 * always be the user's requested size.
>  	 */
> -	intel_de_write(dev_priv, PIPESRC(pipe),
> +	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
>  		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
>  }
>  
> @@ -2878,7 +2878,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	u32 tmp;
>  
> -	tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
> +	tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));
>  
>  	drm_rect_init(&pipe_config->pipe_src, 0, 0,
>  		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
> @@ -8204,7 +8204,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
>  	intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder),
>  		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
> -	intel_de_write(dev_priv, PIPESRC(pipe),
> +	intel_de_write(dev_priv, PIPESRC(dev_priv, pipe),
>  		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
>  
>  	intel_de_write(dev_priv, FP0(pipe), fp);
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 0afde865a7de..c454e25b2b0f 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -267,11 +267,11 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
>  		(_PRI_PLANE_STRIDE_MASK >> 6) :
>  		_PRI_PLANE_STRIDE_MASK, plane->bpp);
>  
> -	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
> +	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >>
>  		_PIPE_H_SRCSZ_SHIFT;
>  	plane->width += 1;
> -	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
> -			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
> +	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) &
> +			 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
>  	plane->height += 1;	/* raw height is one minus the real value */
>  
>  	val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d961f3f70aaa..2e26464672f7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1225,7 +1225,7 @@
>  #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
>  #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
>  #define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
> -#define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
> +#define PIPESRC(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
>  #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>  
>  /* VRR registers */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 5abae7df0bfe..ff561a1e0fd3 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -239,7 +239,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPESRC(TRANSCODER_A));
> +	MMIO_D(PIPESRC(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
> @@ -248,7 +248,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPESRC(TRANSCODER_B));
> +	MMIO_D(PIPESRC(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
> @@ -257,7 +257,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPESRC(TRANSCODER_C));
> +	MMIO_D(PIPESRC(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 10/65] drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:28PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VSYNCSHIFT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           | 3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c     | 3 ++-
>  drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c      | 8 ++++----
>  5 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b267099fde8a..0625c4d5ee0b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -982,7 +982,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>  	if (is_vid_mode(intel_dsi)) {
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
> +			intel_de_write(dev_priv,
> +				       TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
>  				       vsync_shift);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 49f7ac0f7997..993eb0935f6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2707,7 +2707,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 4)
> -		intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
> +		intel_de_write(dev_priv,
> +			       TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder),
>  			       vsyncshift);
>  
>  	intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 9f8269705171..6a45bc1651c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -237,7 +237,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
>  		       intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
>  	intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
> -		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
> +		       intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));
>  }
>  
>  static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 92d9e8cdf782..d961f3f70aaa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1224,7 +1224,7 @@
>  #define TRANS_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
>  #define TRANS_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
>  #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
> -#define TRANS_VSYNCSHIFT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
> +#define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
>  #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
>  #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>  
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 5e1ef52922cc..5abae7df0bfe 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -238,7 +238,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A));
> -	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
> +	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPESRC(TRANSCODER_A));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
> @@ -247,7 +247,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B));
> -	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
> +	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPESRC(TRANSCODER_B));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
> @@ -256,7 +256,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C));
> -	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
> +	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPESRC(TRANSCODER_C));
>  	MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
> @@ -265,7 +265,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
> +	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
> -- 
> 2.39.2
> 

Re: [PATCH 12/65] drm/i915: pass dev_priv explicitly to TRANS_MULT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:30PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_MULT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 6 +++---
>  3 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 81ae72648e8e..e7ee4970e306 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1646,7 +1646,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>  		intel_vrr_set_transcoder_timings(crtc_state);
>  
>  	if (cpu_transcoder != TRANSCODER_EDP)
> -		intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
> +		intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
>  			       crtc_state->pixel_multiplier - 1);
>  
>  	hsw_set_frame_start_delay(crtc_state);
> @@ -3861,7 +3861,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>  	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
>  		pipe_config->pixel_multiplier =
>  			intel_de_read(dev_priv,
> -				      TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
> +				      TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;
>  	} else {
>  		pipe_config->pixel_multiplier = 1;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2e26464672f7..3bb895d030ab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1226,7 +1226,7 @@
>  #define BCLRPAT(dev_priv, trans)		_MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
>  #define TRANS_VSYNCSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
>  #define PIPESRC(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
> -#define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
> +#define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>  
>  /* VRR registers */
>  #define _TRANS_VRR_CTL_A		0x60420
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index ff561a1e0fd3..600e89148f77 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -506,9 +506,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(GAMMA_MODE(PIPE_A));
>  	MMIO_D(GAMMA_MODE(PIPE_B));
>  	MMIO_D(GAMMA_MODE(PIPE_C));
> -	MMIO_D(TRANS_MULT(TRANSCODER_A));
> -	MMIO_D(TRANS_MULT(TRANSCODER_B));
> -	MMIO_D(TRANS_MULT(TRANSCODER_C));
> +	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A));
> +	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B));
> +	MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C));
>  	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A));
>  	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B));
>  	MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));
> -- 
> 2.39.2
> 

Re: [PATCH 13/65] drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:31PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PORT_HOTPLUG_EN register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c         | 2 +-
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  3 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 2660c4a53e6f..b7eab52b64b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -603,7 +603,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
>  					      CRT_HOTPLUG_FORCE_DETECT,
>  					      CRT_HOTPLUG_FORCE_DETECT);
>  		/* wait for FORCE_DETECT to go off */
> -		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
> +		if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
>  					    CRT_HOTPLUG_FORCE_DETECT, 1000))
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "timed out waiting for FORCE_DETECT to go off");
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index d270bb7b9462..90fe5f8538e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -186,7 +186,8 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
>  	lockdep_assert_held(&dev_priv->irq_lock);
>  	drm_WARN_ON(&dev_priv->drm, bits & ~mask);
>  
> -	intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits);
> +	intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask,
> +			 bits);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3bb895d030ab..4508c535f320 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1378,7 +1378,7 @@
>  
>  
>  /* Hotplug control (945+ only) */
> -#define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
> +#define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
>  #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
>  #define   PORTC_HOTPLUG_INT_EN			(1 << 28)
>  #define   PORTD_HOTPLUG_INT_EN			(1 << 27)
> -- 
> 2.39.2
> 

Re: [PATCH 14/65] drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:32PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PORT_HOTPLUG_STAT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c            | 2 +-
>  drivers/gpu/drm/i915/display/intel_crt.c         | 5 +++--
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 9 ++++++---
>  drivers/gpu/drm/i915/i915_irq.c                  | 5 +++--
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  6 files changed, 15 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 06ec04e667e3..40fee8380a81 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -1228,7 +1228,7 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder)
>  		return false;
>  	}
>  
> -	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
> +	return intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)) & bit;
>  }
>  
>  static bool ilk_digital_port_connected(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index b7eab52b64b6..808fa8afb164 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -609,12 +609,13 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
>  				    "timed out waiting for FORCE_DETECT to go off");
>  	}
>  
> -	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
> +	stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
>  	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
>  		ret = true;
>  
>  	/* clear the interrupt we just generated, if any */
> -	intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
> +	intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
> +		       CRT_HOTPLUG_INT_STATUS);
>  
>  	i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 1674570dff1e..be5b48861baf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1377,7 +1377,7 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
>  		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
>  
>  	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
> -	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0);
> +	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 90fe5f8538e1..a1f07ee69a86 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -435,18 +435,21 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
>  	 * bits can itself generate a new hotplug interrupt :(
>  	 */
>  	for (i = 0; i < 10; i++) {
> -		u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask;
> +		u32 tmp = intel_uncore_read(&dev_priv->uncore,
> +					    PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask;
>  
>  		if (tmp == 0)
>  			return hotplug_status;
>  
>  		hotplug_status |= tmp;
> -		intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status);
> +		intel_uncore_write(&dev_priv->uncore,
> +				   PORT_HOTPLUG_STAT(dev_priv),
> +				   hotplug_status);
>  	}
>  
>  	drm_WARN_ONCE(&dev_priv->drm, 1,
>  		      "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
> -		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
> +		      intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv)));
>  
>  	return hotplug_status;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 678d632ed043..8059ac7e15fe 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1040,7 +1040,8 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
>  
>  	if (I915_HAS_HOTPLUG(dev_priv)) {
>  		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> -		intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0);
> +		intel_uncore_rmw(&dev_priv->uncore,
> +				 PORT_HOTPLUG_STAT(dev_priv), 0, 0);
>  	}
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
> @@ -1149,7 +1150,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
>  	struct intel_uncore *uncore = &dev_priv->uncore;
>  
>  	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> -	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0);
> +	intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0);
>  
>  	i9xx_pipestat_irq_reset(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4508c535f320..166c7f4f9c6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1408,7 +1408,7 @@
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
>  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
>  
> -#define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
> +#define PORT_HOTPLUG_STAT(dev_priv)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
>  /* HDMI/DP bits are g4x+ */
>  #define   PORTD_HOTPLUG_LIVE_STATUS_G4X		(1 << 27)
>  #define   PORTC_HOTPLUG_LIVE_STATUS_G4X		(1 << 28)
> -- 
> 2.39.2
> 

Re: [PATCH 15/65] drm/i915: pass dev_priv explicitly to PFIT_CONTROL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:33PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PFIT_CONTROL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++-----
>  drivers/gpu/drm/i915/display/intel_lvds.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h              |  2 +-
>  4 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e7ee4970e306..49672694293f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1861,12 +1861,13 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
>  	 * according to register description and PRM.
>  	 */
>  	drm_WARN_ON(&dev_priv->drm,
> -		    intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
> +		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
>  	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
>  
>  	intel_de_write(dev_priv, PFIT_PGM_RATIOS,
>  		       crtc_state->gmch_pfit.pgm_ratios);
> -	intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
> +	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
> +		       crtc_state->gmch_pfit.control);
>  
>  	/* Border color in case we don't scale up to the full screen. Black by
>  	 * default, change to something else for debugging. */
> @@ -2195,8 +2196,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>  	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
>  
>  	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
> -		    intel_de_read(dev_priv, PFIT_CONTROL));
> -	intel_de_write(dev_priv, PFIT_CONTROL, 0);
> +		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)));
> +	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0);
>  }
>  
>  static void i9xx_crtc_disable(struct intel_atomic_state *state,
> @@ -2974,7 +2975,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
>  	if (!i9xx_has_pfit(dev_priv))
>  		return;
>  
> -	tmp = intel_de_read(dev_priv, PFIT_CONTROL);
> +	tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
>  	if (!(tmp & PFIT_ENABLE))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 891777481dd9..9f018503d4fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  
>  	/* gen2/3 store dither state in pfit control, needs to match */
>  	if (DISPLAY_VER(dev_priv) < 4) {
> -		tmp = intel_de_read(dev_priv, PFIT_CONTROL);
> +		tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
>  
>  		crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 1c2099ed5514..e41881f08d1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -950,7 +950,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>  	} else {
>  		u32 tmp;
>  
> -		if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
> +		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
>  			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
>  		else
>  			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 166c7f4f9c6c..b0dbe6113bbc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1588,7 +1588,7 @@
>  #define   VIDEO_DIP_ENABLE_AS_ADL	REG_BIT(23)
>  
>  /* Panel fitting */
> -#define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
> +#define PFIT_CONTROL(dev_priv)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
>  #define   PFIT_ENABLE			REG_BIT(31)
>  #define   PFIT_PIPE_MASK		REG_GENMASK(30, 29) /* 965+ */
>  #define   PFIT_PIPE(pipe)		REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
> -- 
> 2.39.2
> 

Re: [PATCH 17/65] drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:35PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PFIT_AUTO_RATIOS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_overlay.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 117120ce5a1d..d3d0e22cdd34 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -951,7 +951,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>  		u32 tmp;
>  
>  		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
> -			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
> +			tmp = intel_de_read(dev_priv,
> +					    PFIT_AUTO_RATIOS(dev_priv));
>  		else
>  			tmp = intel_de_read(dev_priv,
>  					    PFIT_PGM_RATIOS(dev_priv));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 094e693c40bf..cd6eda1b6bef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1617,7 +1617,7 @@
>  #define   PFIT_VERT_SCALE_MASK_965	REG_GENMASK(28, 16) /* 965+ */
>  #define   PFIT_HORIZ_SCALE_MASK_965	REG_GENMASK(12, 0) /* 965+ */
>  
> -#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
> +#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
>  
>  #define PCH_GTC_CTL		_MMIO(0xe7000)
>  #define   PCH_GTC_ENABLE	(1 << 31)
> -- 
> 2.39.2
> 

Re: [PATCH 16/65] drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:34PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PFIT_PGM_RATIOS register macro.
> 

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/display/intel_overlay.c | 5 +++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  3 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 49672694293f..1e2ddae5ba94 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1864,7 +1864,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
>  		    intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE);
>  	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
>  
> -	intel_de_write(dev_priv, PFIT_PGM_RATIOS,
> +	intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv),
>  		       crtc_state->gmch_pfit.pgm_ratios);
>  	intel_de_write(dev_priv, PFIT_CONTROL(dev_priv),
>  		       crtc_state->gmch_pfit.control);
> @@ -2990,7 +2990,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
>  
>  	crtc_state->gmch_pfit.control = tmp;
>  	crtc_state->gmch_pfit.pgm_ratios =
> -		intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> +		intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
>  }
>  
>  static enum intel_output_format
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index e41881f08d1f..117120ce5a1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -943,7 +943,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>  	 * line with the intel documentation for the i965
>  	 */
>  	if (DISPLAY_VER(dev_priv) >= 4) {
> -		u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> +		u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv));
>  
>  		/* on i965 use the PGM reg to read out the autoscaler values */
>  		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
> @@ -953,7 +953,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>  		if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE)
>  			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
>  		else
> -			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
> +			tmp = intel_de_read(dev_priv,
> +					    PFIT_PGM_RATIOS(dev_priv));
>  
>  		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b0dbe6113bbc..094e693c40bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1609,7 +1609,7 @@
>  #define   PFIT_HORIZ_AUTO_SCALE		REG_BIT(5) /* pre-965 */
>  #define   PFIT_PANEL_8TO6_DITHER_ENABLE	REG_BIT(3) /* pre-965 */
>  
> -#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
> +#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
>  #define   PFIT_VERT_SCALE_MASK		REG_GENMASK(31, 20) /* pre-965 */
>  #define   PFIT_VERT_SCALE(x)		REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
>  #define   PFIT_HORIZ_SCALE_MASK		REG_GENMASK(15, 4) /* pre-965 */
> -- 
> 2.39.2
> 

Re: [PATCH 18/65] drm/i915: pass dev_priv explicitly to TRANSCONF

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:36PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANSCONF register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        | 12 +++--
>  drivers/gpu/drm/i915/display/intel_crt.c      | 11 ++--
>  drivers/gpu/drm/i915/display/intel_display.c  | 52 +++++++++++--------
>  .../i915/display/intel_display_power_well.c   |  8 +--
>  drivers/gpu/drm/i915/display/intel_drrs.c     |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c      |  6 +--
>  .../gpu/drm/i915/display/intel_pch_display.c  |  7 +--
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |  3 +-
>  drivers/gpu/drm/i915/gvt/display.c            | 12 ++---
>  drivers/gpu/drm/i915/gvt/handlers.c           | 12 +++--
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  8 +--
>  12 files changed, 76 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 0625c4d5ee0b..9beb94494b2b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1013,10 +1013,11 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);
> -		intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
> +		intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
> +			     TRANSCONF_ENABLE);
>  
>  		/* wait for transcoder to be enabled */
> -		if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
> +		if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
>  					  TRANSCONF_STATE_ENABLE, 10))
>  			drm_err(&dev_priv->drm,
>  				"DSI transcoder not enabled\n");
> @@ -1279,10 +1280,11 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
>  		dsi_trans = dsi_port_to_transcoder(port);
>  
>  		/* disable transcoder */
> -		intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
> +		intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
> +			     TRANSCONF_ENABLE, 0);
>  
>  		/* wait for transcoder to be disabled */
> -		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
> +		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
>  					    TRANSCONF_STATE_ENABLE, 50))
>  			drm_err(&dev_priv->drm,
>  				"DSI trancoder not disabled\n");
> @@ -1714,7 +1716,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
>  			goto out;
>  		}
>  
> -		tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
> +		tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
>  		ret = tmp & TRANSCONF_ENABLE;
>  	}
>  out:
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 808fa8afb164..d4f16d894eda 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -725,11 +725,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  	intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
>  
>  	if (DISPLAY_VER(dev_priv) != 2) {
> -		u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> +		u32 transconf = intel_de_read(dev_priv,
> +					      TRANSCONF(dev_priv, cpu_transcoder));
>  
> -		intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
> +		intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
>  			       transconf | TRANSCONF_FORCE_BORDER);
> -		intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> +		intel_de_posting_read(dev_priv,
> +				      TRANSCONF(dev_priv, cpu_transcoder));
>  		/* Wait for next Vblank to substitue
>  		 * border color for Color info */
>  		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
> @@ -738,7 +740,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  			connector_status_connected :
>  			connector_status_disconnected;
>  
> -		intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
> +		intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
> +			       transconf);
>  	} else {
>  		bool restore_vblank = false;
>  		int count, detect;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1e2ddae5ba94..9434eba91839 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -307,7 +307,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
>  		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>  
>  		/* Wait for the Pipe State to go off */
> -		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
> +		if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
>  					    TRANSCONF_STATE_ENABLE, 100))
>  			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
>  	} else {
> @@ -329,7 +329,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
>  	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
>  	if (wakeref) {
> -		u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> +		u32 val = intel_de_read(dev_priv,
> +					TRANSCONF(dev_priv, cpu_transcoder));
>  		cur_state = !!(val & TRANSCONF_ENABLE);
>  
>  		intel_display_power_put(dev_priv, power_domain, wakeref);
> @@ -453,7 +454,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  			     clear, set);
>  	}
>  
> -	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  	if (val & TRANSCONF_ENABLE) {
>  		/* we keep both pipes enabled on 830 */
>  		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
> @@ -468,9 +469,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
>  	}
>  
> -	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
>  		       val | TRANSCONF_ENABLE);
> -	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  
>  	/*
>  	 * Until the pipe starts PIPEDSL reads will return a stale value,
> @@ -499,7 +500,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
>  	 */
>  	assert_planes_disabled(crtc);
>  
> -	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  	if ((val & TRANSCONF_ENABLE) == 0)
>  		return;
>  
> @@ -519,7 +520,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
>  	    old_crtc_state->dsc.compression_enable)
>  		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
>  
> -	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
>  
>  	if (DISPLAY_VER(dev_priv) >= 12)
>  		intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
> @@ -2799,9 +2800,11 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
>  
>  	if (DISPLAY_VER(dev_priv) >= 9 ||
>  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
> +		return intel_de_read(dev_priv,
> +				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
>  	else
> -		return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
> +		return intel_de_read(dev_priv,
> +				     TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
>  }
>  
>  static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> @@ -2952,8 +2955,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  
>  	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
>  
> -	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> -	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  }
>  
>  static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
> @@ -3035,7 +3038,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  
>  	ret = false;
>  
> -	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
> +	tmp = intel_de_read(dev_priv,
> +			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
>  	if (!(tmp & TRANSCONF_ENABLE))
>  		goto out;
>  
> @@ -3182,8 +3186,8 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>  	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
>  	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
>  
> -	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> -	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  }
>  
>  static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
> @@ -3212,8 +3216,8 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
>  	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
>  		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
>  
> -	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> -	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val);
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
>  }
>  
>  static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
> @@ -3408,7 +3412,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->shared_dpll = NULL;
>  
>  	ret = false;
> -	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
> +	tmp = intel_de_read(dev_priv,
> +			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
>  	if (!(tmp & TRANSCONF_ENABLE))
>  		goto out;
>  
> @@ -3721,7 +3726,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>  			pipe_config->pch_pfit.force_thru = true;
>  	}
>  
> -	tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
> +	tmp = intel_de_read(dev_priv,
> +			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
>  
>  	return tmp & TRANSCONF_ENABLE;
>  }
> @@ -3827,7 +3833,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>  
>  	if (IS_HASWELL(dev_priv)) {
>  		u32 tmp = intel_de_read(dev_priv,
> -					TRANSCONF(pipe_config->cpu_transcoder));
> +					TRANSCONF(dev_priv, pipe_config->cpu_transcoder));
>  
>  		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
>  			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
> @@ -8238,8 +8244,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		udelay(150); /* wait for warmup */
>  	}
>  
> -	intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
> -	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE);
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
>  
>  	intel_wait_for_pipe_scanline_moving(crtc);
>  }
> @@ -8262,8 +8268,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	drm_WARN_ON(&dev_priv->drm,
>  		    intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK);
>  
> -	intel_de_write(dev_priv, TRANSCONF(pipe), 0);
> -	intel_de_posting_read(dev_priv, TRANSCONF(pipe));
> +	intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0);
> +	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe));
>  
>  	intel_wait_for_pipe_scanline_stopped(crtc);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 3b6cb237d80a..919f712fef13 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1044,9 +1044,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
>  static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
>  					 struct i915_power_well *power_well)
>  {
> -	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
> +	if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0)
>  		i830_enable_pipe(dev_priv, PIPE_A);
> -	if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
> +	if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0)
>  		i830_enable_pipe(dev_priv, PIPE_B);
>  }
>  
> @@ -1060,8 +1060,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
>  static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
>  					  struct i915_power_well *power_well)
>  {
> -	return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
> -		intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
> +	return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE &&
> +		intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
>  }
>  
>  static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 597f8bd6aa1a..5250622f1479 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -85,7 +85,7 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,
>  	else
>  		bit = TRANSCONF_REFRESH_RATE_ALT_ILK;
>  
> -	intel_de_rmw(dev_priv, TRANSCONF(cpu_transcoder),
> +	intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
>  		     bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 295a0f24ebbf..8b17b8ad71c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1034,7 +1034,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
>  	temp = intel_de_read(dev_priv, reg);
>  	temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
>  	temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
> -	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> +	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
>  	intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
>  
>  	intel_de_posting_read(dev_priv, reg);
> @@ -1090,7 +1090,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>  	reg = FDI_RX_CTL(pipe);
>  	temp = intel_de_read(dev_priv, reg);
>  	temp &= ~(0x7 << 16);
> -	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> +	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
>  	intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
>  
>  	intel_de_posting_read(dev_priv, reg);
> @@ -1116,7 +1116,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
>  	}
>  	/* BPC in FDI rx is consistent with that in TRANSCONF */
>  	temp &= ~(0x07 << 16);
> -	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> +	temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11;
>  	intel_de_write(dev_priv, reg, temp);
>  
>  	intel_de_posting_read(dev_priv, reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 6a45bc1651c3..0d48b9bec29c 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -271,7 +271,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  
>  	reg = PCH_TRANSCONF(pipe);
>  	val = intel_de_read(dev_priv, reg);
> -	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe));
> +	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
>  
>  	if (HAS_PCH_IBX(dev_priv)) {
>  		/* Configure frame start delay to match the CPU */
> @@ -413,7 +413,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
>  	    intel_crtc_has_dp_encoder(crtc_state)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&crtc_state->hw.adjusted_mode;
> -		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5;
> +		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
>  		i915_reg_t reg = TRANS_DP_CTL(pipe);
>  		enum port port;
>  
> @@ -557,7 +557,8 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
>  
>  	val = TRANS_ENABLE;
> -	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> +	pipeconf_val = intel_de_read(dev_priv,
> +				     TRANSCONF(dev_priv, cpu_transcoder));
>  
>  	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
>  		val |= TRANS_INTERLACE_INTERLACED;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index ee9923c7b115..eae5b5e09aa8 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -972,7 +972,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>  		 */
>  		if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
>  		    port == PORT_C)
> -			enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
> +			enabled = intel_de_read(display,
> +						TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE;
>  
>  		/* Try command mode if video mode not enabled */
>  		if (!enabled) {
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index eaa92d392189..ad21b8f65d6b 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
>  
> -	if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE))
> +	if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE))
>  		return 0;
>  
>  	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
> @@ -83,7 +83,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
>  			pipe < PIPE_A || pipe >= I915_MAX_PIPES))
>  		return -EINVAL;
>  
> -	if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE)
> +	if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE)
>  		return 1;
>  
>  	if (edp_pipe_is_enabled(vgpu) &&
> @@ -191,7 +191,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
>  
>  		for_each_pipe(dev_priv, pipe) {
> -			vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &=
> +			vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &=
>  				~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
>  			vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE;
>  			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
> @@ -252,8 +252,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
>  		 *   setup_virtual_dp_monitor.
>  		 */
> -		vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
> -		vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
> +		vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
> +		vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
>  
>  		/*
>  		 * Golden M/N are calculated based on:
> @@ -510,7 +510,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE;
>  	}
>  
> -	vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
> +	vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE;
>  }
>  
>  static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 00cf35a9669e..039d2cb273df 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2270,10 +2270,14 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>  	MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>  
>  	/* display */
> -	MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write);
> -	MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write);
> -	MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write);
> -	MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write);
> +	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,
> +		pipeconf_mmio_write);
> +	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,
> +		pipeconf_mmio_write);
> +	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,
> +		pipeconf_mmio_write);
> +	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,
> +		pipeconf_mmio_write);
>  	MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
>  	MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
>  		reg50080_mmio_write);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cd6eda1b6bef..72f5140cf109 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1876,7 +1876,7 @@
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
> -#define TRANSCONF(trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
> +#define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
>  #define PIPEDSL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 600e89148f77..436d4a2eccd7 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -130,10 +130,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPEDSL(PIPE_B));
>  	MMIO_D(PIPEDSL(PIPE_C));
>  	MMIO_D(PIPEDSL(_PIPE_EDP));
> -	MMIO_D(TRANSCONF(TRANSCODER_A));
> -	MMIO_D(TRANSCONF(TRANSCODER_B));
> -	MMIO_D(TRANSCONF(TRANSCODER_C));
> -	MMIO_D(TRANSCONF(TRANSCODER_EDP));
> +	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
> +	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
> +	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
> +	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPESTAT(PIPE_A));
>  	MMIO_D(PIPESTAT(PIPE_B));
>  	MMIO_D(PIPESTAT(PIPE_C));
> -- 
> 2.39.2
> 

Re: [PATCH 19/65] drm/i915: pass dev_priv explicitly to PIPEDSL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:37PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPEDSL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c    | 6 +++---
>  drivers/gpu/drm/i915/display/intel_hdmi.c   | 3 ++-
>  drivers/gpu/drm/i915/display/intel_vblank.c | 7 ++++---
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
>  5 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index d4f16d894eda..835c8b844494 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -771,9 +771,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  		/*
>  		 * Wait for the border to be displayed
>  		 */
> -		while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
> +		while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
>  			;
> -		while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
> +		while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
>  			;
>  		/*
>  		 * Watch ST00 for an entire scanline
> @@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  			st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
>  			if (st00 & (1 << 4))
>  				detect++;
> -		} while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
> +		} while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
>  
>  		/* restore vblank if necessary */
>  		if (restore_vblank)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 06ec9ce7fe1c..7704ead5002d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1476,7 +1476,8 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
>  	int ret;
>  
>  	for (;;) {
> -		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
> +		scanline = intel_de_read(dev_priv,
> +					 PIPEDSL(dev_priv, crtc->pipe));
>  		if (scanline > 100 && scanline < 200)
>  			break;
>  		usleep_range(25, 50);
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index eb80952b0cfd..e2d20064e68d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -247,7 +247,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  
>  	vtotal = intel_mode_vtotal(mode);
>  
> -	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
> +	position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>  
>  	/*
>  	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
> @@ -266,7 +266,8 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  
>  		for (i = 0; i < 100; i++) {
>  			udelay(1);
> -			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
> +			temp = intel_de_read_fw(dev_priv,
> +						PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>  			if (temp != position) {
>  				position = temp;
>  				break;
> @@ -473,7 +474,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
>  static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
>  				    enum pipe pipe)
>  {
> -	i915_reg_t reg = PIPEDSL(pipe);
> +	i915_reg_t reg = PIPEDSL(dev_priv, pipe);
>  	u32 line1, line2;
>  
>  	line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 72f5140cf109..fbd004bd1992 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1877,7 +1877,7 @@
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
>  #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
> -#define PIPEDSL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
> +#define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
>  #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 436d4a2eccd7..6a37f790c753 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -126,10 +126,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(_MMIO(0x650b4));
>  	MMIO_D(_MMIO(0xc4040));
>  	MMIO_D(DERRMR);
> -	MMIO_D(PIPEDSL(PIPE_A));
> -	MMIO_D(PIPEDSL(PIPE_B));
> -	MMIO_D(PIPEDSL(PIPE_C));
> -	MMIO_D(PIPEDSL(_PIPE_EDP));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_A));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_B));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_C));
> +	MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
> -- 
> 2.39.2
> 

Re: [PATCH 20/65] drm/i915: pass dev_priv explicitly to PIPEFRAME

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:38PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPEFRAME register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index e2d20064e68d..ac8ad3ebf4a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -102,7 +102,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>  	 * we get a low value that's stable across two reads of the high
>  	 * register.
>  	 */
> -	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe));
> +	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe),
> +				     PIPEFRAME(dev_priv, pipe));
>  
>  	pixel = frame & PIPE_PIXEL_MASK;
>  	frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbd004bd1992..c4f8c50f61d4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1878,7 +1878,7 @@
>  
>  #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
>  #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
> -#define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
> +#define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
>  #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>  
> -- 
> 2.39.2
> 

Re: [PATCH 21/65] drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:39PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPEFRAMEPIXEL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index ac8ad3ebf4a4..c6e68c0604b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -102,7 +102,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>  	 * we get a low value that's stable across two reads of the high
>  	 * register.
>  	 */
> -	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe),
> +	frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe),
>  				     PIPEFRAME(dev_priv, pipe));
>  
>  	pixel = frame & PIPE_PIXEL_MASK;
> @@ -386,7 +386,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>  		 * We can split this into vertical and horizontal
>  		 * scanout position.
>  		 */
> -		position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
> +		position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>  
>  		/* convert to pixel counts */
>  		vbl_start *= htotal;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c4f8c50f61d4..a6dff480bd0b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1879,7 +1879,7 @@
>  #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
>  #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
> -#define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
> +#define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
>  #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>  
>  #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
> -- 
> 2.39.2
> 

Re: [PATCH 22/65] drm/i915: pass dev_priv explicitly to PIPESTAT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:40PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPESTAT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c   | 9 +++++----
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c        | 8 ++++----
>  4 files changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index be5b48861baf..76bba95410e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -224,7 +224,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
>  void i915_enable_pipestat(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, u32 status_mask)
>  {
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  	u32 enable_mask;
>  
>  	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
> @@ -247,7 +247,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
>  void i915_disable_pipestat(struct drm_i915_private *dev_priv,
>  			   enum pipe pipe, u32 status_mask)
>  {
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  	u32 enable_mask;
>  
>  	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
> @@ -400,7 +400,8 @@ void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
>  	enum pipe pipe;
>  
>  	for_each_pipe(dev_priv, pipe) {
> -		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
> +		intel_uncore_write(&dev_priv->uncore,
> +				   PIPESTAT(dev_priv, pipe),
>  				   PIPESTAT_INT_STATUS_MASK |
>  				   PIPE_FIFO_UNDERRUN_STATUS);
>  
> @@ -453,7 +454,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
>  		if (!status_mask)
>  			continue;
>  
> -		reg = PIPESTAT(pipe);
> +		reg = PIPESTAT(dev_priv, pipe);
>  		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
>  		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 09a7fa6c0c37..401726f466c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -94,7 +94,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
>  static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	i915_reg_t reg = PIPESTAT(crtc->pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
>  	u32 enable_mask;
>  
>  	lockdep_assert_held(&dev_priv->irq_lock);
> @@ -115,7 +115,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
>  					     bool enable, bool old)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  
>  	lockdep_assert_held(&dev_priv->irq_lock);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a6dff480bd0b..0aaceedf77dc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1880,7 +1880,7 @@
>  #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
> -#define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
> +#define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>  
>  #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
>  #define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 6a37f790c753..00ee588fab39 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -134,10 +134,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPESTAT(PIPE_A));
> -	MMIO_D(PIPESTAT(PIPE_B));
> -	MMIO_D(PIPESTAT(PIPE_C));
> -	MMIO_D(PIPESTAT(_PIPE_EDP));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_A));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_B));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_C));
> +	MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
> -- 
> 2.39.2
> 

Re: [PATCH 23/65] drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:41PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_ARB_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9434eba91839..48ee8aee21be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -439,7 +439,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  
>  	/* Wa_22012358565:adl-p */
>  	if (DISPLAY_VER(dev_priv) == 13)
> -		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
> +		intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
>  			     0, PIPE_ARB_USE_PROG_SLOTS);
>  
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0aaceedf77dc..1b2c0d650bff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1883,7 +1883,7 @@
>  #define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>  
>  #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
> -#define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
> +#define PIPE_ARB_CTL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
>  #define   PIPE_ARB_USE_PROG_SLOTS	REG_BIT(13)
>  
>  #define _PIPE_MISC_A			0x70030
> -- 
> 2.39.2
> 

Re: [PATCH 24/65] drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:42PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the ICL_PIPESTATUS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 9 ++++++---
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 +-
>  2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 401726f466c0..e5e4ca7cc499 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -209,7 +209,8 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
>  
>  	if (enable) {
>  		if (DISPLAY_VER(dev_priv) >= 11)
> -			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),
> +			intel_de_write(dev_priv,
> +				       ICL_PIPESTATUS(dev_priv, pipe),
>  				       icl_pipe_status_underrun_mask(dev_priv));
>  
>  		bdw_enable_pipe_irq(dev_priv, pipe, mask);
> @@ -418,9 +419,11 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
>  	 * the underrun was caused by the downstream port.
>  	 */
>  	if (DISPLAY_VER(dev_priv) >= 11) {
> -		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
> +		underruns = intel_de_read(dev_priv,
> +					  ICL_PIPESTATUS(dev_priv, pipe)) &
>  			icl_pipe_status_underrun_mask(dev_priv);
> -		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
> +		intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe),
> +			       underruns);
>  	}
>  
>  	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b2c0d650bff..cbe109973f57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1927,7 +1927,7 @@
>  #define PIPE_MISC2(pipe)		_MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
>  
>  #define _ICL_PIPE_A_STATUS			0x70058
> -#define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
> +#define ICL_PIPESTATUS(dev_priv, pipe)			_MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
>  #define   PIPE_STATUS_UNDERRUN				REG_BIT(31)
>  #define   PIPE_STATUS_SOFT_UNDERRUN_XELPD		REG_BIT(28)
>  #define   PIPE_STATUS_HARD_UNDERRUN_XELPD		REG_BIT(27)
> -- 
> 2.39.2
> 

Re: [PATCH 25/65] drm/i915: pass dev_priv explicitly to DSPARB

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:43PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPARB register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 22 ++++++++++++----------
>  drivers/gpu/drm/i915/i915_reg.h        |  2 +-
>  drivers/gpu/drm/i915/i915_suspend.c    |  6 ++++--
>  3 files changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 628e7192ebc9..fd14010b4cc3 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  
>  	switch (pipe) {
>  	case PIPE_A:
> -		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb = intel_uncore_read(&dev_priv->uncore,
> +					   DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
>  		break;
>  	case PIPE_B:
> -		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb = intel_uncore_read(&dev_priv->uncore,
> +					   DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
> @@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x1ff;
> @@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  
>  	switch (crtc->pipe) {
>  	case PIPE_A:
> -		dsparb = intel_uncore_read_fw(uncore, DSPARB);
> +		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
>  
>  		dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
> @@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
>  			   VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
>  
> -		intel_uncore_write_fw(uncore, DSPARB, dsparb);
> +		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
>  		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
>  		break;
>  	case PIPE_B:
> -		dsparb = intel_uncore_read_fw(uncore, DSPARB);
> +		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
>  
>  		dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
> @@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
>  			   VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
>  
> -		intel_uncore_write_fw(uncore, DSPARB, dsparb);
> +		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
>  		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
>  		break;
>  	case PIPE_C:
> @@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		break;
>  	}
>  
> -	intel_uncore_posting_read_fw(uncore, DSPARB);
> +	intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
>  
>  	spin_unlock(&uncore->lock);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cbe109973f57..75223b8cb575 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1984,7 +1984,7 @@
>  #define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
>  #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
>  
> -#define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
> +#define DSPARB(dev_priv)			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
>  #define   DSPARB_BSTART_MASK	(0x7f)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 81def10eb58f..bc449613c848 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration control */
>  	if (GRAPHICS_VER(dev_priv) <= 4)
> -		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
> +		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
> +							     DSPARB(dev_priv));
>  
>  	if (GRAPHICS_VER(dev_priv) == 4)
>  		pci_read_config_word(pdev, GCDGMBUS,
> @@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration */
>  	if (GRAPHICS_VER(dev_priv) <= 4)
> -		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
> +		intel_de_write(dev_priv, DSPARB(dev_priv),
> +			       dev_priv->regfile.saveDSPARB);
>  
>  	intel_vga_redisable(dev_priv);
>  
> -- 
> 2.39.2
> 

Re: [PATCH 26/65] drm/i915: pass dev_priv explicitly to DSPFW1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:44PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPFW1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 25 +++++++++++++------------
>  drivers/gpu/drm/i915/i915_reg.h        |  2 +-
>  2 files changed, 14 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index fd14010b4cc3..e39415fb1c19 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -657,10 +657,10 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  					&pnv_display_wm,
>  					pnv_display_wm.fifo_size,
>  					cpp, latency->display_sr);
> -		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
>  		reg &= ~DSPFW_SR_MASK;
>  		reg |= FW_WM(wm, SR);
> -		intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), reg);
>  		drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
>  
>  		/* cursor SR */
> @@ -720,7 +720,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>  	for_each_pipe(dev_priv, pipe)
>  		trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm);
>  
> -	intel_uncore_write(&dev_priv->uncore, DSPFW1,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
>  			   FW_WM(wm->sr.plane, SR) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
> @@ -738,7 +738,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
>  			   FW_WM(wm->hpll.plane, HPLL_SR));
>  
> -	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
>  }
>  
>  #define FW_WM_VLV(value, plane) \
> @@ -770,7 +770,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  	intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
>  	intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
>  
> -	intel_uncore_write(&dev_priv->uncore, DSPFW1,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
>  			   FW_WM(wm->sr.plane, SR) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
> @@ -817,7 +817,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  				   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
>  	}
>  
> -	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
> +	intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv));
>  }
>  
>  #undef FW_WM_VLV
> @@ -2067,10 +2067,11 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
>  		    srwm);
>  
>  	/* 965 has limitations... */
> -	intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
> -		   FW_WM(8, CURSORB) |
> -		   FW_WM(8, PLANEB) |
> -		   FW_WM(8, PLANEA));
> +	intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv),
> +		           FW_WM(srwm, SR) |
> +		           FW_WM(8, CURSORB) |
> +		           FW_WM(8, PLANEB) |
> +		           FW_WM(8, PLANEA));
>  	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
>  		   FW_WM(8, PLANEC_OLD));
>  	/* update cursor SR watermark */
> @@ -3521,7 +3522,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>  {
>  	u32 tmp;
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
>  	wm->sr.plane = _FW_WM(tmp, SR);
>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
> @@ -3561,7 +3562,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  			(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
>  	}
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv));
>  	wm->sr.plane = _FW_WM(tmp, SR);
>  	wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75223b8cb575..5f1db52ee773 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2019,7 +2019,7 @@
>  #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
>  
>  /* pnv/gen4/g4x/vlv/chv */
> -#define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
> +#define DSPFW1(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
>  #define   DSPFW_SR_SHIFT		23
>  #define   DSPFW_SR_MASK			(0x1ff << 23)
>  #define   DSPFW_CURSORB_SHIFT		16
> -- 
> 2.39.2
> 

Re: [PATCH 27/65] drm/i915: pass dev_priv explicitly to DSPFW2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:45PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPFW2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 13 +++++++------
>  drivers/gpu/drm/i915/i915_reg.h        |  2 +-
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index e39415fb1c19..1e11d66d1a7e 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -725,7 +725,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> -	intel_uncore_write(&dev_priv->uncore, DSPFW2,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
>  			   (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
>  			   FW_WM(wm->sr.fbc, FBC_SR) |
>  			   FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
> @@ -775,7 +775,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
>  			   FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
>  			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
> -	intel_uncore_write(&dev_priv->uncore, DSPFW2,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
>  			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>  			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> @@ -2072,8 +2072,9 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
>  		           FW_WM(8, CURSORB) |
>  		           FW_WM(8, PLANEB) |
>  		           FW_WM(8, PLANEA));
> -	intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
> -		   FW_WM(8, PLANEC_OLD));
> +	intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
> +		           FW_WM(8, CURSORA) |
> +		           FW_WM(8, PLANEC_OLD));
>  	/* update cursor SR watermark */
>  	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
>  
> @@ -3528,7 +3529,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
>  	wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
>  	wm->sr.fbc = _FW_WM(tmp, FBC_SR);
>  	wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
> @@ -3568,7 +3569,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  	wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
>  	wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5f1db52ee773..8b642cb0d9b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2030,7 +2030,7 @@
>  #define   DSPFW_PLANEA_SHIFT		0
>  #define   DSPFW_PLANEA_MASK		(0x7f << 0)
>  #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
> -#define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
> +#define DSPFW2(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
>  #define   DSPFW_FBC_SR_EN		(1 << 31)	  /* g4x */
>  #define   DSPFW_FBC_SR_SHIFT		28
>  #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
> -- 
> 2.39.2
> 

Re: [PATCH 28/65] drm/i915: pass dev_priv explicitly to DSPFW3

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:46PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPFW3 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c        | 27 ++++++++++---------
>  .../drm/i915/display/intel_display_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +-
>  3 files changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 1e11d66d1a7e..3fe24bae0728 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -149,14 +149,14 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
>  		intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
>  		intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
>  	} else if (IS_PINEVIEW(dev_priv)) {
> -		val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> +		val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
>  		was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
>  		if (enable)
>  			val |= PINEVIEW_SELF_REFRESH_EN;
>  		else
>  			val &= ~PINEVIEW_SELF_REFRESH_EN;
> -		intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
> -		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), val);
> +		intel_uncore_posting_read(&dev_priv->uncore, DSPFW3(dev_priv));
>  	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
>  		was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
> @@ -668,7 +668,8 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  					&pnv_cursor_wm,
>  					pnv_display_wm.fifo_size,
>  					4, latency->cursor_sr);
> -		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK,
> +		intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
> +				 DSPFW_CURSOR_SR_MASK,
>  				 FW_WM(wm, CURSOR_SR));
>  
>  		/* Display HPLL off SR */
> @@ -676,17 +677,18 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  					&pnv_display_hplloff_wm,
>  					pnv_display_hplloff_wm.fifo_size,
>  					cpp, latency->display_hpll_disable);
> -		intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
> +		intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv),
> +				 DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR));
>  
>  		/* cursor HPLL off SR */
>  		wm = intel_calculate_wm(dev_priv, pixel_rate,
>  					&pnv_cursor_hplloff_wm,
>  					pnv_display_hplloff_wm.fifo_size,
>  					4, latency->cursor_hpll_disable);
> -		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> +		reg = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
>  		reg &= ~DSPFW_HPLL_CURSOR_MASK;
>  		reg |= FW_WM(wm, HPLL_CURSOR);
> -		intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
> +		intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
>  		drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
>  
>  		intel_set_memory_cxsr(dev_priv, true);
> @@ -732,7 +734,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> -	intel_uncore_write(&dev_priv->uncore, DSPFW3,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
>  			   (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
>  			   FW_WM(wm->sr.cursor, CURSOR_SR) |
>  			   FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
> @@ -779,7 +781,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
>  			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
>  			   FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
>  			   FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
> -	intel_uncore_write(&dev_priv->uncore, DSPFW3,
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
>  			   FW_WM(wm->sr.cursor, CURSOR_SR));
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> @@ -2076,7 +2078,8 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
>  		           FW_WM(8, CURSORA) |
>  		           FW_WM(8, PLANEC_OLD));
>  	/* update cursor SR watermark */
> -	intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
> +	intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv),
> +		           FW_WM(cursor_sr, CURSOR_SR));
>  
>  	if (cxsr_enabled)
>  		intel_set_memory_cxsr(dev_priv, true);
> @@ -3537,7 +3540,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
>  	wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>  	wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
> @@ -3574,7 +3577,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
>  	wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
>  	wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
>  
> -	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
> +	tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv));
>  	wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 86d9900c40af..b538a8204124 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -77,7 +77,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  	else if (IS_I915GM(dev_priv))
>  		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
> +		sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b642cb0d9b7..05e0013813f8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2046,7 +2046,7 @@
>  #define   DSPFW_SPRITEA_SHIFT		0
>  #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
>  #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
> -#define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
> +#define DSPFW3(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
>  #define   DSPFW_HPLL_SR_EN		(1 << 31)
>  #define   PINEVIEW_SELF_REFRESH_EN	(1 << 30)
>  #define   DSPFW_CURSOR_SR_SHIFT		24
> -- 
> 2.39.2
> 

Re: [PATCH 29/65] drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:47PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_FRMCOUNT_G4X register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
>  drivers/gpu/drm/i915/gvt/display.c          | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index c6e68c0604b3..4f3b80cd1674 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -125,7 +125,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
>  	if (!vblank->max_vblank_count)
>  		return 0;
>  
> -	return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe));
> +	return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe));
>  }
>  
>  static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index ad21b8f65d6b..3681dca165c6 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -647,7 +647,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
>  	}
>  
>  	if (pipe_is_enabled(vgpu, pipe)) {
> -		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
> +		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++;
>  		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 05e0013813f8..d62da57afda7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2257,7 +2257,7 @@
>  /* GM45+ just has to be different */
>  #define _PIPEA_FRMCOUNT_G4X	0x70040
>  #define _PIPEA_FLIPCOUNT_G4X	0x70044
> -#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
> +#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
>  #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
>  
>  /* CHV pipe B blender */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 00ee588fab39..2e027f3ee750 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -142,10 +142,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP));
> -	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A));
> -	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B));
> -	MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C));
> -	MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP));
> +	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
> +	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
> +	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
> +	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP));
>  	MMIO_D(CURCNTR(dev_priv, PIPE_A));
>  	MMIO_D(CURCNTR(dev_priv, PIPE_B));
>  	MMIO_D(CURCNTR(dev_priv, PIPE_C));
> -- 
> 2.39.2
> 

Re: [PATCH 30/65] drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:48PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_FLIPCOUNT_G4X register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/cmd_parser.c       | 2 +-
>  drivers/gpu/drm/i915/gvt/handlers.c         | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
>  4 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 9cdb53015d16..2f4c9c66b40b 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1437,7 +1437,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
>  	}
>  
>  	if (info->plane == PLANE_PRIMARY)
> -		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
> +		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++;
>  
>  	if (info->async_flip)
>  		intel_vgpu_trigger_virtual_event(vgpu, info->event);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 039d2cb273df..bb904266c3cd 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1021,7 +1021,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  	write_vreg(vgpu, offset, p_data, bytes);
>  	vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
>  
> -	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
> +	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
>  
>  	if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP)
>  		intel_vgpu_trigger_virtual_event(vgpu, event);
> @@ -1063,7 +1063,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu,
>  	write_vreg(vgpu, offset, p_data, bytes);
>  	if (plane == PLANE_PRIMARY) {
>  		vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
> -		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
> +		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
>  	} else {
>  		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d62da57afda7..5d9429bf17a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2258,7 +2258,7 @@
>  #define _PIPEA_FRMCOUNT_G4X	0x70040
>  #define _PIPEA_FLIPCOUNT_G4X	0x70044
>  #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
> -#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
> +#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
>  
>  /* CHV pipe B blender */
>  #define _CHV_BLEND_A		0x60a00
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 2e027f3ee750..ba3f734ced0b 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -138,10 +138,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPESTAT(dev_priv, PIPE_B));
>  	MMIO_D(PIPESTAT(dev_priv, PIPE_C));
>  	MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
> -	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A));
> -	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
> -	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
> -	MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP));
> +	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A));
> +	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B));
> +	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C));
> +	MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP));
>  	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A));
>  	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B));
>  	MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C));
> -- 
> 2.39.2
> 

Re: [PATCH 31/65] drm/i915: pass dev_priv explicitly to CHV_BLEND

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:49PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the CHV_BLEND register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 48ee8aee21be..a6d7928fbe37 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2108,7 +2108,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
>  	intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
>  
>  	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> -		intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> +		intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
> +			       CHV_BLEND_LEGACY);
>  		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5d9429bf17a8..ddfa77231426 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2271,7 +2271,7 @@
>  #define   CHV_CANVAS_GREEN_MASK	REG_GENMASK(19, 10)
>  #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
>  
> -#define CHV_BLEND(pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
> +#define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
>  #define CHV_CANVAS(pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
>  
>  /* Display/Sprite base address macros */
> -- 
> 2.39.2
> 

Re: [PATCH 32/65] drm/i915: pass dev_priv explicitly to CHV_CANVAS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:50PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the CHV_CANVAS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a6d7928fbe37..241121b0b3ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2110,7 +2110,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
>  	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>  		intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe),
>  			       CHV_BLEND_LEGACY);
> -		intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
> +		intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0);
>  	}
>  
>  	crtc->active = true;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ddfa77231426..8aa35bbb2e1b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2272,7 +2272,7 @@
>  #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
>  
>  #define CHV_BLEND(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
> -#define CHV_CANVAS(pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
> +#define CHV_CANVAS(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
>  
>  /* Display/Sprite base address macros */
>  #define DISP_BASEADDR_MASK	(0xfffff000)
> -- 
> 2.39.2
> 

Re: [PATCH 33/65] drm/i915: pass dev_priv explicitly to SWF0

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:51PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the SWF0 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++----
>  2 files changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8aa35bbb2e1b..8b379ff60070 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2290,7 +2290,7 @@
>   * [10:1f] all
>   * [30:32] all
>   */
> -#define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
> +#define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
>  #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
>  #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index bc449613c848..ac8221ae97f3 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -40,7 +40,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  	/* Scratch space */
>  	if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
> -			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
> +			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
> +								      SWF0(dev_priv, i));
>  			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  		}
>  		for (i = 0; i < 3; i++)
> @@ -50,7 +51,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
> -			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
> +			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
> +								      SWF0(dev_priv, i));
>  			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
>  		}
>  		for (i = 0; i < 3; i++)
> @@ -65,7 +67,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  	/* Scratch space */
>  	if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
>  		for (i = 0; i < 7; i++) {
> -			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			intel_de_write(dev_priv, SWF0(dev_priv, i),
> +				       dev_priv->regfile.saveSWF0[i]);
>  			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> @@ -75,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
> -			intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
> +			intel_de_write(dev_priv, SWF0(dev_priv, i),
> +				       dev_priv->regfile.saveSWF0[i]);
>  			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> -- 
> 2.39.2
> 

Re: [PATCH 34/65] drm/i915: pass dev_priv explicitly to SWF1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:52PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the SWF1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/i915_suspend.c | 18 ++++++++++++------
>  2 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b379ff60070..81f1b491d7af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2291,7 +2291,7 @@
>   * [30:32] all
>   */
>  #define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
> -#define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
> +#define SWF1(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
>  #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>  
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index ac8221ae97f3..8a71c1f52cb4 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -42,18 +42,21 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  		for (i = 0; i < 7; i++) {
>  			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
>  								      SWF0(dev_priv, i));
> -			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
> +								      SWF1(dev_priv, i));
>  		}
>  		for (i = 0; i < 3; i++)
>  			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
>  	} else if (GRAPHICS_VER(dev_priv) == 2) {
>  		for (i = 0; i < 7; i++)
> -			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
> +								      SWF1(dev_priv, i));
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
>  			dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv,
>  								      SWF0(dev_priv, i));
> -			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
> +			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
> +								      SWF1(dev_priv, i));
>  		}
>  		for (i = 0; i < 3; i++)
>  			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
> @@ -69,18 +72,21 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  		for (i = 0; i < 7; i++) {
>  			intel_de_write(dev_priv, SWF0(dev_priv, i),
>  				       dev_priv->regfile.saveSWF0[i]);
> -			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF1(dev_priv, i),
> +				       dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
>  			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
>  	} else if (GRAPHICS_VER(dev_priv) == 2) {
>  		for (i = 0; i < 7; i++)
> -			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF1(dev_priv, i),
> +				       dev_priv->regfile.saveSWF1[i]);
>  	} else if (HAS_GMCH(dev_priv)) {
>  		for (i = 0; i < 16; i++) {
>  			intel_de_write(dev_priv, SWF0(dev_priv, i),
>  				       dev_priv->regfile.saveSWF0[i]);
> -			intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
> +			intel_de_write(dev_priv, SWF1(dev_priv, i),
> +				       dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
>  			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
> -- 
> 2.39.2
> 

Re: [PATCH 35/65] drm/i915: pass dev_priv explicitly to SWF3

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:53PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the SWF3 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++----
>  2 files changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 81f1b491d7af..2f942882e7ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2292,7 +2292,7 @@
>   */
>  #define SWF0(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
>  #define SWF1(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
> -#define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
> +#define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>  
>  /* Pipe B */
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 8a71c1f52cb4..f8373a461f17 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -46,7 +46,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  								      SWF1(dev_priv, i));
>  		}
>  		for (i = 0; i < 3; i++)
> -			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
> +			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv,
> +								      SWF3(dev_priv, i));
>  	} else if (GRAPHICS_VER(dev_priv) == 2) {
>  		for (i = 0; i < 7; i++)
>  			dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv,
> @@ -59,7 +60,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
>  								      SWF1(dev_priv, i));
>  		}
>  		for (i = 0; i < 3; i++)
> -			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
> +			dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv,
> +								      SWF3(dev_priv, i));
>  	}
>  }
>  
> @@ -76,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  				       dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> -			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
> +			intel_de_write(dev_priv, SWF3(dev_priv, i),
> +				       dev_priv->regfile.saveSWF3[i]);
>  	} else if (GRAPHICS_VER(dev_priv) == 2) {
>  		for (i = 0; i < 7; i++)
>  			intel_de_write(dev_priv, SWF1(dev_priv, i),
> @@ -89,7 +92,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
>  				       dev_priv->regfile.saveSWF1[i]);
>  		}
>  		for (i = 0; i < 3; i++)
> -			intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
> +			intel_de_write(dev_priv, SWF3(dev_priv, i),
> +				       dev_priv->regfile.saveSWF3[i]);
>  	}
>  }
>  
> -- 
> 2.39.2
> 

Re: [PATCH 36/65] drm/i915: pass dev_priv explicitly to _PIPEBDSL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:54PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _PIPEBDSL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2f942882e7ed..0a2111b0cd98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2296,7 +2296,7 @@
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>  
>  /* Pipe B */
> -#define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
> +#define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)

should we simply remove this reg for now, or one of those cases that
are getting added as we speak?
anyone to Cc here then?

but up to you:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
>  #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
> -- 
> 2.39.2
> 

Re: [PATCH 37/65] drm/i915: pass dev_priv explicitly to _TRANSBCONF

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:55PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _TRANSBCONF register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a2111b0cd98..8dd4b5a72b22 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2297,7 +2297,7 @@
>  
>  /* Pipe B */
>  #define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
> -#define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> +#define _TRANSBCONF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)

ditto


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
> -- 
> 2.39.2
> 

Re: [PATCH 38/65] drm/i915: pass dev_priv explicitly to _PIPEBSTAT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:56PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _PIPEBSTAT register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8dd4b5a72b22..0bbe2f8aff4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2298,7 +2298,7 @@
>  /* Pipe B */
>  #define _PIPEBDSL(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
>  #define _TRANSBCONF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> -#define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
> +#define _PIPEBSTAT(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
>  #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
> -- 
> 2.39.2
> 

Re: [PATCH 39/65] drm/i915: pass dev_priv explicitly to _PIPEB_FRMCOUNT_G4X

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:57PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _PIPEB_FRMCOUNT_G4X register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0bbe2f8aff4b..f5367ec58400 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2301,7 +2301,7 @@
>  #define _PIPEBSTAT(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
> -#define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
> +#define _PIPEB_FRMCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
>  
>  
> -- 
> 2.39.2
> 

Re: [PATCH 40/65] drm/i915: pass dev_priv explicitly to _PIPEB_FLIPCOUNT_G4X

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:58PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _PIPEB_FLIPCOUNT_G4X register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5367ec58400..fb1dc6f5e903 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2302,7 +2302,7 @@
>  #define _PIPEBFRAMEHIGH		0x71040
>  #define _PIPEBFRAMEPIXEL	0x71044
>  #define _PIPEB_FRMCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
> -#define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
> +#define _PIPEB_FLIPCOUNT_G4X(dev_priv)	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)

G4X? and many cases... starting to have a feeling that those
are really not going to be used so soon and should be removed.

but, again, up to you:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  
>  
>  /* Display B control */
> -- 
> 2.39.2
> 

Re: [PATCH 41/65] drm/i915: pass dev_priv explicitly to _DSPBCNTR

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:59PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBCNTR register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb1dc6f5e903..8390294aea5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2306,7 +2306,7 @@
>  
>  
>  /* Display B control */
> -#define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
> +#define _DSPBCNTR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
>  #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
>  #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> -- 
> 2.39.2
> 

Re: [PATCH 42/65] drm/i915: pass dev_priv explicitly to _DSPBADDR

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:00PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBADDR register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8390294aea5b..bcaa7c5b0c40 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2309,7 +2309,7 @@
>  #define _DSPBCNTR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
>  #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
>  #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
> -#define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> +#define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>  #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>  #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
> -- 
> 2.39.2
> 

Re: [PATCH 43/65] drm/i915: pass dev_priv explicitly to _DSPBSTRIDE

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:01PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBSTRIDE register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcaa7c5b0c40..7fd2d5e07b48 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2310,7 +2310,7 @@
>  #define   DISP_ALPHA_TRANS_ENABLE	REG_BIT(15)
>  #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
>  #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> -#define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
> +#define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>  #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
> -- 
> 2.39.2
> 

Re: [PATCH 44/65] drm/i915: pass dev_priv explicitly to _DSPBPOS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:02PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBPOS register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7fd2d5e07b48..38c8b98d95c3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2311,7 +2311,7 @@
>  #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
>  #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
>  #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
> -#define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
> +#define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -- 
> 2.39.2
> 

Re: [PATCH 45/65] drm/i915: pass dev_priv explicitly to _DSPBSIZE

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:03PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBSIZE register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 38c8b98d95c3..36ed23b93475 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2312,7 +2312,7 @@
>  #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
>  #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>  #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
> -#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
> +#define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)

way too many unused cases...
we should probably remove them all in one patch and whoever is introducing them
later should already introduce with the dev_priv...

but again, up to you

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -- 
> 2.39.2
> 

Re: [PATCH 46/65] drm/i915: pass dev_priv explicitly to _DSPBSURF

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:04PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBSURF register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h     | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index bb904266c3cd..88ef8b7b9ab4 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1009,7 +1009,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
>  }
>  
>  #define DSPSURF_TO_PIPE(offset) \
> -	calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C))
> +	calc_index(offset, _DSPASURF, _DSPBSURF(dev_priv), 0, DSPSURF(dev_priv, PIPE_C))
>  
>  static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
>  		void *p_data, unsigned int bytes)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 36ed23b93475..9bb840895baa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2313,7 +2313,7 @@
>  #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>  #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>  #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
> -#define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
> +#define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>  #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
> -- 
> 2.39.2
> 

Re: [PATCH 48/65] drm/i915: pass dev_priv explicitly to _DSPBOFFSET

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:06PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBOFFSET register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c4251f62411..03c7b55e1bd3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2315,7 +2315,7 @@
>  #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>  #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>  #define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -#define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> +#define _DSPBOFFSET(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
>  
>  /* ICL DSI 0 and 1 */
> -- 
> 2.39.2
> 

Re: [PATCH 47/65] drm/i915: pass dev_priv explicitly to _DSPBTILEOFF

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:05PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBTILEOFF register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9bb840895baa..7c4251f62411 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2314,7 +2314,7 @@
>  #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>  #define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>  #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
> -#define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> +#define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>  #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
>  
> -- 
> 2.39.2
> 

Re: [PATCH 49/65] drm/i915: pass dev_priv explicitly to _DSPBSURFLIVE

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:07PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _DSPBSURFLIVE register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 03c7b55e1bd3..62cb456568e5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2316,7 +2316,7 @@
>  #define _DSPBSURF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>  #define _DSPBTILEOFF(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>  #define _DSPBOFFSET(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
> -#define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
> +#define _DSPBSURFLIVE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)

ditto

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  
>  /* ICL DSI 0 and 1 */
>  #define _PIPEDSI0CONF		0x7b008
> -- 
> 2.39.2
> 

Re: [PATCH 50/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_M1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:08PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_DATA_M1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  drivers/gpu/drm/i915/display/intel_fdi.c     | 6 +++---
>  drivers/gpu/drm/i915/gvt/display.c           | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  5 files changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 241121b0b3ff..7fd65e3b018d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2641,7 +2641,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  
>  	if (DISPLAY_VER(dev_priv) >= 5)
>  		intel_set_m_n(dev_priv, m_n,
> -			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
> +			      PIPE_DATA_M1(dev_priv, transcoder),
> +			      PIPE_DATA_N1(transcoder),
>  			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  	else
>  		intel_set_m_n(dev_priv, m_n,
> @@ -3337,7 +3338,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
>  
>  	if (DISPLAY_VER(dev_priv) >= 5)
>  		intel_get_m_n(dev_priv, m_n,
> -			      PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
> +			      PIPE_DATA_M1(dev_priv, transcoder),
> +			      PIPE_DATA_N1(transcoder),
>  			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  	else
>  		intel_get_m_n(dev_priv, m_n,
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 8b17b8ad71c3..007e0f9e9304 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -514,7 +514,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
>  	 * detection works.
>  	 */
>  	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
> -		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
>  
>  	/* FDI needs bits from pipe first */
>  	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
> @@ -616,7 +616,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
>  	 * detection works.
>  	 */
>  	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
> -		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
>  
>  	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
>  	   for train result */
> @@ -754,7 +754,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
>  	 * detection works.
>  	 */
>  	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
> -		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +		       intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK);
>  
>  	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
>  	   for train result */
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 3681dca165c6..ce6f20b1dabc 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -261,8 +261,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 *   DP link clk 1620 MHz and non-constant_n.
>  		 * TODO: calculate DP link symbol clk and stream clk m/n.
>  		 */
> -		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
> -		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
> +		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
> +		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
> @@ -395,8 +395,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 *   DP link clk 1620 MHz and non-constant_n.
>  		 * TODO: calculate DP link symbol clk and stream clk m/n.
>  		 */
> -		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
> -		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
> +		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
> +		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62cb456568e5..96bfa5620989 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2379,7 +2379,7 @@
>  #define _PIPEB_LINK_M2		0x61048
>  #define _PIPEB_LINK_N2		0x6104c
>  
> -#define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
> +#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
>  #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
>  #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
>  #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index ba3f734ced0b..977d695fbdff 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -266,7 +266,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
> +	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
> @@ -274,7 +274,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
> -	MMIO_D(PIPE_DATA_M1(TRANSCODER_B));
> +	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
> @@ -282,7 +282,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
> -	MMIO_D(PIPE_DATA_M1(TRANSCODER_C));
> +	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
> @@ -290,7 +290,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
> -	MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP));
> +	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 51/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_N1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:09PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_DATA_N1 register macro.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  4 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7fd65e3b018d..5eb4ad261c21 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2642,7 +2642,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  	if (DISPLAY_VER(dev_priv) >= 5)
>  		intel_set_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
> -			      PIPE_DATA_N1(transcoder),
> +			      PIPE_DATA_N1(dev_priv, transcoder),
>  			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  	else
>  		intel_set_m_n(dev_priv, m_n,
> @@ -3339,7 +3339,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
>  	if (DISPLAY_VER(dev_priv) >= 5)
>  		intel_get_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
> -			      PIPE_DATA_N1(transcoder),
> +			      PIPE_DATA_N1(dev_priv, transcoder),
>  			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
>  	else
>  		intel_get_m_n(dev_priv, m_n,
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index ce6f20b1dabc..5f3ee57b5982 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -263,7 +263,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 */
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
> -		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
> +		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
>  
> @@ -397,7 +397,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		 */
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
> -		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
> +		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 96bfa5620989..70c5fe687254 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2380,7 +2380,7 @@
>  #define _PIPEB_LINK_N2		0x6104c
>  
>  #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
> -#define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
> +#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
>  #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
>  #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
>  #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 977d695fbdff..b9ad4eec4740 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -267,7 +267,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
> +	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
> @@ -275,7 +275,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_DATA_N1(TRANSCODER_B));
> +	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
> @@ -283,7 +283,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_DATA_N1(TRANSCODER_C));
> +	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
> @@ -291,7 +291,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP));
> +	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 52/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_M2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:10PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_DATA_M2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  3 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5eb4ad261c21..c2a2061a467d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2660,7 +2660,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
>  		return;
>  
>  	intel_set_m_n(dev_priv, m_n,
> -		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
> +		      PIPE_DATA_M2(dev_priv, transcoder),
> +		      PIPE_DATA_N2(transcoder),
>  		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  }
>  
> @@ -3357,7 +3358,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  		return;
>  
>  	intel_get_m_n(dev_priv, m_n,
> -		      PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
> +		      PIPE_DATA_M2(dev_priv, transcoder),
> +		      PIPE_DATA_N2(transcoder),
>  		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 70c5fe687254..9c56df4c1f9f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2381,7 +2381,7 @@
>  
>  #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
>  #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
> -#define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
> +#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
>  #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
>  #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
>  #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index b9ad4eec4740..4199106f7202 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -268,7 +268,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
> +	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
> @@ -276,7 +276,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_DATA_M2(TRANSCODER_B));
> +	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
> @@ -284,7 +284,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_DATA_M2(TRANSCODER_C));
> +	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
> @@ -292,7 +292,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP));
> +	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 53/65] drm/i915: pass dev_priv explicitly to PIPE_DATA_N2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:11PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_DATA_N2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  3 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c2a2061a467d..7bf5b2559143 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2661,7 +2661,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
>  
>  	intel_set_m_n(dev_priv, m_n,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
> -		      PIPE_DATA_N2(transcoder),
> +		      PIPE_DATA_N2(dev_priv, transcoder),
>  		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  }
>  
> @@ -3359,7 +3359,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  
>  	intel_get_m_n(dev_priv, m_n,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
> -		      PIPE_DATA_N2(transcoder),
> +		      PIPE_DATA_N2(dev_priv, transcoder),
>  		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c56df4c1f9f..465d73ef43e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2382,7 +2382,7 @@
>  #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
>  #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
>  #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
> -#define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
> +#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
>  #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
>  #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
>  #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 4199106f7202..829196c665c6 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -269,7 +269,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_DATA_N2(TRANSCODER_A));
> +	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
> @@ -277,7 +277,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_DATA_N2(TRANSCODER_B));
> +	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
> @@ -285,7 +285,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_DATA_N2(TRANSCODER_C));
> +	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
> @@ -293,7 +293,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP));
> +	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 54/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_M1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:12PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_LINK_M1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
>  drivers/gpu/drm/i915/gvt/handlers.c          | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  5 files changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7bf5b2559143..a3249d782a8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2643,7 +2643,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  		intel_set_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
>  			      PIPE_DATA_N1(dev_priv, transcoder),
> -			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
> +			      PIPE_LINK_M1(dev_priv, transcoder),
> +			      PIPE_LINK_N1(transcoder));
>  	else
>  		intel_set_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> @@ -3341,7 +3342,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
>  		intel_get_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
>  			      PIPE_DATA_N1(dev_priv, transcoder),
> -			      PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
> +			      PIPE_LINK_M1(dev_priv, transcoder),
> +			      PIPE_LINK_N1(transcoder));
>  	else
>  		intel_get_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 5f3ee57b5982..eea956603cc8 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
> -		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
> +		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
>  
>  		/* Enable per-DDI/PORT vreg */
> @@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64);
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
> -		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
> +		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 88ef8b7b9ab4..ae5a3e2a5c50 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -673,7 +673,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
>  		dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
>  
>  	/* Get DP link symbol clock M/N */
> -	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A));
> +	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
>  	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
>  
>  	/* Get H/V total from transcoder timing */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 465d73ef43e2..a9f3c4a85318 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2383,7 +2383,7 @@
>  #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
>  #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
>  #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
> -#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
> +#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
>  #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
>  #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
>  #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 829196c665c6..c08b8e755377 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -270,7 +270,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_LINK_M1(TRANSCODER_A));
> +	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
> @@ -278,7 +278,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_LINK_M1(TRANSCODER_B));
> +	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
> @@ -286,7 +286,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_LINK_M1(TRANSCODER_C));
> +	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
> @@ -294,7 +294,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP));
> +	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
> -- 
> 2.39.2
> 

Re: [PATCH 55/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_N1

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:13PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_LINK_N1 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/gvt/display.c           | 4 ++--
>  drivers/gpu/drm/i915/gvt/handlers.c          | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  5 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a3249d782a8b..eef317984564 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2644,7 +2644,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
>  			      PIPE_DATA_N1(dev_priv, transcoder),
>  			      PIPE_LINK_M1(dev_priv, transcoder),
> -			      PIPE_LINK_N1(transcoder));
> +			      PIPE_LINK_N1(dev_priv, transcoder));
>  	else
>  		intel_set_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> @@ -3343,7 +3343,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
>  			      PIPE_DATA_M1(dev_priv, transcoder),
>  			      PIPE_DATA_N1(dev_priv, transcoder),
>  			      PIPE_LINK_M1(dev_priv, transcoder),
> -			      PIPE_LINK_N1(transcoder));
> +			      PIPE_LINK_N1(dev_priv, transcoder));
>  	else
>  		intel_get_m_n(dev_priv, m_n,
>  			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index eea956603cc8..95b4b76d3b45 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -265,7 +265,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
> -		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
> +		vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
>  
>  		/* Enable per-DDI/PORT vreg */
>  		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
> @@ -399,7 +399,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e;
>  		vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000;
>  		vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e;
> -		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
> +		vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000;
>  	}
>  
>  	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index ae5a3e2a5c50..f2af234769bf 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -674,7 +674,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
>  
>  	/* Get DP link symbol clock M/N */
>  	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
> -	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
> +	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
>  
>  	/* Get H/V total from transcoder timing */
>  	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a9f3c4a85318..ac9ef4bd176e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2384,7 +2384,7 @@
>  #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
>  #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
>  #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
> -#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
> +#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
>  #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
>  #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
>  
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index c08b8e755377..00ce7147a9b6 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -271,7 +271,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_LINK_N1(TRANSCODER_A));
> +	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
> @@ -279,7 +279,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_LINK_N1(TRANSCODER_B));
> +	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
> @@ -287,7 +287,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_LINK_N1(TRANSCODER_C));
> +	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
> @@ -295,7 +295,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP));
> +	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
>  	MMIO_D(PF_CTL(PIPE_A));
> -- 
> 2.39.2
> 

Re: [PATCH 59/65] drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:17PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_DDI_FUNC_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        | 12 +++++---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 29 ++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_display.c  |  9 ++++--
>  .../gpu/drm/i915/display/intel_display_irq.c  |  3 +-
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  5 ++--
>  drivers/gpu/drm/i915/display/intel_fdi.c      |  3 +-
>  drivers/gpu/drm/i915/display/intel_hdcp.c     |  3 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  2 +-
>  drivers/gpu/drm/i915/gvt/display.c            | 25 +++++++++-------
>  drivers/gpu/drm/i915/gvt/handlers.c           |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +-
>  11 files changed, 58 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9beb94494b2b..acc80d439352 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -796,7 +796,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  		dsi_trans = dsi_port_to_transcoder(port);
>  
>  		/* select data lane width */
> -		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
>  		tmp &= ~DDI_PORT_WIDTH_MASK;
>  		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
>  
> @@ -822,7 +823,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  
>  		/* enable DDI buffer */
>  		tmp |= TRANS_DDI_FUNC_ENABLE;
> -		intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
> +		intel_de_write(dev_priv,
> +			       TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
>  	}
>  
>  	/* wait for link ready */
> @@ -1333,7 +1335,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  	/* disable ddi function */
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);
> -		intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans),
> +		intel_de_rmw(dev_priv,
> +			     TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
>  			     TRANS_DDI_FUNC_ENABLE, 0);
>  	}
>  
> @@ -1697,7 +1700,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		dsi_trans = dsi_port_to_transcoder(port);
> -		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
>  		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
>  		case TRANS_DDI_EDP_INPUT_A_ON:
>  			*pipe = PIPE_A;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3c3fc53376ce..c5571be3c66e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -606,7 +606,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
>  			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
>  	}
>  
> -	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
> +	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
>  		       intel_ddi_transcoder_func_reg_val_get(encoder,
>  							     crtc_state));
>  }
> @@ -626,7 +626,8 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
>  
>  	ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
>  	ctl &= ~TRANS_DDI_FUNC_ENABLE;
> -	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
> +	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
> +		       ctl);
>  }
>  
>  void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
> @@ -641,7 +642,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  		intel_de_write(dev_priv,
>  			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
>  
> -	ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +	ctl = intel_de_read(dev_priv,
> +			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  
>  	drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
>  
> @@ -660,7 +662,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  		ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
>  	}
>  
> -	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
> +	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
> +		       ctl);
>  
>  	if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> @@ -684,7 +687,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
>  	if (drm_WARN_ON(dev, !wakeref))
>  		return -ENXIO;
>  
> -	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
> +	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
>  		     hdcp_mask, enable ? hdcp_mask : 0);
>  	intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
>  	return ret;
> @@ -718,7 +721,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
>  	else
>  		cpu_transcoder = (enum transcoder) pipe;
>  
> -	tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +	tmp = intel_de_read(dev_priv,
> +			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  
>  	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
>  	case TRANS_DDI_MODE_SELECT_HDMI:
> @@ -782,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  
>  	if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
>  		tmp = intel_de_read(dev_priv,
> -				    TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> +				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP));
>  
>  		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
>  		default:
> @@ -823,7 +827,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
>  		}
>  
>  		tmp = intel_de_read(dev_priv,
> -				    TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +				    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  		intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
>  					trans_wakeref);
>  
> @@ -3025,7 +3029,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
>  		if (is_mst) {
>  			enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>  
> -			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
> +			intel_de_rmw(dev_priv,
> +				     TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
>  				     TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
>  				     0);
>  		}
> @@ -3759,7 +3764,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de
>  
>  		master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
>  	} else {
> -		u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +		u32 ctl = intel_de_read(dev_priv,
> +				        TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  
>  		if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
>  			return INVALID_TRANSCODER;
> @@ -3815,7 +3821,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	u32 temp, flags = 0;
>  
> -	temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +	temp = intel_de_read(dev_priv,
> +			     TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  	if (temp & TRANS_DDI_PHSYNC)
>  		flags |= DRM_MODE_FLAG_PHSYNC;
>  	else
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 952780028630..62f8300c73a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3507,7 +3507,8 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
>  	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  
>  	with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
> -		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  
>  	return tmp & TRANS_DDI_FUNC_ENABLE;
>  }
> @@ -3622,7 +3623,8 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
>  
>  		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
>  		with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
> -			tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> +			tmp = intel_de_read(dev_priv,
> +					    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
>  
>  		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
>  			continue;
> @@ -3729,7 +3731,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
>  		return false;
>  
>  	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
> -		tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> +		tmp = intel_de_read(dev_priv,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));
>  
>  		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
>  			pipe_config->pch_pfit.force_thru = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 76bba95410e7..036f77c2702d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -934,7 +934,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/* Get PIPE for handling VBLANK event */
> -	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans));
> +	val = intel_uncore_read(&dev_priv->uncore,
> +				TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
>  	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
>  	case TRANS_DDI_EDP_INPUT_A_ON:
>  		pipe = PIPE_A;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 715d2f59f565..00fdcbc28e9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1009,7 +1009,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>  
>  	clear_act_sent(encoder, old_crtc_state);
>  
> -	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
> +	intel_de_rmw(dev_priv,
> +		     TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),
>  		     TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
>  
>  	wait_for_act_sent(encoder, old_crtc_state);
> @@ -1230,7 +1231,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>  
>  	clear_act_sent(encoder, pipe_config);
>  
> -	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
> +	intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0,
>  		     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>  
>  	drm_dbg_kms(&dev_priv->drm, "active links %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 007e0f9e9304..d33befd7994d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -34,7 +34,8 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  		 * so pipe->transcoder cast is fine here.
>  		 */
>  		enum transcoder cpu_transcoder = (enum transcoder)pipe;
> -		cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
> +		cur_state = intel_de_read(dev_priv,
> +					  TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
>  	} else {
>  		cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index ba3eca919900..3ebe035f382e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -47,7 +47,8 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
>  				     0, HDCP_LINE_REKEY_DISABLE);
>  		else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
>  			 IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
> -			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder),
> +			intel_de_rmw(dev_priv,
> +				     TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder),
>  				     0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 7704ead5002d..19498ee455fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -83,7 +83,7 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
>  				     enum transcoder cpu_transcoder)
>  {
>  	drm_WARN(&dev_priv->drm,
> -		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
> +		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) &
>  		 TRANS_DDI_FUNC_ENABLE,
>  		 "HDMI transcoder function enabled, expecting disabled\n");
>  }
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 95b4b76d3b45..c66d6d3177c8 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -200,11 +200,11 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		}
>  
>  		for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
> -			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
> +			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &=
>  				~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
>  				  TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
>  		}
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
>  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
>  			  TRANS_DDI_PORT_MASK);
>  
> @@ -287,7 +287,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  				(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
>  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
>  				~DDI_BUF_IS_IDLE;
> -			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
> +			vgpu_vreg_t(vgpu,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |=
>  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  				 TRANS_DDI_FUNC_ENABLE);
>  			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
> @@ -316,7 +317,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  				DDI_BUF_CTL_ENABLE;
>  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
>  				~DDI_BUF_IS_IDLE;
> -			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
> +			vgpu_vreg_t(vgpu,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
>  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
>  				 TRANS_DDI_FUNC_ENABLE);
> @@ -346,7 +348,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  				DDI_BUF_CTL_ENABLE;
>  			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
>  				~DDI_BUF_IS_IDLE;
> -			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
> +			vgpu_vreg_t(vgpu,
> +				    TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
>  				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
>  				 TRANS_DDI_FUNC_ENABLE);
> @@ -410,10 +413,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
>  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
>  		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
>  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
>  			TRANS_DDI_PORT_MASK);
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
>  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  			(PORT_B << TRANS_DDI_PORT_SHIFT) |
>  			TRANS_DDI_FUNC_ENABLE);
> @@ -436,10 +439,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
>  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
>  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
>  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
>  			TRANS_DDI_PORT_MASK);
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
>  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  			(PORT_C << TRANS_DDI_PORT_SHIFT) |
>  			TRANS_DDI_FUNC_ENABLE);
> @@ -462,10 +465,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>  		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
>  			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
>  		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &=
>  			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
>  			TRANS_DDI_PORT_MASK);
> -		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
> +		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |=
>  			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
>  			(PORT_D << TRANS_DDI_PORT_SHIFT) |
>  			TRANS_DDI_FUNC_ENABLE);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index f2af234769bf..24abe70afe46 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -657,7 +657,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
>  	u32 dp_br, link_m, link_n, htotal, vtotal;
>  
>  	/* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
> -	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &
> +	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &
>  		TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>  	if (port != PORT_B && port != PORT_D) {
>  		gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c8488877dd68..14f4060dd573 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3953,7 +3953,7 @@ enum skl_power_gate {
>  #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
>  #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
>  #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
> -#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
> +#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
>  
>  #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
>  /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> -- 
> 2.39.2
> 

Re: [PATCH 61/65] drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:19PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TGL_DP_TP_CTL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 515996c49f5a..135c2e7964fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2184,7 +2184,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
>  	if (DISPLAY_VER(dev_priv) >= 12)
> -		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
> +		return TGL_DP_TP_CTL(dev_priv,
> +				     tgl_dp_tp_transcoder(crtc_state));
>  	else
>  		return DP_TP_CTL(encoder->port);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f330953e71cf..c1547ecdc352 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4022,7 +4022,7 @@ enum skl_power_gate {
>  #define _DP_TP_CTL_B			0x64140
>  #define _TGL_DP_TP_CTL_A		0x60540
>  #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> -#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
> +#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
>  #define  DP_TP_CTL_ENABLE			(1 << 31)
>  #define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
>  #define  DP_TP_CTL_MODE_SST			(0 << 27)
> -- 
> 2.39.2
> 

Re: [PATCH 57/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_N2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:15PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_LINK_N2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  3 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9df8e486a86e..952780028630 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2664,7 +2664,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
>  		      PIPE_DATA_N2(dev_priv, transcoder),
>  		      PIPE_LINK_M2(dev_priv, transcoder),
> -		      PIPE_LINK_N2(transcoder));
> +		      PIPE_LINK_N2(dev_priv, transcoder));
>  }
>  
>  static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> @@ -3364,7 +3364,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
>  		      PIPE_DATA_N2(dev_priv, transcoder),
>  		      PIPE_LINK_M2(dev_priv, transcoder),
> -		      PIPE_LINK_N2(transcoder));
> +		      PIPE_LINK_N2(dev_priv, transcoder));
>  }
>  
>  static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2a73ad779e26..70e549b38984 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2386,7 +2386,7 @@
>  #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
>  #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
>  #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
> -#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
> +#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
>  
>  /* CPU panel fitter */
>  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index d1a51ae042f1..955c9a33212a 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -273,7 +273,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
> +	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B));
> @@ -281,7 +281,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
> +	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C));
> @@ -289,7 +289,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
> +	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP));
> @@ -297,7 +297,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
> +	MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PF_CTL(PIPE_A));
>  	MMIO_D(PF_WIN_SZ(PIPE_A));
>  	MMIO_D(PF_WIN_POS(PIPE_A));
> -- 
> 2.39.2
> 

Re: [PATCH 56/65] drm/i915: pass dev_priv explicitly to PIPE_LINK_M2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:14PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_LINK_M2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c  | 8 ++++----
>  3 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index eef317984564..9df8e486a86e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2663,7 +2663,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
>  	intel_set_m_n(dev_priv, m_n,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
>  		      PIPE_DATA_N2(dev_priv, transcoder),
> -		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
> +		      PIPE_LINK_M2(dev_priv, transcoder),
> +		      PIPE_LINK_N2(transcoder));
>  }
>  
>  static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> @@ -3362,7 +3363,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  	intel_get_m_n(dev_priv, m_n,
>  		      PIPE_DATA_M2(dev_priv, transcoder),
>  		      PIPE_DATA_N2(dev_priv, transcoder),
> -		      PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
> +		      PIPE_LINK_M2(dev_priv, transcoder),
> +		      PIPE_LINK_N2(transcoder));
>  }
>  
>  static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac9ef4bd176e..2a73ad779e26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2385,7 +2385,7 @@
>  #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
>  #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
>  #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
> -#define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
> +#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
>  #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
>  
>  /* CPU panel fitter */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 00ce7147a9b6..d1a51ae042f1 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -272,7 +272,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A));
> -	MMIO_D(PIPE_LINK_M2(TRANSCODER_A));
> +	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_A));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B));
> @@ -280,7 +280,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B));
> -	MMIO_D(PIPE_LINK_M2(TRANSCODER_B));
> +	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_B));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C));
> @@ -288,7 +288,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C));
> -	MMIO_D(PIPE_LINK_M2(TRANSCODER_C));
> +	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_C));
>  	MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP));
> @@ -296,7 +296,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP));
> +	MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP));
>  	MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP));
>  	MMIO_D(PF_CTL(PIPE_A));
>  	MMIO_D(PF_WIN_SZ(PIPE_A));
> -- 
> 2.39.2
> 

Re: [PATCH 62/65] drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:20PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TGL_DP_TP_STATUS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 135c2e7964fc..368cd1312d8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2196,7 +2196,8 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
>  	if (DISPLAY_VER(dev_priv) >= 12)
> -		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
> +		return TGL_DP_TP_STATUS(dev_priv,
> +				        tgl_dp_tp_transcoder(crtc_state));
>  	else
>  		return DP_TP_STATUS(encoder->port);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1547ecdc352..3de6e4f54bc0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4048,7 +4048,7 @@ enum skl_power_gate {
>  #define _DP_TP_STATUS_B			0x64144
>  #define _TGL_DP_TP_STATUS_A		0x60544
>  #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
> -#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
> +#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
>  #define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
>  #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
>  #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
> -- 
> 2.39.2
> 

Re: [PATCH 63/65] drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:21PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_MSA_MISC register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 368cd1312d8a..327f748d3774 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -440,7 +440,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
>  	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
>  		temp |= DP_MSA_MISC_COLOR_VSC_SDP;
>  
> -	intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
> +	intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder),
> +		       temp);
>  }
>  
>  static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3de6e4f54bc0..3fcebccb9f3c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4229,7 +4229,7 @@ enum skl_power_gate {
>  #define _TRANSB_MSA_MISC		0x61410
>  #define _TRANSC_MSA_MISC		0x62410
>  #define _TRANS_EDP_MSA_MISC		0x6f410
> -#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
> +#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
>  /* See DP_MSA_MISC_* for the bit definitions */
>  
>  #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
> -- 
> 2.39.2
> 

Re: [PATCH 58/65] drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:16PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the HSW_STEREO_3D_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 70e549b38984..c8488877dd68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3493,7 +3493,7 @@
>  #define   S3D_ENABLE			(1 << 31)
>  #define _HSW_STEREO_3D_CTL_B		0x71020
>  
> -#define HSW_STEREO_3D_CTL(trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
> +#define HSW_STEREO_3D_CTL(dev_priv, trans)	_MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)

oh! this I'm pretty sure it is really old and will never get used.

Let's remove?! :$

but up to you:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  
>  #define _PCH_TRANS_HTOTAL_B          0xe1000
>  #define _PCH_TRANS_HBLANK_B          0xe1004
> -- 
> 2.39.2
> 

Re: [PATCH 60/65] drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:18PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_DDI_FUNC_CTL2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c           | 6 ++++--
>  drivers/gpu/drm/i915/display/intel_ddi.c         | 9 ++++++---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 +-
>  4 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index acc80d439352..ae8f6617aa70 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -784,7 +784,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  	if (intel_dsi->dual_link) {
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
> +			intel_de_rmw(dev_priv,
> +				     TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
>  				     0, PORT_SYNC_MODE_ENABLE);
>  		}
>  
> @@ -1344,7 +1345,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>  	if (intel_dsi->dual_link) {
>  		for_each_dsi_port(port, intel_dsi->ports) {
>  			dsi_trans = dsi_port_to_transcoder(port);
> -			intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
> +			intel_de_rmw(dev_priv,
> +				     TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
>  				     PORT_SYNC_MODE_ENABLE, 0);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c5571be3c66e..515996c49f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -603,7 +603,8 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
>  		}
>  
>  		intel_de_write(dev_priv,
> -			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
> +			       TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
> +			       ctl2);
>  	}
>  
>  	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder),
> @@ -640,7 +641,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
>  
>  	if (DISPLAY_VER(dev_priv) >= 11)
>  		intel_de_write(dev_priv,
> -			       TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
> +			       TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder),
> +			       0);
>  
>  	ctl = intel_de_read(dev_priv,
>  			    TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder));
> @@ -3757,7 +3759,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de
>  	u32 master_select;
>  
>  	if (DISPLAY_VER(dev_priv) >= 11) {
> -		u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
> +		u32 ctl2 = intel_de_read(dev_priv,
> +				         TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder));
>  
>  		if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
>  			return INVALID_TRANSCODER;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 036f77c2702d..bf55c9064b76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -913,7 +913,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
>  	 * Incase of dual link, TE comes from DSI_1
>  	 * this is to check if dual link is enabled
>  	 */
> -	val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> +	val = intel_uncore_read(&dev_priv->uncore,
> +				TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0));
>  	val &= PORT_SYNC_MODE_ENABLE;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 14f4060dd573..f330953e71cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4009,7 +4009,7 @@ enum skl_power_gate {
>  #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
>  #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
>  #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
> -#define TRANS_DDI_FUNC_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
> +#define TRANS_DDI_FUNC_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
>  #define  PORT_SYNC_MODE_ENABLE			REG_BIT(4)
>  #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
>  #define  PORT_SYNC_MODE_MASTER_SELECT(x)	REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
> -- 
> 2.39.2
> 

Re: [PATCH 64/65] drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:22PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_SET_CONTEXT_LATENCY register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  drivers/gpu/drm/i915/i915_reg.h              | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 62f8300c73a5..c608329dac42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2703,7 +2703,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
>  	 */
>  	if (DISPLAY_VER(dev_priv) >= 13) {
> -		intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
> +		intel_de_write(dev_priv,
> +			       TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder),
>  			       crtc_vblank_start - crtc_vdisplay);
>  
>  		/*
> @@ -2860,7 +2861,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>  	if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
>  		adjusted_mode->crtc_vblank_start =
>  			adjusted_mode->crtc_vdisplay +
> -			intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
> +			intel_de_read(dev_priv,
> +				      TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder));
>  }
>  
>  static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3fcebccb9f3c..8a1414ae72cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4236,7 +4236,7 @@ enum skl_power_gate {
>  #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
>  #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
>  #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
> -#define TRANS_SET_CONTEXT_LATENCY(tran)		_MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
> +#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
>  #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
>  #define  TRANS_SET_CONTEXT_LATENCY_VALUE(x)	REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
>  
> -- 
> 2.39.2
> 

Re: [PATCH 65/65] drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:26:23PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the MTL_CLKGATE_DIS_TRANS register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I hope I didn't missed anything.

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4a4124a92a0d..21f6a4fa86a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1716,7 +1716,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  		if (!intel_dp->psr.panel_replay_enabled &&
>  		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
>  			intel_de_rmw(dev_priv,
> -				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> +				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
> +				     0,
>  				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>  		else if (IS_ALDERLAKE_P(dev_priv))
>  			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
> @@ -1897,7 +1898,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  		if (!intel_dp->psr.panel_replay_enabled &&
>  		    IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
>  			intel_de_rmw(dev_priv,
> -				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> +				     MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder),
>  				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
>  		else if (IS_ALDERLAKE_P(dev_priv))
>  			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8a1414ae72cb..7049a5ccefd9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4718,7 +4718,7 @@ enum skl_power_gate {
>  
>  #define _MTL_CLKGATE_DIS_TRANS_A			0x604E8
>  #define _MTL_CLKGATE_DIS_TRANS_B			0x614E8
> -#define MTL_CLKGATE_DIS_TRANS(trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
> +#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
>  #define  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS		REG_BIT(7)
>  
>  #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> -- 
> 2.39.2
> 

Re: [PATCH 45/65] drm/i915: pass dev_priv explicitly to _DSPBSIZE

[Jani Nikula]

On Thu, 06 Jun 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Jun 04, 2024 at 06:26:03PM +0300, Jani Nikula wrote:
>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>> explicitly to the _DSPBSIZE register macro.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 38c8b98d95c3..36ed23b93475 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2312,7 +2312,7 @@
>>  #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
>>  #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>>  #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>> -#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>> +#define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>
> way too many unused cases...
> we should probably remove them all in one patch and whoever is introducing them
> later should already introduce with the dev_priv...
>
> but again, up to you
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Dropped the changes touching unused macros, and pushed everything else
to din. I've got a separate series cleaning up gvt a bit and removing
the unused ones.

Thanks for the review!

BR,
Jani.


>
>
>>  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>>  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>>  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 45/65] drm/i915: pass dev_priv explicitly to _DSPBSIZE

[Jani Nikula]

On Fri, 07 Jun 2024, Jani Nikula <jani.nikula@intel.com> wrote:
> On Thu, 06 Jun 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>> On Tue, Jun 04, 2024 at 06:26:03PM +0300, Jani Nikula wrote:
>>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>>> explicitly to the _DSPBSIZE register macro.
>>> 
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 38c8b98d95c3..36ed23b93475 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -2312,7 +2312,7 @@
>>>  #define _DSPBADDR(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
>>>  #define _DSPBSTRIDE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
>>>  #define _DSPBPOS(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
>>> -#define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>>> +#define _DSPBSIZE(dev_priv)		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
>>
>> way too many unused cases...
>> we should probably remove them all in one patch and whoever is introducing them
>> later should already introduce with the dev_priv...
>>
>> but again, up to you
>>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Dropped the changes touching unused macros, and pushed everything else
> to din. I've got a separate series cleaning up gvt a bit and removing
> the unused ones.

PS. Fixed a couple of whitespace issues while pushing.

>
> Thanks for the review!
>
> BR,
> Jani.
>
>
>>
>>
>>>  #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
>>>  #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>>>  #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
>>> -- 
>>> 2.39.2
>>> 

-- 
Jani Nikula, Intel