From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
"Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>
Subject: Re: [PATCH v6 1/2] drm/i915/display: Plane capability for 64k phys alignment
Date: Tue, 27 Aug 2024 12:26:46 -0400 [thread overview]
Message-ID: <Zs3-RrVfnDA6XSRY@intel.com> (raw)
In-Reply-To: <20240826170117.327709-2-maarten.lankhorst@linux.intel.com>
On Mon, Aug 26, 2024 at 07:01:15PM +0200, Maarten Lankhorst wrote:
> Some plane formats have been designed to require 64k physical alignment.
> By returning whether this is the case for certain formats, we do not
> need to hardcode this check inside Xe.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
I still believe that 'CAPS' 'needs64k' is strange. But this is indeed
the cleanest way we found and easy to port to future platforms.
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
to get this merged through drm-xe-next as well where this is
needed right now.
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 20 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index d2716915d046d..5be7bb43e2e0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -169,7 +169,7 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> }, {
> .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
> .display_ver = { 14, -1 },
> - .plane_caps = INTEL_PLANE_CAP_TILING_4,
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
> }, {
> .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
> .display_ver = { 14, 14 },
> @@ -420,6 +420,24 @@ bool intel_fb_is_mc_ccs_modifier(u64 modifier)
> INTEL_PLANE_CAP_CCS_MC);
> }
>
> +/**
> + * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
> + * @modifier: Modifier to check
> + *
> + * Returns:
> + * Returns %true if @modifier requires 64k aligned physical pages.
> + */
> +bool intel_fb_needs_64k_phys(u64 modifier)
> +{
> + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
> +
> + if (!md)
> + return false;
> +
> + return plane_caps_contain_any(md->plane_caps,
> + INTEL_PLANE_CAP_NEED64K_PHYS);
> +}
> +
> static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
> u8 display_ver_from, u8 display_ver_until)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> index 6dee0c8b7f226..10de437e8ef84 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -28,11 +28,13 @@ struct intel_plane_state;
> #define INTEL_PLANE_CAP_TILING_Y BIT(4)
> #define INTEL_PLANE_CAP_TILING_Yf BIT(5)
> #define INTEL_PLANE_CAP_TILING_4 BIT(6)
> +#define INTEL_PLANE_CAP_NEED64K_PHYS BIT(7)
>
> bool intel_fb_is_tiled_modifier(u64 modifier);
> bool intel_fb_is_ccs_modifier(u64 modifier);
> bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
> bool intel_fb_is_mc_ccs_modifier(u64 modifier);
> +bool intel_fb_needs_64k_phys(u64 modifier);
>
> bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
> int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
> --
> 2.45.2
>
next prev parent reply other threads:[~2024-08-27 16:26 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-26 17:01 [PATCH v6 0/2] drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed Maarten Lankhorst
2024-08-26 17:01 ` [PATCH v6 1/2] drm/i915/display: Plane capability for 64k phys alignment Maarten Lankhorst
2024-08-27 16:26 ` Rodrigo Vivi [this message]
2024-08-27 18:59 ` Rodrigo Vivi
2024-08-26 17:01 ` [PATCH v6 2/2] drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed Maarten Lankhorst
2024-08-26 19:30 ` Matthew Brost
2024-08-26 19:42 ` Maarten Lankhorst
2024-08-27 3:11 ` Matthew Brost
2024-08-27 6:43 ` Maarten Lankhorst
2024-08-27 16:00 ` Matthew Brost
2024-08-27 16:23 ` Rodrigo Vivi
2024-08-26 19:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed. (rev2) Patchwork
2024-08-26 19:39 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-08-26 19:46 ` ✓ Fi.CI.BAT: success " Patchwork
2024-08-27 15:29 ` ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Zs3-RrVfnDA6XSRY@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=zbigniew.kempczynski@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).