From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF5A4EE57D4 for ; Wed, 11 Sep 2024 20:33:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 056A910EA9B; Wed, 11 Sep 2024 20:33:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PRh1WG5z"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 43B3C10EA9B for ; Wed, 11 Sep 2024 20:33:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726086786; x=1757622786; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=ET2x97FeOClRFI/WaoUwjtv3jbLHuTr/kTLRJ8+/q2c=; b=PRh1WG5zruB9j6NxKTVlD2Q1Lo0YmT6UBqocyzXLSl7fNVl90zUOZi5q Zdp9onALHK5PeqUh13nwPwSOHfMstM9a5YXjLjisVM302/2rXWyp2UoEc PsLEfIfK9B/DQ/y3694UR6ptTHMxlG4vktCwV1ImsFFUwplZpW7hN/D0a 5KTskOc34Bkx9k5vUGafiDzOdrmK7erPHrAb9eoijtuWqLovGKETf+7UT darsQ50lGOkRh8MyLEa1K0ppUVTbsOAK8smTXV8G/GjeIkO1zjwgIPVau axnUXUJM3hkX5jC85MjuI8jApF2SEMb73+tAPT5EVD3/LvkHrW8qFQRvz w==; X-CSE-ConnectionGUID: uhX447aMQ4W8GokpJnMQxg== X-CSE-MsgGUID: WAmu+mKKTQ2v85y8VDhVEA== X-IronPort-AV: E=McAfee;i="6700,10204,11192"; a="36263647" X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="36263647" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 13:33:06 -0700 X-CSE-ConnectionGUID: pgP2KeG4SU2Vd7IB+dJrug== X-CSE-MsgGUID: ChLzXvubTc+jeoaIJVNQ5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,221,1719903600"; d="scan'208";a="67543775" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Sep 2024 13:33:02 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 11 Sep 2024 23:33:01 +0300 Date: Wed, 11 Sep 2024 23:33:01 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, suraj.kandpal@intel.com, jani.saarinen@intel.com Subject: Re: [PATCH 13/19] drm/i915: Implement hw state readout and checks for ultrajoiner Message-ID: References: <20240911131349.933814-1-ankit.k.nautiyal@intel.com> <20240911131349.933814-14-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240911131349.933814-14-ankit.k.nautiyal@intel.com> X-Patchwork-Hint: comment X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Sep 11, 2024 at 06:43:43PM +0530, Ankit Nautiyal wrote: > From: Stanislav Lisovskiy > > Ultrajoiner mode has some new bits and states to be > read out from the hw. Lets make changes accordingly. > > v2: Fix checkpatch warnings. (Ankit) > v3: Add separate functions for computing expected secondary_big/ultrajoiner > pipes. (Ankit) > v4: Streamline the helpers for ultrajoiner. (Ville) > -Add fixup to accommodate PIPED check for ultrajoiner. (Ville) > -Add more Ultrajoiner drm_WARNs. (Ville) > > Signed-off-by: Stanislav Lisovskiy > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_display.c | 91 ++++++++++++++++++- > .../gpu/drm/i915/display/intel_vdsc_regs.h | 3 + > 2 files changed, 89 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index b66685a9843f..02926a8ef7c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3662,13 +3662,68 @@ static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes) > return expected_secondary_pipes(bigjoiner_primary_pipes, 2); > } > > +static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes) > +{ > + return expected_secondary_pipes(ultrajoiner_primary_pipes, 4); > +} > + > +static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, > + u8 ultrajoiner_secondary_pipes) > +{ > + return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; > +} > + > +static > +bool intel_display_can_use_ultrajoiner(struct intel_display *display) > +{ > + struct drm_i915_private *i915 = to_i915(display->drm); > + > + return ((DISPLAY_VER(display) == 14 && IS_DGFX(i915)) || > + DISPLAY_VER(display) > 14); > +} > + > +static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, > + u8 *primary_pipes, u8 *secondary_pipes) > +{ > + struct intel_display *display = to_intel_display(&i915->drm); > + struct intel_crtc *crtc; > + > + *primary_pipes = 0; > + *secondary_pipes = 0; > + > + if (!intel_display_can_use_ultrajoiner(display)) > + return; > + > + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, > + joiner_pipes(i915)) { > + enum intel_display_power_domain power_domain; > + enum pipe pipe = crtc->pipe; > + intel_wakeref_t wakeref; > + > + power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); > + with_intel_display_power_if_enabled(i915, power_domain, wakeref) { > + u32 tmp = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); > + > + if (!(tmp & ULTRA_JOINER_ENABLE)) > + continue; > + > + if (tmp & PRIMARY_ULTRA_JOINER_ENABLE) > + *primary_pipes |= BIT(pipe); > + else > + *secondary_pipes |= BIT(pipe); > + } > + } > +} > + > static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, > u8 *primary_pipes, u8 *secondary_pipes) > { > struct intel_display *display = to_intel_display(&dev_priv->drm); > u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; > + u8 primary_ultrajoiner_pipes; > u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes; > - u8 uncompressed_joiner_pipes, bigjoiner_pipes; > + u8 secondary_ultrajoiner_pipes; > + u8 uncompressed_joiner_pipes, bigjoiner_pipes, ultrajoiner_pipes; > > if (!intel_display_can_use_joiner(display)) > return; > @@ -3685,13 +3740,33 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, > drm_WARN_ON(display->drm, > (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0); > > + enabled_ultrajoiner_pipes(dev_priv, &primary_ultrajoiner_pipes, > + &secondary_ultrajoiner_pipes); > + /* > + * For some strange reason the last pipe in the set of four > + * shouldn't have ultrajoiner enable bit set in hardware. > + * Set the bit anyway to make life easier. > + */ > + drm_WARN_ON(&dev_priv->drm, > + expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != > + secondary_ultrajoiner_pipes); > + secondary_ultrajoiner_pipes = > + fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, > + secondary_ultrajoiner_pipes); Did we find out if the spec is right or wrong about this? > + > + drm_WARN_ON(&dev_priv->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); > + > uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes | > secondary_uncompressed_joiner_pipes; > bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes; > + ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes; > > drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, > "Uncomressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n", > uncompressed_joiner_pipes, bigjoiner_pipes); > + drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, > + "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n", > + ultrajoiner_pipes, bigjoiner_pipes); > drm_WARN(display->drm, secondary_bigjoiner_pipes != > expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), > "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n", > @@ -3702,10 +3777,16 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, > "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n", > expected_uncompjoiner_secondary_pipes(primary_uncompressed_joiner_pipes), > secondary_uncompressed_joiner_pipes); > - > - *primary_pipes = primary_uncompressed_joiner_pipes | primary_bigjoiner_pipes; > - > - *secondary_pipes = secondary_uncompressed_joiner_pipes | secondary_bigjoiner_pipes; > + drm_WARN(display->drm, secondary_ultrajoiner_pipes != > + expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), > + "Wrong secondary ultrajoiner pipes(expected %x, current %x)\n", > + expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), > + secondary_ultrajoiner_pipes); > + > + *primary_pipes = primary_uncompressed_joiner_pipes | primary_bigjoiner_pipes | > + primary_ultrajoiner_pipes; > + *secondary_pipes = secondary_uncompressed_joiner_pipes | secondary_bigjoiner_pipes | > + secondary_ultrajoiner_pipes; > > /* Joiner pipes should always be consecutive primary and secondary */ > drm_WARN(display->drm, *secondary_pipes != *primary_pipes << 1, > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > index f921ad67b587..db07c9775892 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h > @@ -37,6 +37,9 @@ > #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) > #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) > #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) > + spurious newline > +#define ULTRA_JOINER_ENABLE REG_BIT(23) > +#define PRIMARY_ULTRA_JOINER_ENABLE REG_BIT(22) > #define UNCOMPRESSED_JOINER_PRIMARY (1 << 21) > #define UNCOMPRESSED_JOINER_SECONDARY (1 << 20) > > -- > 2.45.2 -- Ville Syrjälä Intel