From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR Date: Mon, 11 Mar 2019 23:38:00 +0000 Message-ID: References: <20190305234734.19506-1-jose.souza@intel.com> <20190305234734.19506-3-jose.souza@intel.com> <20190311233405.GE24277@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0790575771==" Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id AAD0B89BA3 for ; Mon, 11 Mar 2019 23:38:02 +0000 (UTC) In-Reply-To: <20190311233405.GE24277@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Vivi, Rodrigo" Cc: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" List-Id: intel-gfx@lists.freedesktop.org --===============0790575771== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-hqN6GRWl2qk41vwzy5VR" --=-hqN6GRWl2qk41vwzy5VR Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, 2019-03-11 at 16:34 -0700, Rodrigo Vivi wrote: > On Tue, Mar 05, 2019 at 03:47:34PM -0800, Jos=C3=A9 Roberto de Souza > wrote: > > TPS4 support was added to PSR because HBR3/PSR spec was not closed > > when ICL was freezed so if HBR3 was supported by PSR, ICL would > > already be ready but it was not added to spec so lets always > > disable TPS4. > >=20 > > v3: Missed ";" SPANK SPANK SPANK!!! > >=20 > > BSpec: 17524 > >=20 > > Cc: Dhinakaran Pandiyan > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 5 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 16ce9c609c65..a7697909e0c9 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4205,6 +4205,8 @@ enum { > > #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) > > #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) > > #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) > > +#define EDP_PSR_TP4_TIME_SHIFT (6) /* ICL+ */ > > +#define EDP_PSR_TP4_TIME_0US (3 << > > EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */ >=20 > could we please leave this as the rest of the reg and use (3 << 6) > imo easier to read because the rest of reg was already there Sure, I will change to (3 << 6) >=20 > > #define EDP_PSR_TP1_TIME_500us (0 << 4) > > #define EDP_PSR_TP1_TIME_100us (1 << 4) > > #define EDP_PSR_TP1_TIME_2500us (2 << 4) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 2fa2f4c9c935..c70d735f5b93 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct > > intel_dp *intel_dp) > > struct drm_i915_private *dev_priv =3D dp_to_i915(intel_dp); > > u32 val =3D 0; > > =20 > > + if (INTEL_GEN(dev_priv) >=3D 11) > > + val |=3D EDP_PSR_TP4_TIME_0US; > > + > > if (dev_priv->vbt.psr.tp1_wakeup_time_us =3D=3D 0) > > val |=3D EDP_PSR_TP1_TIME_0us; > > else if (dev_priv->vbt.psr.tp1_wakeup_time_us <=3D 100) > > --=20 > > 2.21.0 > >=20 > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-hqN6GRWl2qk41vwzy5VR Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlyG8VUACgkQVenbO/mO Wklw2wgAhlo+wKDKXptsltHwihqfSFFFXFDh/3jf6iicZDz9FZYP2t2GzAyF0TcG WKrG/AHFdUd4YOGFlNDHXao8hmPY6LEDbl05buXFghF6iCdy68gbNSjiubnF1zZy HloneJsWcOG1IV22UvUA598SGD1IPxaRRdNLoe3ZnhEkGlMABAbjEuYMBmxc6L54 Aaa2yIylwyxJeKwve73pEPwKKFOg3H2qwB9NUkKV1I9dzVmjLT5sFhKCmMh2LVih PFWR90WIHUMZWGOsCswNUn0Pig+6MCQCPP0xrX2nhvkJkr7XNWLJjLFNHyTBZAdn Q1v7LqJ56MVQ4vdABil29I7WIkR11A== =fYiy -----END PGP SIGNATURE----- --=-hqN6GRWl2qk41vwzy5VR-- --===============0790575771== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============0790575771==--