From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2 1/3] drm/i915/bdw+: Move misc display IRQ handling to it own function Date: Fri, 12 Apr 2019 22:45:16 +0000 Message-ID: References: <20190412222909.1711-1-jose.souza@intel.com> <20190412224013.GD19065@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2052076933==" Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5E53899C4 for ; Fri, 12 Apr 2019 22:45:18 +0000 (UTC) In-Reply-To: <20190412224013.GD19065@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Vivi, Rodrigo" Cc: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" List-Id: intel-gfx@lists.freedesktop.org --===============2052076933== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-xJFMlW4J+K6UPxCxDvpa" --=-xJFMlW4J+K6UPxCxDvpa Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 2019-04-12 at 15:40 -0700, Rodrigo Vivi wrote: > On Fri, Apr 12, 2019 at 03:29:07PM -0700, Jos=C3=A9 Roberto de Souza > wrote: > > Just moving it to reduce the tabs and avoid break code lines. > > No behavior changes intended here. >=20 > this function is indeed big and deserves a split. > I wonder why haven't you moved the entire de_misc block to a > separated > function instead only the middle of the handling... >=20 > i mean, including reg read above and error message below. It was reading and writing GEN8_DE_MISC_IIR inside of gen8_de_misc_irq_handler() but to keep consistent with the other handlers Dhinakaran suggested this change. >=20 > > v2: > > - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as > > other irq handlers (Dhinakaran) > >=20 > > Cc: Dhinakaran Pandiyan > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/i915_irq.c | 45 ++++++++++++++++++----------- > > ---- > > 1 file changed, 25 insertions(+), 20 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/i915_irq.c > > b/drivers/gpu/drm/i915/i915_irq.c > > index d934545445e1..820d89300454 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -2740,6 +2740,28 @@ static u32 gen8_de_port_aux_mask(struct > > drm_i915_private *dev_priv) > > return mask; > > } > > =20 > > +static void > > +gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 > > iir) > > +{ > > + bool found =3D false; > > + > > + if (iir & GEN8_DE_MISC_GSE) { > > + intel_opregion_asle_intr(dev_priv); > > + found =3D true; > > + } > > + > > + if (iir & GEN8_DE_EDP_PSR) { > > + u32 psr_iir =3D I915_READ(EDP_PSR_IIR); > > + > > + intel_psr_irq_handler(dev_priv, psr_iir); > > + I915_WRITE(EDP_PSR_IIR, psr_iir); > > + found =3D true; > > + } > > + > > + if (!found) > > + DRM_ERROR("Unexpected DE Misc interrupt\n"); > > +} > > + > > static irqreturn_t > > gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 > > master_ctl) > > { > > @@ -2750,29 +2772,12 @@ gen8_de_irq_handler(struct drm_i915_private > > *dev_priv, u32 master_ctl) > > if (master_ctl & GEN8_DE_MISC_IRQ) { > > iir =3D I915_READ(GEN8_DE_MISC_IIR); > > if (iir) { > > - bool found =3D false; > > - > > I915_WRITE(GEN8_DE_MISC_IIR, iir); > > ret =3D IRQ_HANDLED; > > - > > - if (iir & GEN8_DE_MISC_GSE) { > > - intel_opregion_asle_intr(dev_priv); > > - found =3D true; > > - } > > - > > - if (iir & GEN8_DE_EDP_PSR) { > > - u32 psr_iir =3D I915_READ(EDP_PSR_IIR); > > - > > - intel_psr_irq_handler(dev_priv, > > psr_iir); > > - I915_WRITE(EDP_PSR_IIR, psr_iir); > > - found =3D true; > > - } > > - > > - if (!found) > > - DRM_ERROR("Unexpected DE Misc > > interrupt\n"); > > - } > > - else > > + gen8_de_misc_irq_handler(dev_priv, iir); > > + } else { > > DRM_ERROR("The master control interrupt lied > > (DE MISC)!\n"); > > + } > > } > > =20 > > if (INTEL_GEN(dev_priv) >=3D 11 && (master_ctl & > > GEN11_DE_HPD_IRQ)) { > > --=20 > > 2.21.0 > >=20 > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-xJFMlW4J+K6UPxCxDvpa Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlyxFPsACgkQVenbO/mO WkmTPwf+JbK78zuNrYuu0JdnNzM2tQf6BTfUqQIx6lqEzao1GN1KJb8xo+REMmQ1 QAIFDxen4ODfnFmdlNY7w0gwFawTFAVFefn++S6Fgz0MIYePjZ7BRDmna9F82HxI NaVEs/n7sWTW1nsNMrOJI9YYxH393X9LLSsCqiC/vfIxx+4GoB0oHMeF6Ttda7LC gRwecWci/mv6RK+buaev2SCV7JpvUjhyqP3owgcEmi8O6eHbqFqKGTM08F9pMPwU wGJy9mpb6W82pYrx/0p0gh/N/IFVVxdrfkHQo4fRj63KZDbflH27iRiDGEFALXur 3mRGdEoCefk+ccqJXV16AmPC9glSTw== =ZRz8 -----END PGP SIGNATURE----- --=-xJFMlW4J+K6UPxCxDvpa-- --===============2052076933== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============2052076933==--