[PATCH 00/12] drm/i915/flipq: Rough flip queue implementation

[PATCH 00/12] drm/i915/flipq: Rough flip queue implementation

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Initial stab at implementing the PIPEDMC based flip queue.
Briefly smoke tested on LNL, not much more.

Still has quite a few warts..

Ville Syrjälä (12):
  drm/i915/dsb: Extract intel_dsb_ins_align()
  drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()
  drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
  drm/i915/dsb: Extract intel_dsb_{head,tail}()
  drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()
  drm/i915/dmc: Define flip queue related PIPEDMC registers
  drm/i915/flipq: Provide the nuts and bolts code for flip queue
  drm/i915/flipq: Implement flipq queue based commit path
  drm/i915/flipq: Implement Wa_18034343758
  drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
  drm/i915/flipq: Add intel_flipq_dump()
  drm/i915/flipq: Enable flipq by default for testing

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  |  69 +++-
 .../drm/i915/display/intel_display_driver.c   |   3 +
 .../drm/i915/display/intel_display_params.c   |   3 +
 .../drm/i915/display/intel_display_params.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |  20 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  90 ++++-
 drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172 +++++++-
 drivers/gpu/drm/i915/display/intel_dsb.c      |  63 ++-
 drivers/gpu/drm/i915/display/intel_dsb.h      |   2 +
 drivers/gpu/drm/i915/display/intel_flipq.c    | 374 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_flipq.h    |  35 ++
 drivers/gpu/drm/xe/Makefile                   |   1 +
 14 files changed, 811 insertions(+), 34 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h

-- 
2.49.0

[PATCH 01/12] drm/i915/dsb: Extract intel_dsb_ins_align()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code that alings the next instruction to the next
QW boundary into a small helper. I'll have some more uses for
this later.

Also explain why we don't have to zero out the extra DW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 393ea07947b4..d6641cfe8061 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
-static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
+static void intel_dsb_ins_align(struct intel_dsb *dsb)
 {
-	if (!assert_dsb_has_room(dsb))
-		return;
-
-	/* Every instruction should be 8 byte aligned. */
+	/*
+	 * Every instruction should be 8 byte aligned.
+	 *
+	 * The only way to get unaligned free_pos is via
+	 * intel_dsb_reg_write_indexed() which already
+	 * makes sure the next dword is zeroed, so no need
+	 * to clear it here.
+	 */
 	dsb->free_pos = ALIGN(dsb->free_pos, 2);
+}
+
+static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
+{
+	if (!assert_dsb_has_room(dsb))
+		return;
+
+	intel_dsb_ins_align(dsb);
 
 	dsb->ins_start_offset = dsb->free_pos;
 	dsb->ins[0] = ldw;
-- 
2.49.0

[PATCH 02/12] drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If the free_post is not QW aligned we don't have to memset the
extra DW needed to make it so, as the only way that can happen
is via intel_dsb_reg_write_indexed() which already makes sure
the next DW is zeroed.

Not a big deal, but this is more consistent how all the other
stuff operates that puts instructions into the DSB buffer, and
we'll get a few more of those soon.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index d6641cfe8061..b5c8972dfad2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -504,6 +504,8 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb)
 {
 	u32 aligned_tail, tail;
 
+	intel_dsb_ins_align(dsb);
+
 	tail = dsb->free_pos * 4;
 	aligned_tail = ALIGN(tail, CACHELINE_BYTES);
 
-- 
2.49.0

[PATCH 03/12] drm/i915/dsb: Extract assert_dsb_tail_is_aligned()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DSB tail alignment checks into helper. We already
have two uses of this, and soo we'll get a third.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index b5c8972dfad2..b7d11eb1ce80 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -204,6 +204,15 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
 			 crtc->base.base.id, crtc->base.name, dsb->id);
 }
 
+static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct intel_display *display = to_intel_display(crtc->base.dev);
+
+	return !drm_WARN_ON(display->drm,
+			    !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES));
+}
+
 static void intel_dsb_dump(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
@@ -623,9 +632,10 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
 		return;
 
+	if (!assert_dsb_tail_is_aligned(chained_dsb))
+		return;
+
 	tail = chained_dsb->free_pos * 4;
-	if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
-		return;
 
 	intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
 			    ctrl | DSB_ENABLE);
@@ -697,10 +707,11 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	enum pipe pipe = crtc->pipe;
 	u32 tail;
 
-	tail = dsb->free_pos * 4;
-	if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
+	if (!assert_dsb_tail_is_aligned(dsb))
 		return;
 
+	tail = dsb->free_pos * 4;
+
 	if (is_dsb_busy(display, pipe, dsb->id)) {
 		drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
-- 
2.49.0

[PATCH 04/12] drm/i915/dsb: Extract intel_dsb_{head,tail}()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code that calculates the DSB_HEAD/TAIL register
values into small helpers. We already have two copies of this,
and soon there will be a third.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index b7d11eb1ce80..b54fb6170364 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -237,6 +237,16 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
+static unsigned int intel_dsb_head(struct intel_dsb *dsb)
+{
+	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
+}
+
+static unsigned int intel_dsb_tail(struct intel_dsb *dsb)
+{
+	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4;
+}
+
 static void intel_dsb_ins_align(struct intel_dsb *dsb)
 {
 	/*
@@ -627,7 +637,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(state->base.dev);
 	struct intel_crtc *crtc = dsb->crtc;
 	enum pipe pipe = crtc->pipe;
-	u32 tail;
 
 	if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
 		return;
@@ -635,8 +644,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	if (!assert_dsb_tail_is_aligned(chained_dsb))
 		return;
 
-	tail = chained_dsb->free_pos * 4;
-
 	intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
 			    ctrl | DSB_ENABLE);
 
@@ -657,10 +664,10 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	}
 
 	intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),
-			    intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf));
+			    intel_dsb_head(chained_dsb));
 
 	intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
-			    intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail);
+			    intel_dsb_tail(chained_dsb));
 
 	if (ctrl & DSB_WAIT_FOR_VBLANK) {
 		/*
@@ -705,13 +712,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	struct intel_crtc *crtc = dsb->crtc;
 	struct intel_display *display = to_intel_display(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	u32 tail;
 
 	if (!assert_dsb_tail_is_aligned(dsb))
 		return;
 
-	tail = dsb->free_pos * 4;
-
 	if (is_dsb_busy(display, pipe, dsb->id)) {
 		drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
@@ -729,7 +733,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 			  dsb_error_int_en(display) | DSB_PROG_INT_EN);
 
 	intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
-			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf));
+			  intel_dsb_head(dsb));
 
 	if (hw_dewake_scanline >= 0) {
 		int diff, position;
@@ -751,7 +755,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	}
 
 	intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),
-			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail);
+			  intel_dsb_tail(dsb));
 }
 
 /**
-- 
2.49.0

[PATCH 05/12] drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The upcoming flip queue implementation will need to know the
DSB buffer head and size. Expose those outside intel_dsb.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 9 +++++++--
 drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index b54fb6170364..82cb58cf9c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -237,14 +237,19 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
-static unsigned int intel_dsb_head(struct intel_dsb *dsb)
+unsigned int intel_dsb_size(struct intel_dsb *dsb)
+{
+	return dsb->free_pos * 4;
+}
+
+unsigned int intel_dsb_head(struct intel_dsb *dsb)
 {
 	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
 }
 
 static unsigned int intel_dsb_tail(struct intel_dsb *dsb)
 {
-	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4;
+	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + intel_dsb_size(dsb);
 }
 
 static void intel_dsb_ins_align(struct intel_dsb *dsb)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index e843c52bf97c..6a90ffe1f6ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -26,6 +26,8 @@ enum intel_dsb_id {
 	I915_MAX_DSBS,
 };
 
+unsigned int intel_dsb_size(struct intel_dsb *dsb);
+unsigned int intel_dsb_head(struct intel_dsb *dsb);
 struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc,
 				    enum intel_dsb_id dsb_id,
-- 
2.49.0

RE: [PATCH 05/12] drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 05/12] drm/i915/dsb: Provide intel_dsb_head() and
> intel_dsb_size()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The upcoming flip queue implementation will need to know the DSB buffer head
> and size. Expose those outside intel_dsb.c.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 9 +++++++--
> drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index b54fb6170364..82cb58cf9c6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -237,14 +237,19 @@ static bool is_dsb_busy(struct intel_display *display,
> enum pipe pipe,
>  	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) &
> DSB_STATUS_BUSY;  }
> 
> -static unsigned int intel_dsb_head(struct intel_dsb *dsb)
> +unsigned int intel_dsb_size(struct intel_dsb *dsb) {
> +	return dsb->free_pos * 4;
> +}
> +
> +unsigned int intel_dsb_head(struct intel_dsb *dsb)
>  {
>  	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
>  }
> 
>  static unsigned int intel_dsb_tail(struct intel_dsb *dsb)  {
> -	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4;
> +	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) +
> +intel_dsb_size(dsb);
>  }
> 
>  static void intel_dsb_ins_align(struct intel_dsb *dsb) diff --git
> a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index e843c52bf97c..6a90ffe1f6ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -26,6 +26,8 @@ enum intel_dsb_id {
>  	I915_MAX_DSBS,
>  };
> 
> +unsigned int intel_dsb_size(struct intel_dsb *dsb); unsigned int
> +intel_dsb_head(struct intel_dsb *dsb);
>  struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
>  				    struct intel_crtc *crtc,
>  				    enum intel_dsb_id dsb_id,
> --
> 2.49.0

[PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the register definitions for a bunch of flip queue related
PIPEDMC registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172 +++++++++++++++++-
 1 file changed, 171 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index d8e715677454..613160a1f9f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_DMC_REGS_H__
 #define __INTEL_DMC_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 enum dmc_event_id {
 	DMC_EVENT_TRUE = 0x0,
@@ -287,6 +287,17 @@ enum pipedmc_event_id {
 #define MTL_PIPEDMC_CONTROL		_MMIO(0x45250)
 #define  PIPEDMC_ENABLE_MTL(pipe)	REG_BIT(((pipe) - PIPE_A) * 4)
 
+#define _PIPEDMC_LOAD_HTP_A		0x5f000
+#define _PIPEDMC_LOAD_HTP_B		0x5f400
+#define PIPEDMC_LOAD_HTP(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
+
+#define _PIPEDMC_CTL_A		0x5f064
+#define _PIPEDMC_CTL_B		0x5f464
+#define PIPEDMC_CTL(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_CTL_A, _PIPEDMC_CTL_B)
+#define   PIPEDMC_HALT			REG_BIT(31)
+#define   PIPEDMC_STEP			REG_BIT(27)
+#define   PIPEDMC_CLOCKGATE		REG_BIT(23)
+
 #define _PIPEDMC_STATUS_A		0x5f06c
 #define _PIPEDMC_STATUS_B		0x5f46c
 #define PIPEDMC_STATUS(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)
@@ -298,6 +309,139 @@ enum pipedmc_event_id {
 #define   PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE		REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /* Wa_16018781658:lnl[a0] */
 #define   PIPEDMC_EVT_PENDING		REG_GENMASK(7, 0)
 
+#define _PIPEDMC_FQ_CTRL_A		0x5f078
+#define _PIPEDMC_FQ_CTRL_B		0x5f478
+#define PIPEDMC_FQ_CTRL(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
+#define   PIPEDMC_FQ_CTRL_ENABLE	REG_BIT(31)
+#define   PIPEDMC_FQ_CTRL_BUSY		REG_BIT(30)
+#define   PIPEDMC_FQ_CTRL_ASYNC		REG_BIT(29)
+#define   PIPEDMC_FQ_CTRL_PREEMPT	REG_BIT(0)
+
+#define _PIPEDMC_FQ_STATUS_A		0x5f098
+#define _PIPEDMC_FQ_STATUS_B		0x5f498
+#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
+#define   PIPEDMC_FQ_STATUS_BUSY		REG_BIT(31)
+#define   PIPEDMC_FQ_STATUS_W2_LIVE_STATUS	REG_BIT(1)
+#define   PIPEDMC_FQ_STATUS_W1_LIVE_STATUS	REG_BIT(0)
+
+#define _PIPEDMC_FPQ_ATOMIC_TP_A	0x5f0a0
+#define _PIPEDMC_FPQ_ATOMIC_TP_B	0x5f4a0
+#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
+#define   PIPEDMC_FPQ_PLANEQ_3_TP_MASK	REG_GENMASK(31, 26)
+#define   PIPEDMC_FPQ_PLANEQ_3_TP(tail)	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
+#define   PIPEDMC_FPQ_PLANEQ_2_TP_MASK	REG_GENMASK(24, 19)
+#define   PIPEDMC_FPQ_PLANEQ_2_TP(tail)	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
+#define   PIPEDMC_FPQ_PLANEQ_1_TP_MASK	REG_GENMASK(17, 12)
+#define   PIPEDMC_FPQ_PLANEQ_1_TP(tail)	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
+#define   PIPEDMC_FPQ_FASTQ_TP_MASK	REG_GENMASK(10, 6)
+#define   PIPEDMC_FPQ_FASTQ_TP(tail)	REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
+#define   PIPEDMC_FPQ_GENERALQ_TP_MASK	REG_GENMASK(4, 0)
+#define   PIPEDMC_FPQ_GENERALQ_TP(tail)	REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
+
+#define _PIPEDMC_FPQ_LINES_TO_W1_A	0x5f0a4
+#define _PIPEDMC_FPQ_LINES_TO_W1_B	0x5f4a4
+#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
+
+#define _PIPEDMC_FPQ_LINES_TO_W2_A	0x5f0a8
+#define _PIPEDMC_FPQ_LINES_TO_W2_B	0x5f4a8
+#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
+
+#define _PIPEDMC_SCANLINECMP_A		0x5f11c
+#define _PIPEDMC_SCANLINECMP_B		0x5f51c
+#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
+#define   PIPEDMC_SCANLINECMP_EN	REG_BIT(31)
+#define   PIPEDMC_SCANLINE_NUMBER	REG_GENMASK(27, 0)
+
+#define _PIPEDMC_SCANLINECMPLOWER_A	0x5f120
+#define _PIPEDMC_SCANLINECMPLOWER_B	0x5f520
+#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
+#define   PIPEDMC_SCANLINEINRANGECMP_EN		REG_BIT(31)
+#define   PIPEDMC_SCANLINEOUTRANGECMP_EN	REG_BIT(30)
+#define   PIPEDMC_SCANLINE_LOWER_MASK		REG_GENMASK(27, 0)
+#define   PIPEDMC_SCANLINE_LOWER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
+
+#define _PIPEDMC_SCANLINECMPUPPER_A	0x5f124
+#define _PIPEDMC_SCANLINECMPUPPER_B	0x5f524
+#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
+#define   PIPEDMC_SCANLINE_UPPER_MASK	REG_GENMASK(27, 0)
+#define   PIPEDMC_SCANLINE_UPPER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
+
+#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
+			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
+			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
+	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
+				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
+				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
+				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
+				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
+
+#define _PIPEDMC_FPQ1_HP_A		0x5f128
+#define _PIPEDMC_FPQ2_HP_A		0x5f138
+#define _PIPEDMC_FPQ3_HP_A		0x5f168
+#define _PIPEDMC_FPQ4_HP_A		0x5f174
+#define _PIPEDMC_FPQ5_HP_A		0x5f180
+#define _PIPEDMC_FPQ1_HP_B		0x5f528
+#define _PIPEDMC_FPQ2_HP_B		0x5f538
+#define _PIPEDMC_FPQ3_HP_B		0x5f568
+#define _PIPEDMC_FPQ4_HP_B		0x5f574
+#define _PIPEDMC_FPQ5_HP_B		0x5f580
+#define PIPEDMC_FPQ_HP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
+							  _PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
+							  _PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
+							  _PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
+							  _PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
+
+#define _PIPEDMC_FPQ1_TP_A		0x5f12c
+#define _PIPEDMC_FPQ2_TP_A		0x5f13c
+#define _PIPEDMC_FPQ3_TP_A		0x5f16c
+#define _PIPEDMC_FPQ4_TP_A		0x5f178
+#define _PIPEDMC_FPQ5_TP_A		0x5f184
+#define _PIPEDMC_FPQ1_TP_B		0x5f52c
+#define _PIPEDMC_FPQ2_TP_B		0x5f53c
+#define _PIPEDMC_FPQ3_TP_B		0x5f56c
+#define _PIPEDMC_FPQ4_TP_B		0x5f578
+#define _PIPEDMC_FPQ5_TP_B		0x5f584
+#define PIPEDMC_FPQ_TP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
+							  _PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
+							  _PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
+							  _PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
+							  _PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
+
+#define _PIPEDMC_FPQ1_CHP_A		0x5f130
+#define _PIPEDMC_FPQ2_CHP_A		0x5f140
+#define _PIPEDMC_FPQ3_CHP_A		0x5f170
+#define _PIPEDMC_FPQ4_CHP_A		0x5f17c
+#define _PIPEDMC_FPQ5_CHP_A		0x5f188
+#define _PIPEDMC_FPQ1_CHP_B		0x5f530
+#define _PIPEDMC_FPQ2_CHP_B		0x5f540
+#define _PIPEDMC_FPQ3_CHP_B		0x5f570
+#define _PIPEDMC_FPQ4_CHP_B		0x5f57c
+#define _PIPEDMC_FPQ5_CHP_B		0x5f588
+#define PIPEDMC_FPQ_CHP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
+							  _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
+							  _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
+							  _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
+							  _PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
+
+#define _PIPEDMC_FPQ_TS_A		0x5f134
+#define _PIPEDMC_FPQ_TS_B		0x5f534
+#define PIPEDMC_FPQ_TS(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
+
+#define _PIPEDMC_SCANLINE_RO_A		0x5f144
+#define _PIPEDMC_SCANLINE_RO_B		0x5f544
+#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
+
+#define _PIPEDMC_FPQ_CTL1_A		0x5f160
+#define _PIPEDMC_FPQ_CTL1_B		0x5f560
+#define PIPEDMC_FPQ_CTL1(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
+#define   PIPEDMC_SW_DMC_WAKE		REG_BIT(0)
+
+#define _PIPEDMC_FPQ_CTL2_A		0x5f164
+#define _PIPEDMC_FPQ_CTL2_B		0x5f564
+#define PIPEDMC_FPQ_CTL2(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
+#define   PIPEDMC_DMC_INT_AT_DELAYED_VBLANK	REG_BIT(1)
+#define   PIPEDMC_W1_DMC_WAKE			REG_BIT(0)
+
 #define _PIPEDMC_INTERRUPT_A		0x5f190 /* lnl+ */
 #define _PIPEDMC_INTERRUPT_B		0x5f590 /* lnl+ */
 #define PIPEDMC_INTERRUPT(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B)
@@ -394,4 +538,30 @@ enum pipedmc_event_id {
 #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
 #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
 
+#define DMC_FQ_W2_PTS_CFG_SEL	_MMIO(0x8f240)
+#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK	REG_GENMASK(25, 24)
+#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
+#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK	REG_GENMASK(17, 16)
+#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
+#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK	REG_GENMASK(9, 8)
+#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
+#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK	REG_GENMASK(1, 0)
+#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))
+
+/* planel/general flip queue entries */
+#define PIPEDMC_FQ_RAM(start_mmioaddr, i)	_MMIO((start_mmioaddr) + (i) * 4)
+/* DW0 pts */
+/* DW1 head */
+/* DW2 size/etc. */
+#define FQ_INTERRUPT		REG_BIT(31)
+#define FQ_DSB_ID_MASK		REG_GENMASK(30, 29)
+#define FQ_DSB_ID(dsb_id)	REG_FIELD_PREP(FQ_DSB_ID_MASK, (dsb_id))
+#define FQ_EXECUTED		REG_BIT(28)
+#define FQ_DSB_SIZE_MASK	REG_GENMASK(15, 0)
+#define FQ_DSB_SIZE(size)	REG_FIELD_PREP(FQ_DSB_SIZE_MASK, (size))
+/* DW3 reserved (plane queues) */
+/* DW3 second DSB head (general queue) */
+/* DW4 second DSB size/etc. (general queue) */
+/* DW5 reserved (general queue) */
+
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.49.0

RE: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC registers

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC
> registers
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add the register definitions for a bunch of flip queue related PIPEDMC registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172 +++++++++++++++++-
>  1 file changed, 171 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index d8e715677454..613160a1f9f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -6,7 +6,7 @@
>  #ifndef __INTEL_DMC_REGS_H__
>  #define __INTEL_DMC_REGS_H__
> 
> -#include "i915_reg_defs.h"
> +#include "intel_display_reg_defs.h"
> 
>  enum dmc_event_id {
>  	DMC_EVENT_TRUE = 0x0,
> @@ -287,6 +287,17 @@ enum pipedmc_event_id {
>  #define MTL_PIPEDMC_CONTROL		_MMIO(0x45250)
>  #define  PIPEDMC_ENABLE_MTL(pipe)	REG_BIT(((pipe) - PIPE_A) * 4)
> 
> +#define _PIPEDMC_LOAD_HTP_A		0x5f000
> +#define _PIPEDMC_LOAD_HTP_B		0x5f400
> +#define PIPEDMC_LOAD_HTP(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
> +
> +#define _PIPEDMC_CTL_A		0x5f064
> +#define _PIPEDMC_CTL_B		0x5f464
> +#define PIPEDMC_CTL(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_CTL_A,
> _PIPEDMC_CTL_B)
> +#define   PIPEDMC_HALT			REG_BIT(31)
> +#define   PIPEDMC_STEP			REG_BIT(27)
> +#define   PIPEDMC_CLOCKGATE		REG_BIT(23)
> +
>  #define _PIPEDMC_STATUS_A		0x5f06c
>  #define _PIPEDMC_STATUS_B		0x5f46c
>  #define PIPEDMC_STATUS(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)
> @@ -298,6 +309,139 @@ enum pipedmc_event_id {
>  #define   PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE
> 	REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /*
> Wa_16018781658:lnl[a0] */
>  #define   PIPEDMC_EVT_PENDING		REG_GENMASK(7, 0)
> 
> +#define _PIPEDMC_FQ_CTRL_A		0x5f078
> +#define _PIPEDMC_FQ_CTRL_B		0x5f478
> +#define PIPEDMC_FQ_CTRL(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
> +#define   PIPEDMC_FQ_CTRL_ENABLE	REG_BIT(31)
> +#define   PIPEDMC_FQ_CTRL_BUSY		REG_BIT(30)
> +#define   PIPEDMC_FQ_CTRL_ASYNC		REG_BIT(29)
> +#define   PIPEDMC_FQ_CTRL_PREEMPT	REG_BIT(0)
> +
> +#define _PIPEDMC_FQ_STATUS_A		0x5f098
> +#define _PIPEDMC_FQ_STATUS_B		0x5f498
> +#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
> +#define   PIPEDMC_FQ_STATUS_BUSY		REG_BIT(31)
> +#define   PIPEDMC_FQ_STATUS_W2_LIVE_STATUS	REG_BIT(1)
> +#define   PIPEDMC_FQ_STATUS_W1_LIVE_STATUS	REG_BIT(0)
> +
> +#define _PIPEDMC_FPQ_ATOMIC_TP_A	0x5f0a0
> +#define _PIPEDMC_FPQ_ATOMIC_TP_B	0x5f4a0
> +#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
> +#define   PIPEDMC_FPQ_PLANEQ_3_TP_MASK	REG_GENMASK(31, 26)
> +#define   PIPEDMC_FPQ_PLANEQ_3_TP(tail)
> 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
> +#define   PIPEDMC_FPQ_PLANEQ_2_TP_MASK	REG_GENMASK(24, 19)
> +#define   PIPEDMC_FPQ_PLANEQ_2_TP(tail)
> 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
> +#define   PIPEDMC_FPQ_PLANEQ_1_TP_MASK	REG_GENMASK(17, 12)
> +#define   PIPEDMC_FPQ_PLANEQ_1_TP(tail)
> 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
> +#define   PIPEDMC_FPQ_FASTQ_TP_MASK	REG_GENMASK(10, 6)
> +#define   PIPEDMC_FPQ_FASTQ_TP(tail)
> 	REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
> +#define   PIPEDMC_FPQ_GENERALQ_TP_MASK	REG_GENMASK(4, 0)
> +#define   PIPEDMC_FPQ_GENERALQ_TP(tail)
> 	REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
> +
> +#define _PIPEDMC_FPQ_LINES_TO_W1_A	0x5f0a4
> +#define _PIPEDMC_FPQ_LINES_TO_W1_B	0x5f4a4
> +#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
> +
> +#define _PIPEDMC_FPQ_LINES_TO_W2_A	0x5f0a8
> +#define _PIPEDMC_FPQ_LINES_TO_W2_B	0x5f4a8
> +#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
> +
> +#define _PIPEDMC_SCANLINECMP_A		0x5f11c
> +#define _PIPEDMC_SCANLINECMP_B		0x5f51c
> +#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe),
> _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
> +#define   PIPEDMC_SCANLINECMP_EN	REG_BIT(31)
> +#define   PIPEDMC_SCANLINE_NUMBER	REG_GENMASK(27, 0)

The scanline number seems to be 0:20 for LNL/PTL, can you please re-check once. It's extended
to 27 for later platforms.

> +#define _PIPEDMC_SCANLINECMPLOWER_A	0x5f120
> +#define _PIPEDMC_SCANLINECMPLOWER_B	0x5f520
> +#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe),
> _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
> +#define   PIPEDMC_SCANLINEINRANGECMP_EN		REG_BIT(31)
> +#define   PIPEDMC_SCANLINEOUTRANGECMP_EN	REG_BIT(30)
> +#define   PIPEDMC_SCANLINE_LOWER_MASK		REG_GENMASK(27, 0)

This as well.

> +#define   PIPEDMC_SCANLINE_LOWER(scanline)
> 	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
> +
> +#define _PIPEDMC_SCANLINECMPUPPER_A	0x5f124
> +#define _PIPEDMC_SCANLINECMPUPPER_B	0x5f524
> +#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe),
> _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
> +#define   PIPEDMC_SCANLINE_UPPER_MASK	REG_GENMASK(27, 0)

Same as above.

> +#define   PIPEDMC_SCANLINE_UPPER(scanline)
> 	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
> +
> +#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
> +			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
> +			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
> +	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
> +				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
> +				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
> +				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
> +				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
> +
> +#define _PIPEDMC_FPQ1_HP_A		0x5f128
> +#define _PIPEDMC_FPQ2_HP_A		0x5f138
> +#define _PIPEDMC_FPQ3_HP_A		0x5f168
> +#define _PIPEDMC_FPQ4_HP_A		0x5f174
> +#define _PIPEDMC_FPQ5_HP_A		0x5f180
> +#define _PIPEDMC_FPQ1_HP_B		0x5f528
> +#define _PIPEDMC_FPQ2_HP_B		0x5f538
> +#define _PIPEDMC_FPQ3_HP_B		0x5f568
> +#define _PIPEDMC_FPQ4_HP_B		0x5f574
> +#define _PIPEDMC_FPQ5_HP_B		0x5f580

This entry 5 is not used, is it intentional ?

> +#define PIPEDMC_FPQ_HP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> +
> _PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
> +
> _PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
> +
> _PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
> +
> _PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
> +
> +#define _PIPEDMC_FPQ1_TP_A		0x5f12c
> +#define _PIPEDMC_FPQ2_TP_A		0x5f13c
> +#define _PIPEDMC_FPQ3_TP_A		0x5f16c
> +#define _PIPEDMC_FPQ4_TP_A		0x5f178
> +#define _PIPEDMC_FPQ5_TP_A		0x5f184
> +#define _PIPEDMC_FPQ1_TP_B		0x5f52c
> +#define _PIPEDMC_FPQ2_TP_B		0x5f53c
> +#define _PIPEDMC_FPQ3_TP_B		0x5f56c
> +#define _PIPEDMC_FPQ4_TP_B		0x5f578
> +#define _PIPEDMC_FPQ5_TP_B		0x5f584
> +#define PIPEDMC_FPQ_TP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> +
> _PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
> +
> _PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
> +
> _PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
> +
> _PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
> +
> +#define _PIPEDMC_FPQ1_CHP_A		0x5f130
> +#define _PIPEDMC_FPQ2_CHP_A		0x5f140
> +#define _PIPEDMC_FPQ3_CHP_A		0x5f170
> +#define _PIPEDMC_FPQ4_CHP_A		0x5f17c
> +#define _PIPEDMC_FPQ5_CHP_A		0x5f188
> +#define _PIPEDMC_FPQ1_CHP_B		0x5f530
> +#define _PIPEDMC_FPQ2_CHP_B		0x5f540
> +#define _PIPEDMC_FPQ3_CHP_B		0x5f570
> +#define _PIPEDMC_FPQ4_CHP_B		0x5f57c
> +#define _PIPEDMC_FPQ5_CHP_B		0x5f588
> +#define PIPEDMC_FPQ_CHP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> +
> _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
> +
> _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
> +
> _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
> +
> _PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
> +
> +#define _PIPEDMC_FPQ_TS_A		0x5f134
> +#define _PIPEDMC_FPQ_TS_B		0x5f534
> +#define PIPEDMC_FPQ_TS(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
> +
> +#define _PIPEDMC_SCANLINE_RO_A		0x5f144
> +#define _PIPEDMC_SCANLINE_RO_B		0x5f544
> +#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe),
> _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
> +
> +#define _PIPEDMC_FPQ_CTL1_A		0x5f160
> +#define _PIPEDMC_FPQ_CTL1_B		0x5f560
> +#define PIPEDMC_FPQ_CTL1(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
> +#define   PIPEDMC_SW_DMC_WAKE		REG_BIT(0)
> +
> +#define _PIPEDMC_FPQ_CTL2_A		0x5f164
> +#define _PIPEDMC_FPQ_CTL2_B		0x5f564
> +#define PIPEDMC_FPQ_CTL2(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
> +#define   PIPEDMC_DMC_INT_AT_DELAYED_VBLANK	REG_BIT(1)
> +#define   PIPEDMC_W1_DMC_WAKE			REG_BIT(0)
> +
>  #define _PIPEDMC_INTERRUPT_A		0x5f190 /* lnl+ */
>  #define _PIPEDMC_INTERRUPT_B		0x5f590 /* lnl+ */
>  #define PIPEDMC_INTERRUPT(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B)
> @@ -394,4 +538,30 @@ enum pipedmc_event_id {
>  #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
>  #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
> 
> +#define DMC_FQ_W2_PTS_CFG_SEL	_MMIO(0x8f240)
> +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK
> 	REG_GENMASK(25, 24)

This is extended to 3 bit 24:26, please check once.

> +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)
> 	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK,
> (pipe))
> +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK
> 	REG_GENMASK(17, 16)

This as well, 16:18

> +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)
> 	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK,
> (pipe))
> +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK
> 	REG_GENMASK(9, 8)

This is 8:10

> +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)
> 	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK,
> (pipe))
> +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK
> 	REG_GENMASK(1, 0)

This is 0:2.

> +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)
> 	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK,
> (pipe))
> +
> +/* planel/general flip queue entries */
> +#define PIPEDMC_FQ_RAM(start_mmioaddr, i)	_MMIO((start_mmioaddr) + (i)
> * 4)
> +/* DW0 pts */
> +/* DW1 head */
> +/* DW2 size/etc. */
> +#define FQ_INTERRUPT		REG_BIT(31)
> +#define FQ_DSB_ID_MASK		REG_GENMASK(30, 29)
> +#define FQ_DSB_ID(dsb_id)	REG_FIELD_PREP(FQ_DSB_ID_MASK, (dsb_id))
> +#define FQ_EXECUTED		REG_BIT(28)
> +#define FQ_DSB_SIZE_MASK	REG_GENMASK(15, 0)
> +#define FQ_DSB_SIZE(size)	REG_FIELD_PREP(FQ_DSB_SIZE_MASK, (size))
> +/* DW3 reserved (plane queues) */
> +/* DW3 second DSB head (general queue) */
> +/* DW4 second DSB size/etc. (general queue) */
> +/* DW5 reserved (general queue) */
> +
>  #endif /* __INTEL_DMC_REGS_H__ */
> --
> 2.49.0

Re: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC registers

[Ville Syrjälä]

On Sun, May 18, 2025 at 07:41:06PM +0000, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> > Sent: Friday, May 16, 2025 5:04 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: intel-xe@lists.freedesktop.org
> > Subject: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC
> > registers
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add the register definitions for a bunch of flip queue related PIPEDMC registers.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172 +++++++++++++++++-
> >  1 file changed, 171 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > index d8e715677454..613160a1f9f2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > @@ -6,7 +6,7 @@
> >  #ifndef __INTEL_DMC_REGS_H__
> >  #define __INTEL_DMC_REGS_H__
> > 
> > -#include "i915_reg_defs.h"
> > +#include "intel_display_reg_defs.h"
> > 
> >  enum dmc_event_id {
> >  	DMC_EVENT_TRUE = 0x0,
> > @@ -287,6 +287,17 @@ enum pipedmc_event_id {
> >  #define MTL_PIPEDMC_CONTROL		_MMIO(0x45250)
> >  #define  PIPEDMC_ENABLE_MTL(pipe)	REG_BIT(((pipe) - PIPE_A) * 4)
> > 
> > +#define _PIPEDMC_LOAD_HTP_A		0x5f000
> > +#define _PIPEDMC_LOAD_HTP_B		0x5f400
> > +#define PIPEDMC_LOAD_HTP(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
> > +
> > +#define _PIPEDMC_CTL_A		0x5f064
> > +#define _PIPEDMC_CTL_B		0x5f464
> > +#define PIPEDMC_CTL(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_CTL_A,
> > _PIPEDMC_CTL_B)
> > +#define   PIPEDMC_HALT			REG_BIT(31)
> > +#define   PIPEDMC_STEP			REG_BIT(27)
> > +#define   PIPEDMC_CLOCKGATE		REG_BIT(23)
> > +
> >  #define _PIPEDMC_STATUS_A		0x5f06c
> >  #define _PIPEDMC_STATUS_B		0x5f46c
> >  #define PIPEDMC_STATUS(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B)
> > @@ -298,6 +309,139 @@ enum pipedmc_event_id {
> >  #define   PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE
> > 	REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /*
> > Wa_16018781658:lnl[a0] */
> >  #define   PIPEDMC_EVT_PENDING		REG_GENMASK(7, 0)
> > 
> > +#define _PIPEDMC_FQ_CTRL_A		0x5f078
> > +#define _PIPEDMC_FQ_CTRL_B		0x5f478
> > +#define PIPEDMC_FQ_CTRL(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
> > +#define   PIPEDMC_FQ_CTRL_ENABLE	REG_BIT(31)
> > +#define   PIPEDMC_FQ_CTRL_BUSY		REG_BIT(30)
> > +#define   PIPEDMC_FQ_CTRL_ASYNC		REG_BIT(29)
> > +#define   PIPEDMC_FQ_CTRL_PREEMPT	REG_BIT(0)
> > +
> > +#define _PIPEDMC_FQ_STATUS_A		0x5f098
> > +#define _PIPEDMC_FQ_STATUS_B		0x5f498
> > +#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
> > +#define   PIPEDMC_FQ_STATUS_BUSY		REG_BIT(31)
> > +#define   PIPEDMC_FQ_STATUS_W2_LIVE_STATUS	REG_BIT(1)
> > +#define   PIPEDMC_FQ_STATUS_W1_LIVE_STATUS	REG_BIT(0)
> > +
> > +#define _PIPEDMC_FPQ_ATOMIC_TP_A	0x5f0a0
> > +#define _PIPEDMC_FPQ_ATOMIC_TP_B	0x5f4a0
> > +#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
> > +#define   PIPEDMC_FPQ_PLANEQ_3_TP_MASK	REG_GENMASK(31, 26)
> > +#define   PIPEDMC_FPQ_PLANEQ_3_TP(tail)
> > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
> > +#define   PIPEDMC_FPQ_PLANEQ_2_TP_MASK	REG_GENMASK(24, 19)
> > +#define   PIPEDMC_FPQ_PLANEQ_2_TP(tail)
> > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
> > +#define   PIPEDMC_FPQ_PLANEQ_1_TP_MASK	REG_GENMASK(17, 12)
> > +#define   PIPEDMC_FPQ_PLANEQ_1_TP(tail)
> > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
> > +#define   PIPEDMC_FPQ_FASTQ_TP_MASK	REG_GENMASK(10, 6)
> > +#define   PIPEDMC_FPQ_FASTQ_TP(tail)
> > 	REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
> > +#define   PIPEDMC_FPQ_GENERALQ_TP_MASK	REG_GENMASK(4, 0)
> > +#define   PIPEDMC_FPQ_GENERALQ_TP(tail)
> > 	REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
> > +
> > +#define _PIPEDMC_FPQ_LINES_TO_W1_A	0x5f0a4
> > +#define _PIPEDMC_FPQ_LINES_TO_W1_B	0x5f4a4
> > +#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
> > +
> > +#define _PIPEDMC_FPQ_LINES_TO_W2_A	0x5f0a8
> > +#define _PIPEDMC_FPQ_LINES_TO_W2_B	0x5f4a8
> > +#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
> > +
> > +#define _PIPEDMC_SCANLINECMP_A		0x5f11c
> > +#define _PIPEDMC_SCANLINECMP_B		0x5f51c
> > +#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe),
> > _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
> > +#define   PIPEDMC_SCANLINECMP_EN	REG_BIT(31)
> > +#define   PIPEDMC_SCANLINE_NUMBER	REG_GENMASK(27, 0)
> 
> The scanline number seems to be 0:20 for LNL/PTL, can you please re-check once. It's extended
> to 27 for later platforms.

The later stuff seems uncertain, so I'll drop these to 21 bits
for now.

> 
> > +#define _PIPEDMC_SCANLINECMPLOWER_A	0x5f120
> > +#define _PIPEDMC_SCANLINECMPLOWER_B	0x5f520
> > +#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe),
> > _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
> > +#define   PIPEDMC_SCANLINEINRANGECMP_EN		REG_BIT(31)
> > +#define   PIPEDMC_SCANLINEOUTRANGECMP_EN	REG_BIT(30)
> > +#define   PIPEDMC_SCANLINE_LOWER_MASK		REG_GENMASK(27, 0)
> 
> This as well.
> 
> > +#define   PIPEDMC_SCANLINE_LOWER(scanline)
> > 	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
> > +
> > +#define _PIPEDMC_SCANLINECMPUPPER_A	0x5f124
> > +#define _PIPEDMC_SCANLINECMPUPPER_B	0x5f524
> > +#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe),
> > _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
> > +#define   PIPEDMC_SCANLINE_UPPER_MASK	REG_GENMASK(27, 0)
> 
> Same as above.
> 
> > +#define   PIPEDMC_SCANLINE_UPPER(scanline)
> > 	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
> > +
> > +#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
> > +			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
> > +			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
> > +	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
> > +				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
> > +				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
> > +				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
> > +				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
> > +
> > +#define _PIPEDMC_FPQ1_HP_A		0x5f128
> > +#define _PIPEDMC_FPQ2_HP_A		0x5f138
> > +#define _PIPEDMC_FPQ3_HP_A		0x5f168
> > +#define _PIPEDMC_FPQ4_HP_A		0x5f174
> > +#define _PIPEDMC_FPQ5_HP_A		0x5f180
> > +#define _PIPEDMC_FPQ1_HP_B		0x5f528
> > +#define _PIPEDMC_FPQ2_HP_B		0x5f538
> > +#define _PIPEDMC_FPQ3_HP_B		0x5f568
> > +#define _PIPEDMC_FPQ4_HP_B		0x5f574
> > +#define _PIPEDMC_FPQ5_HP_B		0x5f580
> 
> This entry 5 is not used, is it intentional ?

We don't need it for the macro since it's (fortunately)
at a suitable offset from the previous entry. It's also
for the "fast queue" which isn't used, so technically could
just nuke it. But since the firmware still has all the code
for it I figured I might as well document them all.

> 
> > +#define PIPEDMC_FPQ_HP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> > +
> > _PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
> > +
> > _PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
> > +
> > _PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
> > +
> > _PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
> > +
> > +#define _PIPEDMC_FPQ1_TP_A		0x5f12c
> > +#define _PIPEDMC_FPQ2_TP_A		0x5f13c
> > +#define _PIPEDMC_FPQ3_TP_A		0x5f16c
> > +#define _PIPEDMC_FPQ4_TP_A		0x5f178
> > +#define _PIPEDMC_FPQ5_TP_A		0x5f184
> > +#define _PIPEDMC_FPQ1_TP_B		0x5f52c
> > +#define _PIPEDMC_FPQ2_TP_B		0x5f53c
> > +#define _PIPEDMC_FPQ3_TP_B		0x5f56c
> > +#define _PIPEDMC_FPQ4_TP_B		0x5f578
> > +#define _PIPEDMC_FPQ5_TP_B		0x5f584
> > +#define PIPEDMC_FPQ_TP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> > +
> > _PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
> > +
> > _PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
> > +
> > _PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
> > +
> > _PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
> > +
> > +#define _PIPEDMC_FPQ1_CHP_A		0x5f130
> > +#define _PIPEDMC_FPQ2_CHP_A		0x5f140
> > +#define _PIPEDMC_FPQ3_CHP_A		0x5f170
> > +#define _PIPEDMC_FPQ4_CHP_A		0x5f17c
> > +#define _PIPEDMC_FPQ5_CHP_A		0x5f188
> > +#define _PIPEDMC_FPQ1_CHP_B		0x5f530
> > +#define _PIPEDMC_FPQ2_CHP_B		0x5f540
> > +#define _PIPEDMC_FPQ3_CHP_B		0x5f570
> > +#define _PIPEDMC_FPQ4_CHP_B		0x5f57c
> > +#define _PIPEDMC_FPQ5_CHP_B		0x5f588
> > +#define PIPEDMC_FPQ_CHP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe), (fq_id), \
> > +
> > _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
> > +
> > _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
> > +
> > _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
> > +
> > _PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
> > +
> > +#define _PIPEDMC_FPQ_TS_A		0x5f134
> > +#define _PIPEDMC_FPQ_TS_B		0x5f534
> > +#define PIPEDMC_FPQ_TS(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
> > +
> > +#define _PIPEDMC_SCANLINE_RO_A		0x5f144
> > +#define _PIPEDMC_SCANLINE_RO_B		0x5f544
> > +#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe),
> > _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
> > +
> > +#define _PIPEDMC_FPQ_CTL1_A		0x5f160
> > +#define _PIPEDMC_FPQ_CTL1_B		0x5f560
> > +#define PIPEDMC_FPQ_CTL1(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
> > +#define   PIPEDMC_SW_DMC_WAKE		REG_BIT(0)
> > +
> > +#define _PIPEDMC_FPQ_CTL2_A		0x5f164
> > +#define _PIPEDMC_FPQ_CTL2_B		0x5f564
> > +#define PIPEDMC_FPQ_CTL2(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
> > +#define   PIPEDMC_DMC_INT_AT_DELAYED_VBLANK	REG_BIT(1)
> > +#define   PIPEDMC_W1_DMC_WAKE			REG_BIT(0)
> > +
> >  #define _PIPEDMC_INTERRUPT_A		0x5f190 /* lnl+ */
> >  #define _PIPEDMC_INTERRUPT_B		0x5f590 /* lnl+ */
> >  #define PIPEDMC_INTERRUPT(pipe)		_MMIO_PIPE((pipe),
> > _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B)
> > @@ -394,4 +538,30 @@ enum pipedmc_event_id {
> >  #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
> >  #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
> > 
> > +#define DMC_FQ_W2_PTS_CFG_SEL	_MMIO(0x8f240)
> > +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK
> > 	REG_GENMASK(25, 24)
> 
> This is extended to 3 bit 24:26, please check once.

Doesn't really matter for now as we don't have that many pipes,
but might as well use the wider masks I guess.

> 
> > +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > 	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > (pipe))
> > +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK
> > 	REG_GENMASK(17, 16)
> 
> This as well, 16:18
> 
> > +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > 	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > (pipe))
> > +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK
> > 	REG_GENMASK(9, 8)
> 
> This is 8:10
> 
> > +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > 	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > (pipe))
> > +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK
> > 	REG_GENMASK(1, 0)
> 
> This is 0:2.
> 
> > +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > 	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > (pipe))
> > +
> > +/* planel/general flip queue entries */
> > +#define PIPEDMC_FQ_RAM(start_mmioaddr, i)	_MMIO((start_mmioaddr) + (i)
> > * 4)
> > +/* DW0 pts */
> > +/* DW1 head */
> > +/* DW2 size/etc. */
> > +#define FQ_INTERRUPT		REG_BIT(31)
> > +#define FQ_DSB_ID_MASK		REG_GENMASK(30, 29)
> > +#define FQ_DSB_ID(dsb_id)	REG_FIELD_PREP(FQ_DSB_ID_MASK, (dsb_id))
> > +#define FQ_EXECUTED		REG_BIT(28)
> > +#define FQ_DSB_SIZE_MASK	REG_GENMASK(15, 0)
> > +#define FQ_DSB_SIZE(size)	REG_FIELD_PREP(FQ_DSB_SIZE_MASK, (size))
> > +/* DW3 reserved (plane queues) */
> > +/* DW3 second DSB head (general queue) */
> > +/* DW4 second DSB size/etc. (general queue) */
> > +/* DW5 reserved (general queue) */
> > +
> >  #endif /* __INTEL_DMC_REGS_H__ */
> > --
> > 2.49.0
> 

-- 
Ville Syrjälä
Intel

RE: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC registers

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, May 21, 2025 11:14 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 06/12] drm/i915/dmc: Define flip queue related PIPEDMC
> registers
> 
> On Sun, May 18, 2025 at 07:41:06PM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> > > Ville Syrjala
> > > Sent: Friday, May 16, 2025 5:04 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: intel-xe@lists.freedesktop.org
> > > Subject: [PATCH 06/12] drm/i915/dmc: Define flip queue related
> > > PIPEDMC registers
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Add the register definitions for a bunch of flip queue related PIPEDMC
> registers.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172
> > > +++++++++++++++++-
> > >  1 file changed, 171 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > index d8e715677454..613160a1f9f2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> > > @@ -6,7 +6,7 @@
> > >  #ifndef __INTEL_DMC_REGS_H__
> > >  #define __INTEL_DMC_REGS_H__
> > >
> > > -#include "i915_reg_defs.h"
> > > +#include "intel_display_reg_defs.h"
> > >
> > >  enum dmc_event_id {
> > >  	DMC_EVENT_TRUE = 0x0,
> > > @@ -287,6 +287,17 @@ enum pipedmc_event_id {
> > >  #define MTL_PIPEDMC_CONTROL		_MMIO(0x45250)
> > >  #define  PIPEDMC_ENABLE_MTL(pipe)	REG_BIT(((pipe) - PIPE_A) * 4)
> > >
> > > +#define _PIPEDMC_LOAD_HTP_A		0x5f000
> > > +#define _PIPEDMC_LOAD_HTP_B		0x5f400
> > > +#define PIPEDMC_LOAD_HTP(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_LOAD_HTP_A, _PIPEDMC_LOAD_HTP_B)
> > > +
> > > +#define _PIPEDMC_CTL_A		0x5f064
> > > +#define _PIPEDMC_CTL_B		0x5f464
> > > +#define PIPEDMC_CTL(pipe)		_MMIO_PIPE((pipe),
> _PIPEDMC_CTL_A,
> > > _PIPEDMC_CTL_B)
> > > +#define   PIPEDMC_HALT			REG_BIT(31)
> > > +#define   PIPEDMC_STEP			REG_BIT(27)
> > > +#define   PIPEDMC_CLOCKGATE		REG_BIT(23)
> > > +
> > >  #define _PIPEDMC_STATUS_A		0x5f06c
> > >  #define _PIPEDMC_STATUS_B		0x5f46c
> > >  #define PIPEDMC_STATUS(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_STATUS_A, _PIPEDMC_STATUS_B) @@ -298,6 +309,139 @@
> enum
> > > pipedmc_event_id {
> > >  #define   PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE
> > > 	REG_FIELD_PREP(PIPEDMC_INT_VECTOR_MASK, 0xff) /*
> > > Wa_16018781658:lnl[a0] */
> > >  #define   PIPEDMC_EVT_PENDING		REG_GENMASK(7, 0)
> > >
> > > +#define _PIPEDMC_FQ_CTRL_A		0x5f078
> > > +#define _PIPEDMC_FQ_CTRL_B		0x5f478
> > > +#define PIPEDMC_FQ_CTRL(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FQ_CTRL_A, _PIPEDMC_FQ_CTRL_B)
> > > +#define   PIPEDMC_FQ_CTRL_ENABLE	REG_BIT(31)
> > > +#define   PIPEDMC_FQ_CTRL_BUSY		REG_BIT(30)
> > > +#define   PIPEDMC_FQ_CTRL_ASYNC		REG_BIT(29)
> > > +#define   PIPEDMC_FQ_CTRL_PREEMPT	REG_BIT(0)
> > > +
> > > +#define _PIPEDMC_FQ_STATUS_A		0x5f098
> > > +#define _PIPEDMC_FQ_STATUS_B		0x5f498
> > > +#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)
> > > +#define   PIPEDMC_FQ_STATUS_BUSY		REG_BIT(31)
> > > +#define   PIPEDMC_FQ_STATUS_W2_LIVE_STATUS	REG_BIT(1)
> > > +#define   PIPEDMC_FQ_STATUS_W1_LIVE_STATUS	REG_BIT(0)
> > > +
> > > +#define _PIPEDMC_FPQ_ATOMIC_TP_A	0x5f0a0
> > > +#define _PIPEDMC_FPQ_ATOMIC_TP_B	0x5f4a0
> > > +#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)
> > > +#define   PIPEDMC_FPQ_PLANEQ_3_TP_MASK	REG_GENMASK(31, 26)
> > > +#define   PIPEDMC_FPQ_PLANEQ_3_TP(tail)
> > > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, (tail))
> > > +#define   PIPEDMC_FPQ_PLANEQ_2_TP_MASK	REG_GENMASK(24, 19)
> > > +#define   PIPEDMC_FPQ_PLANEQ_2_TP(tail)
> > > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, (tail))
> > > +#define   PIPEDMC_FPQ_PLANEQ_1_TP_MASK	REG_GENMASK(17, 12)
> > > +#define   PIPEDMC_FPQ_PLANEQ_1_TP(tail)
> > > 	REG_FIELD_PREP(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, (tail))
> > > +#define   PIPEDMC_FPQ_FASTQ_TP_MASK	REG_GENMASK(10, 6)
> > > +#define   PIPEDMC_FPQ_FASTQ_TP(tail)
> > > 	REG_FIELD_PREP(PIPEDMC_FPQ_FASTQ_TP_MASK, (tail))
> > > +#define   PIPEDMC_FPQ_GENERALQ_TP_MASK	REG_GENMASK(4, 0)
> > > +#define   PIPEDMC_FPQ_GENERALQ_TP(tail)
> > > 	REG_FIELD_PREP(PIPEDMC_FPQ_GENERALQ_TP_MASK, (tail))
> > > +
> > > +#define _PIPEDMC_FPQ_LINES_TO_W1_A	0x5f0a4
> > > +#define _PIPEDMC_FPQ_LINES_TO_W1_B	0x5f4a4
> > > +#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)
> > > +
> > > +#define _PIPEDMC_FPQ_LINES_TO_W2_A	0x5f0a8
> > > +#define _PIPEDMC_FPQ_LINES_TO_W2_B	0x5f4a8
> > > +#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)
> > > +
> > > +#define _PIPEDMC_SCANLINECMP_A		0x5f11c
> > > +#define _PIPEDMC_SCANLINECMP_B		0x5f51c
> > > +#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe),
> > > _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)
> > > +#define   PIPEDMC_SCANLINECMP_EN	REG_BIT(31)
> > > +#define   PIPEDMC_SCANLINE_NUMBER	REG_GENMASK(27, 0)
> >
> > The scanline number seems to be 0:20 for LNL/PTL, can you please
> > re-check once. It's extended to 27 for later platforms.
> 
> The later stuff seems uncertain, so I'll drop these to 21 bits for now.

Sure

> >
> > > +#define _PIPEDMC_SCANLINECMPLOWER_A	0x5f120
> > > +#define _PIPEDMC_SCANLINECMPLOWER_B	0x5f520
> > > +#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe),
> > > _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)
> > > +#define   PIPEDMC_SCANLINEINRANGECMP_EN		REG_BIT(31)
> > > +#define   PIPEDMC_SCANLINEOUTRANGECMP_EN	REG_BIT(30)
> > > +#define   PIPEDMC_SCANLINE_LOWER_MASK
> 	REG_GENMASK(27, 0)
> >
> > This as well.
> >
> > > +#define   PIPEDMC_SCANLINE_LOWER(scanline)
> > > 	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))
> > > +
> > > +#define _PIPEDMC_SCANLINECMPUPPER_A	0x5f124
> > > +#define _PIPEDMC_SCANLINECMPUPPER_B	0x5f524
> > > +#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe),
> > > _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)
> > > +#define   PIPEDMC_SCANLINE_UPPER_MASK	REG_GENMASK(27, 0)
> >
> > Same as above.
> >
> > > +#define   PIPEDMC_SCANLINE_UPPER(scanline)
> > > 	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))
> > > +
> > > +#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
> > > +			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
> > > +			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
> > > +	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
> > > +				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
> > > +				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
> > > +				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
> > > +				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))
> > > +
> > > +#define _PIPEDMC_FPQ1_HP_A		0x5f128
> > > +#define _PIPEDMC_FPQ2_HP_A		0x5f138
> > > +#define _PIPEDMC_FPQ3_HP_A		0x5f168
> > > +#define _PIPEDMC_FPQ4_HP_A		0x5f174
> > > +#define _PIPEDMC_FPQ5_HP_A		0x5f180
> > > +#define _PIPEDMC_FPQ1_HP_B		0x5f528
> > > +#define _PIPEDMC_FPQ2_HP_B		0x5f538
> > > +#define _PIPEDMC_FPQ3_HP_B		0x5f568
> > > +#define _PIPEDMC_FPQ4_HP_B		0x5f574
> > > +#define _PIPEDMC_FPQ5_HP_B		0x5f580
> >
> > This entry 5 is not used, is it intentional ?
> 
> We don't need it for the macro since it's (fortunately) at a suitable offset from the
> previous entry. It's also for the "fast queue" which isn't used, so technically could
> just nuke it. But since the firmware still has all the code for it I figured I might as
> well document them all.

Ok, will leave to your discretion.

> >
> > > +#define PIPEDMC_FPQ_HP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe),
> (fq_id), \
> > > +
> > > _PIPEDMC_FPQ1_HP_A, _PIPEDMC_FPQ2_HP_A, \
> > > +
> > > _PIPEDMC_FPQ3_HP_A, _PIPEDMC_FPQ4_HP_A, \
> > > +
> > > _PIPEDMC_FPQ1_HP_B, _PIPEDMC_FPQ2_HP_B, \
> > > +
> > > _PIPEDMC_FPQ3_HP_B, _PIPEDMC_FPQ4_HP_B)
> > > +
> > > +#define _PIPEDMC_FPQ1_TP_A		0x5f12c
> > > +#define _PIPEDMC_FPQ2_TP_A		0x5f13c
> > > +#define _PIPEDMC_FPQ3_TP_A		0x5f16c
> > > +#define _PIPEDMC_FPQ4_TP_A		0x5f178
> > > +#define _PIPEDMC_FPQ5_TP_A		0x5f184
> > > +#define _PIPEDMC_FPQ1_TP_B		0x5f52c
> > > +#define _PIPEDMC_FPQ2_TP_B		0x5f53c
> > > +#define _PIPEDMC_FPQ3_TP_B		0x5f56c
> > > +#define _PIPEDMC_FPQ4_TP_B		0x5f578
> > > +#define _PIPEDMC_FPQ5_TP_B		0x5f584
> > > +#define PIPEDMC_FPQ_TP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe),
> (fq_id), \
> > > +
> > > _PIPEDMC_FPQ1_TP_A, _PIPEDMC_FPQ2_TP_A, \
> > > +
> > > _PIPEDMC_FPQ3_TP_A, _PIPEDMC_FPQ4_TP_A, \
> > > +
> > > _PIPEDMC_FPQ1_TP_B, _PIPEDMC_FPQ2_TP_B, \
> > > +
> > > _PIPEDMC_FPQ3_TP_B, _PIPEDMC_FPQ4_TP_B)
> > > +
> > > +#define _PIPEDMC_FPQ1_CHP_A		0x5f130
> > > +#define _PIPEDMC_FPQ2_CHP_A		0x5f140
> > > +#define _PIPEDMC_FPQ3_CHP_A		0x5f170
> > > +#define _PIPEDMC_FPQ4_CHP_A		0x5f17c
> > > +#define _PIPEDMC_FPQ5_CHP_A		0x5f188
> > > +#define _PIPEDMC_FPQ1_CHP_B		0x5f530
> > > +#define _PIPEDMC_FPQ2_CHP_B		0x5f540
> > > +#define _PIPEDMC_FPQ3_CHP_B		0x5f570
> > > +#define _PIPEDMC_FPQ4_CHP_B		0x5f57c
> > > +#define _PIPEDMC_FPQ5_CHP_B		0x5f588
> > > +#define PIPEDMC_FPQ_CHP(pipe, fq_id)	_MMIO_PIPEDMC_FPQ((pipe),
> (fq_id), \
> > > +
> > > _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \
> > > +
> > > _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \
> > > +
> > > _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \
> > > +
> > > _PIPEDMC_FPQ3_CHP_B, _PIPEDMC_FPQ4_CHP_B)
> > > +
> > > +#define _PIPEDMC_FPQ_TS_A		0x5f134
> > > +#define _PIPEDMC_FPQ_TS_B		0x5f534
> > > +#define PIPEDMC_FPQ_TS(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_TS_A, _PIPEDMC_FPQ_TS_B)
> > > +
> > > +#define _PIPEDMC_SCANLINE_RO_A		0x5f144
> > > +#define _PIPEDMC_SCANLINE_RO_B		0x5f544
> > > +#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe),
> > > _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)
> > > +
> > > +#define _PIPEDMC_FPQ_CTL1_A		0x5f160
> > > +#define _PIPEDMC_FPQ_CTL1_B		0x5f560
> > > +#define PIPEDMC_FPQ_CTL1(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_CTL1_A, _PIPEDMC_FPQ_CTL1_B)
> > > +#define   PIPEDMC_SW_DMC_WAKE		REG_BIT(0)
> > > +
> > > +#define _PIPEDMC_FPQ_CTL2_A		0x5f164
> > > +#define _PIPEDMC_FPQ_CTL2_B		0x5f564
> > > +#define PIPEDMC_FPQ_CTL2(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_FPQ_CTL2_A, _PIPEDMC_FPQ_CTL2_B)
> > > +#define   PIPEDMC_DMC_INT_AT_DELAYED_VBLANK	REG_BIT(1)
> > > +#define   PIPEDMC_W1_DMC_WAKE			REG_BIT(0)
> > > +
> > >  #define _PIPEDMC_INTERRUPT_A		0x5f190 /* lnl+ */
> > >  #define _PIPEDMC_INTERRUPT_B		0x5f590 /* lnl+ */
> > >  #define PIPEDMC_INTERRUPT(pipe)		_MMIO_PIPE((pipe),
> > > _PIPEDMC_INTERRUPT_A, _PIPEDMC_INTERRUPT_B) @@ -394,4 +538,30
> @@
> > > enum pipedmc_event_id {
> > >  #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
> > >  #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
> > >
> > > +#define DMC_FQ_W2_PTS_CFG_SEL	_MMIO(0x8f240)
> > > +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK
> > > 	REG_GENMASK(25, 24)
> >
> > This is extended to 3 bit 24:26, please check once.
> 
> Doesn't really matter for now as we don't have that many pipes, but might as well
> use the wider masks I guess.

Yeah, would be good to extend these.

Regards,
Uma Shankar

> >
> > > +#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > > 	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > > (pipe))
> > > +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK
> > > 	REG_GENMASK(17, 16)
> >
> > This as well, 16:18
> >
> > > +#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > > 	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > > (pipe))
> > > +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK
> > > 	REG_GENMASK(9, 8)
> >
> > This is 8:10
> >
> > > +#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > > 	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > > (pipe))
> > > +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK
> > > 	REG_GENMASK(1, 0)
> >
> > This is 0:2.
> >
> > > +#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)
> > > 	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK,
> > > (pipe))
> > > +
> > > +/* planel/general flip queue entries */
> > > +#define PIPEDMC_FQ_RAM(start_mmioaddr, i)
> 	_MMIO((start_mmioaddr) + (i)
> > > * 4)
> > > +/* DW0 pts */
> > > +/* DW1 head */
> > > +/* DW2 size/etc. */
> > > +#define FQ_INTERRUPT		REG_BIT(31)
> > > +#define FQ_DSB_ID_MASK		REG_GENMASK(30, 29)
> > > +#define FQ_DSB_ID(dsb_id)	REG_FIELD_PREP(FQ_DSB_ID_MASK, (dsb_id))
> > > +#define FQ_EXECUTED		REG_BIT(28)
> > > +#define FQ_DSB_SIZE_MASK	REG_GENMASK(15, 0)
> > > +#define FQ_DSB_SIZE(size)	REG_FIELD_PREP(FQ_DSB_SIZE_MASK, (size))
> > > +/* DW3 reserved (plane queues) */
> > > +/* DW3 second DSB head (general queue) */
> > > +/* DW4 second DSB size/etc. (general queue) */
> > > +/* DW5 reserved (general queue) */
> > > +
> > >  #endif /* __INTEL_DMC_REGS_H__ */
> > > --
> > > 2.49.0
> >
> 
> --
> Ville Syrjälä
> Intel

[PATCH 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Provide the lower level code for PIPEDMC based flip queue.

We'll use the so called semi-full flip queue mode where the
PIPEDMC will start the provided DSB on a scanline a little
ahead of the vblank. We need to program the triggering scanline
early enough so that the DSB has enough time to complete writing
all the double buffered registers before they get latched (at
start of vblank).

The firmware implements several queues:
- 3 "plane queues" which execute a single DSB per entry
- 1 "general queue" which can apparently execute 2 DSBs per entry
- 1 vestigial "fast queue" that replaced the "simple flip queue"
  on ADL+, but this isn't supposed to be used due to issues.

But we only need a single plane queue really, and we won't actually
use it as a real queue because we don't allow queueing multiple commits
ahead of time. So the whole thing is perhaps useless. I suppose
there migth be some power saving benefits if we would get the flip
scheduled by userspace early and then could keep some hardware powered
off a bit longer until the DMC kicks off the flipq programming. But that
is pure speculation at this time and needs to be proven.

The code to hook up the flip queue into the actual atomic commit
path will follow later.

TODO: need to think how to do the "wait for DMC firmware load" nicely
      need to think what to about the cdclk dependency on the execution time
      need to think about VRR and PSR
      etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../drm/i915/display/intel_display_driver.c   |   3 +
 .../drm/i915/display/intel_display_types.h    |  17 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  51 +++
 drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
 drivers/gpu/drm/i915/display/intel_dsb.c      |   1 +
 drivers/gpu/drm/i915/display/intel_flipq.c    | 306 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_flipq.h    |  33 ++
 drivers/gpu/drm/xe/Makefile                   |   1 +
 9 files changed, 424 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a90eb1f180a..20ac3b2bdb81 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -266,6 +266,7 @@ i915-y += \
 	display/intel_fbc.o \
 	display/intel_fdi.o \
 	display/intel_fifo_underrun.o \
+	display/intel_flipq.o \
 	display/intel_frontbuffer.o \
 	display/intel_global_state.o \
 	display/intel_hdcp.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 5c74ab5fd1aa..1c4751cf1d27 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -43,6 +43,7 @@
 #include "intel_fbc.h"
 #include "intel_fbdev.h"
 #include "intel_fdi.h"
+#include "intel_flipq.h"
 #include "intel_gmbus.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
@@ -506,6 +507,8 @@ int intel_display_driver_probe(struct intel_display *display)
 	 */
 	intel_hdcp_component_init(display);
 
+	intel_flipq_init(display);
+
 	/*
 	 * Force all active planes to recompute their states. So that on
 	 * mode_setcrtc after probe, all the intel_plane_state variables
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 056219272c36..2f3fdf292d88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1365,6 +1365,21 @@ struct intel_pipe_crc {
 	enum intel_pipe_crc_source source;
 };
 
+enum intel_flipq_id {
+	INTEL_FLIPQ_PLANE_1,
+	INTEL_FLIPQ_PLANE_2,
+	INTEL_FLIPQ_PLANE_3,
+	INTEL_FLIPQ_GENERAL,
+	INTEL_FLIPQ_FAST,
+	MAX_INTEL_FLIPQ,
+};
+
+struct intel_flipq {
+	u32 start_mmioaddr;
+	enum intel_flipq_id flipq_id;
+	u8 tail;
+};
+
 struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
@@ -1396,6 +1411,8 @@ struct intel_crtc {
 	bool cpu_fifo_underrun_disabled;
 	bool pch_fifo_underrun_disabled;
 
+	struct intel_flipq flipq[MAX_INTEL_FLIPQ];
+
 	/* per-pipe watermark state */
 	struct {
 		/* watermarks currently being used  */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index a7ba17361d63..7b28da58faec 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -24,16 +24,19 @@
 
 #include <linux/debugfs.h>
 #include <linux/firmware.h>
+#include <drm/drm_vblank.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_display_types.h"
 #include "intel_display_rpm.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
+#include "intel_flipq.h"
 #include "intel_step.h"
 
 /**
@@ -511,6 +514,8 @@ void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
 		return;
 
 	if (DISPLAY_VER(display) >= 20) {
+		intel_flipq_reset(display, pipe);
+
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
 		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
 	}
@@ -536,6 +541,8 @@ void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
 	if (DISPLAY_VER(display) >= 20) {
 		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
+
+		intel_flipq_reset(display, pipe);
 	}
 }
 
@@ -715,6 +722,12 @@ void intel_dmc_load_program(struct intel_display *display)
 		}
 	}
 
+	intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
+		       PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) |
+		       PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) |
+		       PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |
+		       PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
+
 	power_domains->dc_state = 0;
 
 	gen9_set_dc_state_debugmask(display);
@@ -1243,6 +1256,17 @@ void intel_dmc_suspend(struct intel_display *display)
 		intel_dmc_runtime_pm_put(display);
 }
 
+void intel_dmc_wait_fw_load(struct intel_display *display)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+
+	if (!HAS_DMC(display))
+		return;
+
+	if (dmc)
+		flush_work(&dmc->work);
+}
+
 /**
  * intel_dmc_resume() - init DMC firmware during system resume
  * @display: display instance
@@ -1478,3 +1502,30 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
 			crtc->base.base.id, crtc->base.name, tmp);
 }
+
+void intel_pipedmc_enable_event(struct intel_crtc *crtc,
+				enum pipedmc_event_id event)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	dmc_configure_event(display, dmc_id, event, true);
+}
+
+void intel_pipedmc_disable_event(struct intel_crtc *crtc,
+				 enum pipedmc_event_id event)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	dmc_configure_event(display, dmc_id, event, false);
+}
+
+u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_dmc *dmc = display_to_dmc(display);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	return dmc->dmc_info[dmc_id].start_mmioaddr;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index a98e8deff13a..b94aa2e7e50c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -9,12 +9,15 @@
 #include <linux/types.h>
 
 enum pipe;
+enum pipedmc_event_id;
 struct drm_printer;
+struct intel_crtc;
 struct intel_display;
 struct intel_dmc_snapshot;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
+void intel_dmc_wait_fw_load(struct intel_display *display);
 void intel_dmc_disable_program(struct intel_display *display);
 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);
 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
@@ -36,4 +39,12 @@ void assert_dmc_loaded(struct intel_display *display);
 
 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
 
+u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
+void intel_pipedmc_enable_event(struct intel_crtc *crtc,
+				enum pipedmc_event_id event);
+void intel_pipedmc_disable_event(struct intel_crtc *crtc,
+				 enum pipedmc_event_id event);
+
+void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+
 #endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 82cb58cf9c6a..8f022adfea18 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -13,6 +13,7 @@
 #include "intel_de.h"
 #include "intel_display_rpm.h"
 #include "intel_display_types.h"
+#include "intel_dmc_regs.h"
 #include "intel_dsb.h"
 #include "intel_dsb_buffer.h"
 #include "intel_dsb_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
new file mode 100644
index 000000000000..8677929b7ece
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/pci.h>
+
+#include <drm/drm_print.h>
+
+#include "i915_utils.h"
+#include "intel_step.h"
+#include "intel_crtc.h"
+#include "intel_de.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "intel_flipq.h"
+#include "intel_dmc.h"
+#include "intel_dmc_regs.h"
+#include "intel_dsb.h"
+#include "intel_vblank.h"
+
+#define for_each_flipq(flipq_id) \
+	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ; (flipq_id)++)
+
+static int intel_flipq_offset(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+		return 0x008;
+	case INTEL_FLIPQ_PLANE_2:
+		return 0x108;
+	case INTEL_FLIPQ_PLANE_3:
+		return 0x208;
+	case INTEL_FLIPQ_GENERAL:
+		return 0x308;
+	case INTEL_FLIPQ_FAST:
+		return 0x3c8;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_size_dw(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		return 64;
+	case INTEL_FLIPQ_GENERAL:
+	case INTEL_FLIPQ_FAST:
+		return 48;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_elem_size_dw(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		return 4;
+	case INTEL_FLIPQ_GENERAL:
+	case INTEL_FLIPQ_FAST:
+		return 6;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_size_entries(enum intel_flipq_id flipq_id)
+{
+	return intel_flipq_size_dw(flipq_id) / intel_flipq_elem_size_dw(flipq_id);
+}
+
+static void intel_flipq_crtc_init(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_flipq_id flipq_id;
+
+	for_each_flipq(flipq_id) {
+		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+
+		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id);
+		flipq->flipq_id = flipq_id;
+
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] flip queue %d: start 0x%x\n",
+			    crtc->base.base.id, crtc->base.name,
+			    flipq_id, flipq->start_mmioaddr);
+	}
+}
+
+void intel_flipq_init(struct intel_display *display)
+{
+	struct intel_crtc *crtc;
+
+	intel_dmc_wait_fw_load(display);
+
+	for_each_intel_crtc(display->drm, crtc)
+		intel_flipq_crtc_init(crtc);
+}
+
+static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	drm_dbg_kms(display->drm, "preempt %d\n", preempt);
+
+	intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),
+		     PIPEDMC_FQ_CTRL_PREEMPT, preempt ? PIPEDMC_FQ_CTRL_PREEMPT : 0);
+	/* FIXME what timeout? */
+	if (preempt &&
+	    intel_de_wait_for_clear(display, PIPEDMC_FQ_CTRL(crtc->pipe),
+				    PIPEDMC_FQ_CTRL_BUSY, 10))
+		drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",
+			crtc->base.base.id, crtc->base.name);
+}
+
+static int intel_flipq_current_head(struct intel_crtc *crtc, enum intel_flipq_id flipq_id)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
+}
+
+static void intel_flipq_write_tail(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),
+		       PIPEDMC_FPQ_PLANEQ_3_TP(crtc->flipq[INTEL_FLIPQ_PLANE_3].tail) |
+		       PIPEDMC_FPQ_PLANEQ_2_TP(crtc->flipq[INTEL_FLIPQ_PLANE_2].tail) |
+		       PIPEDMC_FPQ_PLANEQ_1_TP(crtc->flipq[INTEL_FLIPQ_PLANE_1].tail) |
+		       PIPEDMC_FPQ_FASTQ_TP(crtc->flipq[INTEL_FLIPQ_FAST].tail) |
+		       PIPEDMC_FPQ_GENERALQ_TP(crtc->flipq[INTEL_FLIPQ_GENERAL].tail));
+}
+
+static void intel_flipq_sw_dmc_wake(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);
+}
+
+static int cdclk_factor(struct intel_display *display)
+{
+	if (DISPLAY_VER(display) >= 30)
+		return 120;
+	else
+		return 280;
+}
+
+static int intel_flipq_exec_time_us(struct intel_display *display)
+{
+	/* TODO ask the DSB code what this should be */
+	int dsb_exec_time = 20;
+	/* FIXME how to deal with cdclk changes? */
+	int cdclk_freq = 200000;
+
+	return dsb_exec_time + 540000 / cdclk_freq * cdclk_factor(display) +
+		display->sagv.block_time_us;
+}
+
+static int intel_flipq_exec_time_lines(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+					intel_flipq_exec_time_us(display));
+}
+
+void intel_flipq_reset(struct intel_display *display, enum pipe pipe)
+{
+	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
+	enum intel_flipq_id flipq_id;
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);
+
+	for_each_flipq(flipq_id) {
+		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+
+		intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);
+		intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);
+
+		flipq->tail = 0;
+	}
+
+	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);
+}
+
+void intel_flipq_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	/* FIXME what to do with VRR? */
+	int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode) -
+		intel_flipq_exec_time_lines(crtc_state);
+
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] flipq queue scanlined %d-%d\n",
+		    crtc->base.base.id, crtc->base.name, scanline - 2, scanline);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),
+		       PIPEDMC_SCANLINEINRANGECMP_EN |
+		       PIPEDMC_SCANLINE_LOWER(scanline - 2));
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),
+		       PIPEDMC_SCANLINE_UPPER(scanline));
+
+	intel_pipedmc_enable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);
+}
+
+void intel_flipq_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
+
+	intel_pipedmc_disable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);
+}
+
+static bool assert_flipq_has_room(struct intel_crtc *crtc,
+				  enum intel_flipq_id flipq_id)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+	int head, size = intel_flipq_size_entries(flipq_id);
+
+	head = intel_flipq_current_head(crtc, flipq_id);
+
+	return !drm_WARN(display->drm,
+			 (flipq->tail + size - head) % size >= size - 1,
+			 "[CRTC:%d:%s] FLIPQ %d overflow (head %d, tail %d, size %d)\n",
+			 crtc->base.base.id, crtc->base.name, flipq_id,
+			 head, flipq->tail, size);
+}
+
+static void intel_flipq_write(struct intel_display *display,
+			      struct intel_flipq *flipq, u32 data, int i)
+{
+	intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail *
+					       intel_flipq_elem_size_dw(flipq->flipq_id) + i), data);
+}
+
+void intel_flipq_add(struct intel_crtc *crtc,
+		     enum intel_flipq_id flipq_id,
+		     unsigned int pts,
+		     enum intel_dsb_id dsb_id,
+		     struct intel_dsb *dsb)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+	int i = 0;
+
+	if (!assert_flipq_has_room(crtc, flipq_id))
+		return;
+
+	pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
+
+	intel_flipq_preempt(crtc, true);
+
+	switch (flipq_id) {
+	case INTEL_FLIPQ_GENERAL:
+		intel_flipq_write(display, flipq, pts, i++);
+		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
+		intel_flipq_write(display, flipq, FQ_INTERRUPT |
+				  FQ_DSB_ID(dsb_id) |
+				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
+		intel_flipq_write(display, flipq, 0, i++);
+		intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
+		intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */
+		break;
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		intel_flipq_write(display, flipq, pts, i++);
+		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
+		intel_flipq_write(display, flipq, FQ_INTERRUPT |
+				  FQ_DSB_ID(dsb_id) |
+				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
+		intel_flipq_write(display, flipq, 0, i++);
+		break;
+	default:
+		MISSING_CASE(flipq_id);
+		return;
+	}
+
+	flipq->tail = (flipq->tail + 1) % intel_flipq_size_entries(flipq->flipq_id);
+	intel_flipq_write_tail(crtc);
+
+	intel_flipq_preempt(crtc, false);
+
+	intel_flipq_sw_dmc_wake(crtc);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h b/drivers/gpu/drm/i915/display/intel_flipq.h
new file mode 100644
index 000000000000..8483c93ecdb3
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_flipq.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_FLIPQ_H__
+#define __INTEL_FLIPQ_H__
+
+#include <linux/types.h>
+
+enum intel_dsb_id;
+enum intel_flipq_id;
+enum pipe;
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_display;
+struct intel_dsb;
+
+void intel_flipq_init(struct intel_display *display);
+void intel_flipq_reset(struct intel_display *display, enum pipe pipe);
+
+void intel_flipq_enable(const struct intel_crtc_state *crtc_state);
+void intel_flipq_disable(const struct intel_crtc_state *old_crtc_state);
+
+void intel_flipq_add(struct intel_crtc *crtc,
+		     enum intel_flipq_id flip_queue_id,
+		     unsigned int pts,
+		     enum intel_dsb_id dsb_id,
+		     struct intel_dsb *dsb);
+void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb);
+void intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
+
+#endif /* __INTEL_FLIPQ_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e4bf484d4121..558d282c7b90 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -254,6 +254,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_fbc.o \
 	i915-display/intel_fdi.o \
 	i915-display/intel_fifo_underrun.o \
+	i915-display/intel_flipq.o \
 	i915-display/intel_frontbuffer.o \
 	i915-display/intel_global_state.o \
 	i915-display/intel_gmbus.o \
-- 
2.49.0

Re: [PATCH 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Jani Nikula]

On Fri, 16 May 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
> new file mode 100644
> index 000000000000..8677929b7ece
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -0,0 +1,306 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +

I'd really appreciate adding a high level comment about what flip queue
is, and maybe some words about how it's implemented, right around
here. Doesn't need to be a special DOC comment, nor does it need to be
exhaustive, and can come as a follow-up patch.

BR,
Jani.


-- 
Jani Nikula, Intel

RE: [PATCH 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip
> queue
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Provide the lower level code for PIPEDMC based flip queue.
> 
> We'll use the so called semi-full flip queue mode where the PIPEDMC will start
> the provided DSB on a scanline a little ahead of the vblank. We need to program
> the triggering scanline early enough so that the DSB has enough time to complete
> writing all the double buffered registers before they get latched (at start of
> vblank).
> 
> The firmware implements several queues:
> - 3 "plane queues" which execute a single DSB per entry
> - 1 "general queue" which can apparently execute 2 DSBs per entry
> - 1 vestigial "fast queue" that replaced the "simple flip queue"
>   on ADL+, but this isn't supposed to be used due to issues.
> 
> But we only need a single plane queue really, and we won't actually use it as a
> real queue because we don't allow queueing multiple commits ahead of time. So
> the whole thing is perhaps useless. I suppose there migth be some power saving
> benefits if we would get the flip scheduled by userspace early and then could
> keep some hardware powered off a bit longer until the DMC kicks off the flipq
> programming. But that is pure speculation at this time and needs to be proven.
> 
> The code to hook up the flip queue into the actual atomic commit path will follow
> later.
> 
> TODO: need to think how to do the "wait for DMC firmware load" nicely
>       need to think what to about the cdclk dependency on the execution time
>       need to think about VRR and PSR
>       etc.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  .../drm/i915/display/intel_display_driver.c   |   3 +
>  .../drm/i915/display/intel_display_types.h    |  17 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      |  51 +++
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
>  drivers/gpu/drm/i915/display/intel_dsb.c      |   1 +
>  drivers/gpu/drm/i915/display/intel_flipq.c    | 306 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_flipq.h    |  33 ++
>  drivers/gpu/drm/xe/Makefile                   |   1 +
>  9 files changed, 424 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1a90eb1f180a..20ac3b2bdb81 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -266,6 +266,7 @@ i915-y += \
>  	display/intel_fbc.o \
>  	display/intel_fdi.o \
>  	display/intel_fifo_underrun.o \
> +	display/intel_flipq.o \
>  	display/intel_frontbuffer.o \
>  	display/intel_global_state.o \
>  	display/intel_hdcp.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 5c74ab5fd1aa..1c4751cf1d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -43,6 +43,7 @@
>  #include "intel_fbc.h"
>  #include "intel_fbdev.h"
>  #include "intel_fdi.h"
> +#include "intel_flipq.h"
>  #include "intel_gmbus.h"
>  #include "intel_hdcp.h"
>  #include "intel_hotplug.h"
> @@ -506,6 +507,8 @@ int intel_display_driver_probe(struct intel_display
> *display)
>  	 */
>  	intel_hdcp_component_init(display);
> 
> +	intel_flipq_init(display);
> +
>  	/*
>  	 * Force all active planes to recompute their states. So that on
>  	 * mode_setcrtc after probe, all the intel_plane_state variables diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 056219272c36..2f3fdf292d88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1365,6 +1365,21 @@ struct intel_pipe_crc {
>  	enum intel_pipe_crc_source source;
>  };
> 
> +enum intel_flipq_id {
> +	INTEL_FLIPQ_PLANE_1,
> +	INTEL_FLIPQ_PLANE_2,
> +	INTEL_FLIPQ_PLANE_3,
> +	INTEL_FLIPQ_GENERAL,
> +	INTEL_FLIPQ_FAST,
> +	MAX_INTEL_FLIPQ,
> +};
> +
> +struct intel_flipq {
> +	u32 start_mmioaddr;
> +	enum intel_flipq_id flipq_id;
> +	u8 tail;
> +};
> +
>  struct intel_crtc {
>  	struct drm_crtc base;
>  	enum pipe pipe;
> @@ -1396,6 +1411,8 @@ struct intel_crtc {
>  	bool cpu_fifo_underrun_disabled;
>  	bool pch_fifo_underrun_disabled;
> 
> +	struct intel_flipq flipq[MAX_INTEL_FLIPQ];
> +
>  	/* per-pipe watermark state */
>  	struct {
>  		/* watermarks currently being used  */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index a7ba17361d63..7b28da58faec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -24,16 +24,19 @@
> 
>  #include <linux/debugfs.h>
>  #include <linux/firmware.h>
> +#include <drm/drm_vblank.h>
> 
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> +#include "intel_display_types.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_power_well.h"
>  #include "intel_display_types.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
> +#include "intel_flipq.h"
>  #include "intel_step.h"
> 
>  /**
> @@ -511,6 +514,8 @@ void intel_dmc_enable_pipe(struct intel_display *display,
> enum pipe pipe)
>  		return;
> 
>  	if (DISPLAY_VER(display) >= 20) {
> +		intel_flipq_reset(display, pipe);
> +
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe),
> pipedmc_interrupt_mask(display));
>  		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe),
> ~pipedmc_interrupt_mask(display));
>  	}
> @@ -536,6 +541,8 @@ void intel_dmc_disable_pipe(struct intel_display *display,
> enum pipe pipe)
>  	if (DISPLAY_VER(display) >= 20) {
>  		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe),
> pipedmc_interrupt_mask(display));
> +
> +		intel_flipq_reset(display, pipe);
>  	}
>  }
> 
> @@ -715,6 +722,12 @@ void intel_dmc_load_program(struct intel_display
> *display)
>  		}
>  	}
> 
> +	intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
> +		       PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) |
> +		       PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) |
> +		       PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |
> +		       PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
> +
>  	power_domains->dc_state = 0;
> 
>  	gen9_set_dc_state_debugmask(display);
> @@ -1243,6 +1256,17 @@ void intel_dmc_suspend(struct intel_display *display)
>  		intel_dmc_runtime_pm_put(display);
>  }
> 
> +void intel_dmc_wait_fw_load(struct intel_display *display) {
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +
> +	if (!HAS_DMC(display))
> +		return;
> +
> +	if (dmc)
> +		flush_work(&dmc->work);
> +}
> +
>  /**
>   * intel_dmc_resume() - init DMC firmware during system resume
>   * @display: display instance
> @@ -1478,3 +1502,30 @@ void intel_pipedmc_irq_handler(struct intel_display
> *display, enum pipe pipe)
>  		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt
> vector 0x%x\n",
>  			crtc->base.base.id, crtc->base.name, tmp);  }
> +
> +void intel_pipedmc_enable_event(struct intel_crtc *crtc,
> +				enum pipedmc_event_id event)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	dmc_configure_event(display, dmc_id, event, true); }
> +
> +void intel_pipedmc_disable_event(struct intel_crtc *crtc,
> +				 enum pipedmc_event_id event)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	dmc_configure_event(display, dmc_id, event, false); }
> +
> +u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	return dmc->dmc_info[dmc_id].start_mmioaddr;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> b/drivers/gpu/drm/i915/display/intel_dmc.h
> index a98e8deff13a..b94aa2e7e50c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -9,12 +9,15 @@
>  #include <linux/types.h>
> 
>  enum pipe;
> +enum pipedmc_event_id;
>  struct drm_printer;
> +struct intel_crtc;
>  struct intel_display;
>  struct intel_dmc_snapshot;
> 
>  void intel_dmc_init(struct intel_display *display);  void
> intel_dmc_load_program(struct intel_display *display);
> +void intel_dmc_wait_fw_load(struct intel_display *display);
>  void intel_dmc_disable_program(struct intel_display *display);  void
> intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);  void
> intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe); @@ -36,4
> +39,12 @@ void assert_dmc_loaded(struct intel_display *display);
> 
>  void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> 
> +u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc); void
> +intel_pipedmc_enable_event(struct intel_crtc *crtc,
> +				enum pipedmc_event_id event);
> +void intel_pipedmc_disable_event(struct intel_crtc *crtc,
> +				 enum pipedmc_event_id event);
> +
> +void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe
> +pipe);
> +
>  #endif /* __INTEL_DMC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 82cb58cf9c6a..8f022adfea18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -13,6 +13,7 @@
>  #include "intel_de.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_types.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dsb.h"
>  #include "intel_dsb_buffer.h"
>  #include "intel_dsb_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> new file mode 100644
> index 000000000000..8677929b7ece
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -0,0 +1,306 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */

Agree with Jani, a bit of documentation on how it works at high level
would be useful

> +#include <linux/pci.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "i915_utils.h"
> +#include "intel_step.h"
> +#include "intel_crtc.h"
> +#include "intel_de.h"
> +#include "intel_display_core.h"
> +#include "intel_display_types.h"
> +#include "intel_flipq.h"
> +#include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
> +#include "intel_dsb.h"
> +#include "intel_vblank.h"
> +
> +#define for_each_flipq(flipq_id) \
> +	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ;
> +(flipq_id)++)
> +
> +static int intel_flipq_offset(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +		return 0x008;
> +	case INTEL_FLIPQ_PLANE_2:
> +		return 0x108;
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 0x208;
> +	case INTEL_FLIPQ_GENERAL:
> +		return 0x308;
> +	case INTEL_FLIPQ_FAST:
> +		return 0x3c8;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_size_dw(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 64;
> +	case INTEL_FLIPQ_GENERAL:
> +	case INTEL_FLIPQ_FAST:
> +		return 48;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_elem_size_dw(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 4;
> +	case INTEL_FLIPQ_GENERAL:
> +	case INTEL_FLIPQ_FAST:
> +		return 6;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_size_entries(enum intel_flipq_id flipq_id) {
> +	return intel_flipq_size_dw(flipq_id) /
> +intel_flipq_elem_size_dw(flipq_id);
> +}
> +
> +static void intel_flipq_crtc_init(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_flipq_id flipq_id;
> +
> +	for_each_flipq(flipq_id) {
> +		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +
> +		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) +
> intel_flipq_offset(flipq_id);
> +		flipq->flipq_id = flipq_id;
> +
> +		drm_dbg_kms(display->drm, "[CRTC:%d:%s] flip queue %d: start
> 0x%x\n",
> +			    crtc->base.base.id, crtc->base.name,
> +			    flipq_id, flipq->start_mmioaddr);
> +	}
> +}
> +
> +void intel_flipq_init(struct intel_display *display) {
> +	struct intel_crtc *crtc;
> +
> +	intel_dmc_wait_fw_load(display);
> +
> +	for_each_intel_crtc(display->drm, crtc)
> +		intel_flipq_crtc_init(crtc);
> +}
> +
> +static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	drm_dbg_kms(display->drm, "preempt %d\n", preempt);
> +
> +	intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +		     PIPEDMC_FQ_CTRL_PREEMPT, preempt ?
> PIPEDMC_FQ_CTRL_PREEMPT : 0);
> +	/* FIXME what timeout? */

Yeah this is not defined clearly, I guess 10 should be ok.

> +	if (preempt &&
> +	    intel_de_wait_for_clear(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +				    PIPEDMC_FQ_CTRL_BUSY, 10))
> +		drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt
> timeout\n",
> +			crtc->base.base.id, crtc->base.name); }
> +
> +static int intel_flipq_current_head(struct intel_crtc *crtc, enum
> +intel_flipq_id flipq_id) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
> +}
> +
> +static void intel_flipq_write_tail(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),
> +		       PIPEDMC_FPQ_PLANEQ_3_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_3].tail) |
> +		       PIPEDMC_FPQ_PLANEQ_2_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_2].tail) |
> +		       PIPEDMC_FPQ_PLANEQ_1_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_1].tail) |
> +		       PIPEDMC_FPQ_FASTQ_TP(crtc-
> >flipq[INTEL_FLIPQ_FAST].tail) |
> +
> +PIPEDMC_FPQ_GENERALQ_TP(crtc->flipq[INTEL_FLIPQ_GENERAL].tail));
> +}
> +
> +static void intel_flipq_sw_dmc_wake(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe),
> +PIPEDMC_SW_DMC_WAKE); }
> +
> +static int cdclk_factor(struct intel_display *display) {
> +	if (DISPLAY_VER(display) >= 30)
> +		return 120;
> +	else
> +		return 280;
> +}
> +
> +static int intel_flipq_exec_time_us(struct intel_display *display) {
> +	/* TODO ask the DSB code what this should be */
> +	int dsb_exec_time = 20;

I think optimum value would be 100.
From bspec: "For the flip queue use case, the recommended DSB execution time is 100us + one SAGV block time"

> +	/* FIXME how to deal with cdclk changes? */
> +	int cdclk_freq = 200000;
> +
> +	return dsb_exec_time + 540000 / cdclk_freq * cdclk_factor(display) +
> +		display->sagv.block_time_us;
> +}
> +
> +static int intel_flipq_exec_time_lines(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> +					intel_flipq_exec_time_us(display));
> +}
> +
> +void intel_flipq_reset(struct intel_display *display, enum pipe pipe) {
> +	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> +	enum intel_flipq_id flipq_id;
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);
> +
> +	for_each_flipq(flipq_id) {
> +		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +
> +		intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);
> +		intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);
> +
> +		flipq->tail = 0;
> +	}
> +
> +	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0); }
> +
> +void intel_flipq_enable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	/* FIXME what to do with VRR? */
> +	int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode)
> -
> +		intel_flipq_exec_time_lines(crtc_state);
> +
> +	drm_dbg_kms(display->drm, "[CRTC:%d:%s] flipq queue scanlined %d-
> %d\n",
> +		    crtc->base.base.id, crtc->base.name, scanline - 2, scanline);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),
> +		       PIPEDMC_SCANLINEINRANGECMP_EN |
> +		       PIPEDMC_SCANLINE_LOWER(scanline - 2));
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),
> +		       PIPEDMC_SCANLINE_UPPER(scanline));
> +
> +	intel_pipedmc_enable_event(crtc,
> +PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +PIPEDMC_FQ_CTRL_ENABLE); }
> +
> +void intel_flipq_disable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
> +
> +	intel_pipedmc_disable_event(crtc,
> +PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0); }
> +
> +static bool assert_flipq_has_room(struct intel_crtc *crtc,
> +				  enum intel_flipq_id flipq_id)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	int head, size = intel_flipq_size_entries(flipq_id);
> +
> +	head = intel_flipq_current_head(crtc, flipq_id);
> +
> +	return !drm_WARN(display->drm,
> +			 (flipq->tail + size - head) % size >= size - 1,
> +			 "[CRTC:%d:%s] FLIPQ %d overflow (head %d, tail %d,
> size %d)\n",
> +			 crtc->base.base.id, crtc->base.name, flipq_id,
> +			 head, flipq->tail, size);
> +}
> +
> +static void intel_flipq_write(struct intel_display *display,
> +			      struct intel_flipq *flipq, u32 data, int i) {
> +	intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq-
> >tail *
> +					       intel_flipq_elem_size_dw(flipq-
> >flipq_id) + i), data); }
> +
> +void intel_flipq_add(struct intel_crtc *crtc,
> +		     enum intel_flipq_id flipq_id,
> +		     unsigned int pts,
> +		     enum intel_dsb_id dsb_id,
> +		     struct intel_dsb *dsb)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	int i = 0;
> +
> +	if (!assert_flipq_has_room(crtc, flipq_id))
> +		return;
> +
> +	pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
> +
> +	intel_flipq_preempt(crtc, true);
> +
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_GENERAL:
> +		intel_flipq_write(display, flipq, pts, i++);
> +		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
> +		intel_flipq_write(display, flipq, FQ_INTERRUPT |
> +				  FQ_DSB_ID(dsb_id) |
> +				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
> +		intel_flipq_write(display, flipq, 0, i++);
> +		intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
> +		intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for
> second DSB */
> +		break;
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		intel_flipq_write(display, flipq, pts, i++);
> +		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
> +		intel_flipq_write(display, flipq, FQ_INTERRUPT |
> +				  FQ_DSB_ID(dsb_id) |
> +				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
> +		intel_flipq_write(display, flipq, 0, i++);
> +		break;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return;
> +	}
> +
> +	flipq->tail = (flipq->tail + 1) % intel_flipq_size_entries(flipq->flipq_id);
> +	intel_flipq_write_tail(crtc);
> +
> +	intel_flipq_preempt(crtc, false);
> +
> +	intel_flipq_sw_dmc_wake(crtc);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h
> b/drivers/gpu/drm/i915/display/intel_flipq.h
> new file mode 100644
> index 000000000000..8483c93ecdb3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_FLIPQ_H__
> +#define __INTEL_FLIPQ_H__
> +
> +#include <linux/types.h>
> +
> +enum intel_dsb_id;
> +enum intel_flipq_id;
> +enum pipe;
> +struct intel_crtc;
> +struct intel_crtc_state;
> +struct intel_display;
> +struct intel_dsb;
> +
> +void intel_flipq_init(struct intel_display *display); void
> +intel_flipq_reset(struct intel_display *display, enum pipe pipe);
> +
> +void intel_flipq_enable(const struct intel_crtc_state *crtc_state);
> +void intel_flipq_disable(const struct intel_crtc_state
> +*old_crtc_state);
> +
> +void intel_flipq_add(struct intel_crtc *crtc,
> +		     enum intel_flipq_id flip_queue_id,
> +		     unsigned int pts,
> +		     enum intel_dsb_id dsb_id,
> +		     struct intel_dsb *dsb);
> +void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb); void
> +intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +
> +#endif /* __INTEL_FLIPQ_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> e4bf484d4121..558d282c7b90 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -254,6 +254,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>  	i915-display/intel_fbc.o \
>  	i915-display/intel_fdi.o \
>  	i915-display/intel_fifo_underrun.o \
> +	i915-display/intel_flipq.o \
>  	i915-display/intel_frontbuffer.o \
>  	i915-display/intel_global_state.o \
>  	i915-display/intel_gmbus.o \
> --
> 2.49.0

[PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Provide the lower level code for PIPEDMC based flip queue.

We'll use the so called semi-full flip queue mode where the
PIPEDMC will start the provided DSB on a scanline a little
ahead of the vblank. We need to program the triggering scanline
early enough so that the DSB has enough time to complete writing
all the double buffered registers before they get latched (at
start of vblank).

The firmware implements several queues:
- 3 "plane queues" which execute a single DSB per entry
- 1 "general queue" which can apparently execute 2 DSBs per entry
- 1 vestigial "fast queue" that replaced the "simple flip queue"
  on ADL+, but this isn't supposed to be used due to issues.

But we only need a single plane queue really, and we won't actually
use it as a real queue because we don't allow queueing multiple commits
ahead of time. So the whole thing is perhaps useless. I suppose
there migth be some power saving benefits if we would get the flip
scheduled by userspace early and then could keep some hardware powered
off a bit longer until the DMC kicks off the flipq programming. But that
is pure speculation at this time and needs to be proven.

The code to hook up the flip queue into the actual atomic commit
path will follow later.

TODO: need to think how to do the "wait for DMC firmware load" nicely
      need to think what to about the cdclk dependency on the execution time
      need to think about VRR and PSR
      etc.

v2: Don't write DMC_FQ_W2_PTS_CFG_SEL on pre-lnl
    Don't oops at flipq init if there is no dmc

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../drm/i915/display/intel_display_driver.c   |   3 +
 .../drm/i915/display/intel_display_types.h    |  17 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  52 +++
 drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
 drivers/gpu/drm/i915/display/intel_dsb.c      |   1 +
 drivers/gpu/drm/i915/display/intel_flipq.c    | 306 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_flipq.h    |  33 ++
 drivers/gpu/drm/xe/Makefile                   |   1 +
 9 files changed, 425 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a90eb1f180a..20ac3b2bdb81 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -266,6 +266,7 @@ i915-y += \
 	display/intel_fbc.o \
 	display/intel_fdi.o \
 	display/intel_fifo_underrun.o \
+	display/intel_flipq.o \
 	display/intel_frontbuffer.o \
 	display/intel_global_state.o \
 	display/intel_hdcp.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 5c74ab5fd1aa..1c4751cf1d27 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -43,6 +43,7 @@
 #include "intel_fbc.h"
 #include "intel_fbdev.h"
 #include "intel_fdi.h"
+#include "intel_flipq.h"
 #include "intel_gmbus.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
@@ -506,6 +507,8 @@ int intel_display_driver_probe(struct intel_display *display)
 	 */
 	intel_hdcp_component_init(display);
 
+	intel_flipq_init(display);
+
 	/*
 	 * Force all active planes to recompute their states. So that on
 	 * mode_setcrtc after probe, all the intel_plane_state variables
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 056219272c36..2f3fdf292d88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1365,6 +1365,21 @@ struct intel_pipe_crc {
 	enum intel_pipe_crc_source source;
 };
 
+enum intel_flipq_id {
+	INTEL_FLIPQ_PLANE_1,
+	INTEL_FLIPQ_PLANE_2,
+	INTEL_FLIPQ_PLANE_3,
+	INTEL_FLIPQ_GENERAL,
+	INTEL_FLIPQ_FAST,
+	MAX_INTEL_FLIPQ,
+};
+
+struct intel_flipq {
+	u32 start_mmioaddr;
+	enum intel_flipq_id flipq_id;
+	u8 tail;
+};
+
 struct intel_crtc {
 	struct drm_crtc base;
 	enum pipe pipe;
@@ -1396,6 +1411,8 @@ struct intel_crtc {
 	bool cpu_fifo_underrun_disabled;
 	bool pch_fifo_underrun_disabled;
 
+	struct intel_flipq flipq[MAX_INTEL_FLIPQ];
+
 	/* per-pipe watermark state */
 	struct {
 		/* watermarks currently being used  */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index a7ba17361d63..2ff62740833c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -24,16 +24,19 @@
 
 #include <linux/debugfs.h>
 #include <linux/firmware.h>
+#include <drm/drm_vblank.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_display_types.h"
 #include "intel_display_rpm.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
+#include "intel_flipq.h"
 #include "intel_step.h"
 
 /**
@@ -511,6 +514,8 @@ void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
 		return;
 
 	if (DISPLAY_VER(display) >= 20) {
+		intel_flipq_reset(display, pipe);
+
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
 		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
 	}
@@ -536,6 +541,8 @@ void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
 	if (DISPLAY_VER(display) >= 20) {
 		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
+
+		intel_flipq_reset(display, pipe);
 	}
 }
 
@@ -715,6 +722,13 @@ void intel_dmc_load_program(struct intel_display *display)
 		}
 	}
 
+	if (DISPLAY_VER(display) >= 20)
+		intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
+			       PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) |
+			       PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) |
+			       PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |
+			       PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
+
 	power_domains->dc_state = 0;
 
 	gen9_set_dc_state_debugmask(display);
@@ -1243,6 +1257,17 @@ void intel_dmc_suspend(struct intel_display *display)
 		intel_dmc_runtime_pm_put(display);
 }
 
+void intel_dmc_wait_fw_load(struct intel_display *display)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+
+	if (!HAS_DMC(display))
+		return;
+
+	if (dmc)
+		flush_work(&dmc->work);
+}
+
 /**
  * intel_dmc_resume() - init DMC firmware during system resume
  * @display: display instance
@@ -1478,3 +1503,30 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
 			crtc->base.base.id, crtc->base.name, tmp);
 }
+
+void intel_pipedmc_enable_event(struct intel_crtc *crtc,
+				enum pipedmc_event_id event)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	dmc_configure_event(display, dmc_id, event, true);
+}
+
+void intel_pipedmc_disable_event(struct intel_crtc *crtc,
+				 enum pipedmc_event_id event)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	dmc_configure_event(display, dmc_id, event, false);
+}
+
+u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_dmc *dmc = display_to_dmc(display);
+	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
+
+	return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index a98e8deff13a..b94aa2e7e50c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -9,12 +9,15 @@
 #include <linux/types.h>
 
 enum pipe;
+enum pipedmc_event_id;
 struct drm_printer;
+struct intel_crtc;
 struct intel_display;
 struct intel_dmc_snapshot;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
+void intel_dmc_wait_fw_load(struct intel_display *display);
 void intel_dmc_disable_program(struct intel_display *display);
 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);
 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
@@ -36,4 +39,12 @@ void assert_dmc_loaded(struct intel_display *display);
 
 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
 
+u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc);
+void intel_pipedmc_enable_event(struct intel_crtc *crtc,
+				enum pipedmc_event_id event);
+void intel_pipedmc_disable_event(struct intel_crtc *crtc,
+				 enum pipedmc_event_id event);
+
+void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
+
 #endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 82cb58cf9c6a..8f022adfea18 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -13,6 +13,7 @@
 #include "intel_de.h"
 #include "intel_display_rpm.h"
 #include "intel_display_types.h"
+#include "intel_dmc_regs.h"
 #include "intel_dsb.h"
 #include "intel_dsb_buffer.h"
 #include "intel_dsb_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
new file mode 100644
index 000000000000..8677929b7ece
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/pci.h>
+
+#include <drm/drm_print.h>
+
+#include "i915_utils.h"
+#include "intel_step.h"
+#include "intel_crtc.h"
+#include "intel_de.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "intel_flipq.h"
+#include "intel_dmc.h"
+#include "intel_dmc_regs.h"
+#include "intel_dsb.h"
+#include "intel_vblank.h"
+
+#define for_each_flipq(flipq_id) \
+	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ; (flipq_id)++)
+
+static int intel_flipq_offset(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+		return 0x008;
+	case INTEL_FLIPQ_PLANE_2:
+		return 0x108;
+	case INTEL_FLIPQ_PLANE_3:
+		return 0x208;
+	case INTEL_FLIPQ_GENERAL:
+		return 0x308;
+	case INTEL_FLIPQ_FAST:
+		return 0x3c8;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_size_dw(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		return 64;
+	case INTEL_FLIPQ_GENERAL:
+	case INTEL_FLIPQ_FAST:
+		return 48;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_elem_size_dw(enum intel_flipq_id flipq_id)
+{
+	switch (flipq_id) {
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		return 4;
+	case INTEL_FLIPQ_GENERAL:
+	case INTEL_FLIPQ_FAST:
+		return 6;
+	default:
+		MISSING_CASE(flipq_id);
+		return 0;
+	}
+}
+
+static int intel_flipq_size_entries(enum intel_flipq_id flipq_id)
+{
+	return intel_flipq_size_dw(flipq_id) / intel_flipq_elem_size_dw(flipq_id);
+}
+
+static void intel_flipq_crtc_init(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	enum intel_flipq_id flipq_id;
+
+	for_each_flipq(flipq_id) {
+		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+
+		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id);
+		flipq->flipq_id = flipq_id;
+
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] flip queue %d: start 0x%x\n",
+			    crtc->base.base.id, crtc->base.name,
+			    flipq_id, flipq->start_mmioaddr);
+	}
+}
+
+void intel_flipq_init(struct intel_display *display)
+{
+	struct intel_crtc *crtc;
+
+	intel_dmc_wait_fw_load(display);
+
+	for_each_intel_crtc(display->drm, crtc)
+		intel_flipq_crtc_init(crtc);
+}
+
+static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	drm_dbg_kms(display->drm, "preempt %d\n", preempt);
+
+	intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),
+		     PIPEDMC_FQ_CTRL_PREEMPT, preempt ? PIPEDMC_FQ_CTRL_PREEMPT : 0);
+	/* FIXME what timeout? */
+	if (preempt &&
+	    intel_de_wait_for_clear(display, PIPEDMC_FQ_CTRL(crtc->pipe),
+				    PIPEDMC_FQ_CTRL_BUSY, 10))
+		drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt timeout\n",
+			crtc->base.base.id, crtc->base.name);
+}
+
+static int intel_flipq_current_head(struct intel_crtc *crtc, enum intel_flipq_id flipq_id)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
+}
+
+static void intel_flipq_write_tail(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),
+		       PIPEDMC_FPQ_PLANEQ_3_TP(crtc->flipq[INTEL_FLIPQ_PLANE_3].tail) |
+		       PIPEDMC_FPQ_PLANEQ_2_TP(crtc->flipq[INTEL_FLIPQ_PLANE_2].tail) |
+		       PIPEDMC_FPQ_PLANEQ_1_TP(crtc->flipq[INTEL_FLIPQ_PLANE_1].tail) |
+		       PIPEDMC_FPQ_FASTQ_TP(crtc->flipq[INTEL_FLIPQ_FAST].tail) |
+		       PIPEDMC_FPQ_GENERALQ_TP(crtc->flipq[INTEL_FLIPQ_GENERAL].tail));
+}
+
+static void intel_flipq_sw_dmc_wake(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+
+	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);
+}
+
+static int cdclk_factor(struct intel_display *display)
+{
+	if (DISPLAY_VER(display) >= 30)
+		return 120;
+	else
+		return 280;
+}
+
+static int intel_flipq_exec_time_us(struct intel_display *display)
+{
+	/* TODO ask the DSB code what this should be */
+	int dsb_exec_time = 20;
+	/* FIXME how to deal with cdclk changes? */
+	int cdclk_freq = 200000;
+
+	return dsb_exec_time + 540000 / cdclk_freq * cdclk_factor(display) +
+		display->sagv.block_time_us;
+}
+
+static int intel_flipq_exec_time_lines(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+					intel_flipq_exec_time_us(display));
+}
+
+void intel_flipq_reset(struct intel_display *display, enum pipe pipe)
+{
+	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
+	enum intel_flipq_id flipq_id;
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);
+
+	for_each_flipq(flipq_id) {
+		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+
+		intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);
+		intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);
+
+		flipq->tail = 0;
+	}
+
+	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0);
+}
+
+void intel_flipq_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	/* FIXME what to do with VRR? */
+	int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode) -
+		intel_flipq_exec_time_lines(crtc_state);
+
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] flipq queue scanlined %d-%d\n",
+		    crtc->base.base.id, crtc->base.name, scanline - 2, scanline);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),
+		       PIPEDMC_SCANLINEINRANGECMP_EN |
+		       PIPEDMC_SCANLINE_LOWER(scanline - 2));
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),
+		       PIPEDMC_SCANLINE_UPPER(scanline));
+
+	intel_pipedmc_enable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);
+}
+
+void intel_flipq_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
+
+	intel_pipedmc_disable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
+
+	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
+	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0);
+}
+
+static bool assert_flipq_has_room(struct intel_crtc *crtc,
+				  enum intel_flipq_id flipq_id)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+	int head, size = intel_flipq_size_entries(flipq_id);
+
+	head = intel_flipq_current_head(crtc, flipq_id);
+
+	return !drm_WARN(display->drm,
+			 (flipq->tail + size - head) % size >= size - 1,
+			 "[CRTC:%d:%s] FLIPQ %d overflow (head %d, tail %d, size %d)\n",
+			 crtc->base.base.id, crtc->base.name, flipq_id,
+			 head, flipq->tail, size);
+}
+
+static void intel_flipq_write(struct intel_display *display,
+			      struct intel_flipq *flipq, u32 data, int i)
+{
+	intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq->tail *
+					       intel_flipq_elem_size_dw(flipq->flipq_id) + i), data);
+}
+
+void intel_flipq_add(struct intel_crtc *crtc,
+		     enum intel_flipq_id flipq_id,
+		     unsigned int pts,
+		     enum intel_dsb_id dsb_id,
+		     struct intel_dsb *dsb)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+	int i = 0;
+
+	if (!assert_flipq_has_room(crtc, flipq_id))
+		return;
+
+	pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
+
+	intel_flipq_preempt(crtc, true);
+
+	switch (flipq_id) {
+	case INTEL_FLIPQ_GENERAL:
+		intel_flipq_write(display, flipq, pts, i++);
+		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
+		intel_flipq_write(display, flipq, FQ_INTERRUPT |
+				  FQ_DSB_ID(dsb_id) |
+				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
+		intel_flipq_write(display, flipq, 0, i++);
+		intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
+		intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for second DSB */
+		break;
+	case INTEL_FLIPQ_PLANE_1:
+	case INTEL_FLIPQ_PLANE_2:
+	case INTEL_FLIPQ_PLANE_3:
+		intel_flipq_write(display, flipq, pts, i++);
+		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
+		intel_flipq_write(display, flipq, FQ_INTERRUPT |
+				  FQ_DSB_ID(dsb_id) |
+				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
+		intel_flipq_write(display, flipq, 0, i++);
+		break;
+	default:
+		MISSING_CASE(flipq_id);
+		return;
+	}
+
+	flipq->tail = (flipq->tail + 1) % intel_flipq_size_entries(flipq->flipq_id);
+	intel_flipq_write_tail(crtc);
+
+	intel_flipq_preempt(crtc, false);
+
+	intel_flipq_sw_dmc_wake(crtc);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h b/drivers/gpu/drm/i915/display/intel_flipq.h
new file mode 100644
index 000000000000..8483c93ecdb3
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_flipq.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_FLIPQ_H__
+#define __INTEL_FLIPQ_H__
+
+#include <linux/types.h>
+
+enum intel_dsb_id;
+enum intel_flipq_id;
+enum pipe;
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_display;
+struct intel_dsb;
+
+void intel_flipq_init(struct intel_display *display);
+void intel_flipq_reset(struct intel_display *display, enum pipe pipe);
+
+void intel_flipq_enable(const struct intel_crtc_state *crtc_state);
+void intel_flipq_disable(const struct intel_crtc_state *old_crtc_state);
+
+void intel_flipq_add(struct intel_crtc *crtc,
+		     enum intel_flipq_id flip_queue_id,
+		     unsigned int pts,
+		     enum intel_dsb_id dsb_id,
+		     struct intel_dsb *dsb);
+void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb);
+void intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
+
+#endif /* __INTEL_FLIPQ_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e4bf484d4121..558d282c7b90 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -254,6 +254,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_fbc.o \
 	i915-display/intel_fdi.o \
 	i915-display/intel_fifo_underrun.o \
+	i915-display/intel_flipq.o \
 	i915-display/intel_frontbuffer.o \
 	i915-display/intel_global_state.o \
 	i915-display/intel_gmbus.o \
-- 
2.49.0

RE: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Monday, May 19, 2025 10:39 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip
> queue
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Provide the lower level code for PIPEDMC based flip queue.
> 
> We'll use the so called semi-full flip queue mode where the PIPEDMC will start
> the provided DSB on a scanline a little ahead of the vblank. We need to program
> the triggering scanline early enough so that the DSB has enough time to complete
> writing all the double buffered registers before they get latched (at start of
> vblank).
> 
> The firmware implements several queues:
> - 3 "plane queues" which execute a single DSB per entry
> - 1 "general queue" which can apparently execute 2 DSBs per entry
> - 1 vestigial "fast queue" that replaced the "simple flip queue"
>   on ADL+, but this isn't supposed to be used due to issues.
> 
> But we only need a single plane queue really, and we won't actually use it as a
> real queue because we don't allow queueing multiple commits ahead of time. So
> the whole thing is perhaps useless. I suppose there migth be some power saving
> benefits if we would get the flip scheduled by userspace early and then could
> keep some hardware powered off a bit longer until the DMC kicks off the flipq
> programming. But that is pure speculation at this time and needs to be proven.
> 
> The code to hook up the flip queue into the actual atomic commit path will follow
> later.
> 
> TODO: need to think how to do the "wait for DMC firmware load" nicely
>       need to think what to about the cdclk dependency on the execution time
>       need to think about VRR and PSR
>       etc.
> 
> v2: Don't write DMC_FQ_W2_PTS_CFG_SEL on pre-lnl
>     Don't oops at flipq init if there is no dmc
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  .../drm/i915/display/intel_display_driver.c   |   3 +
>  .../drm/i915/display/intel_display_types.h    |  17 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      |  52 +++
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
>  drivers/gpu/drm/i915/display/intel_dsb.c      |   1 +
>  drivers/gpu/drm/i915/display/intel_flipq.c    | 306 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_flipq.h    |  33 ++
>  drivers/gpu/drm/xe/Makefile                   |   1 +
>  9 files changed, 425 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 1a90eb1f180a..20ac3b2bdb81 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -266,6 +266,7 @@ i915-y += \
>  	display/intel_fbc.o \
>  	display/intel_fdi.o \
>  	display/intel_fifo_underrun.o \
> +	display/intel_flipq.o \
>  	display/intel_frontbuffer.o \
>  	display/intel_global_state.o \
>  	display/intel_hdcp.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 5c74ab5fd1aa..1c4751cf1d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -43,6 +43,7 @@
>  #include "intel_fbc.h"
>  #include "intel_fbdev.h"
>  #include "intel_fdi.h"
> +#include "intel_flipq.h"
>  #include "intel_gmbus.h"
>  #include "intel_hdcp.h"
>  #include "intel_hotplug.h"
> @@ -506,6 +507,8 @@ int intel_display_driver_probe(struct intel_display
> *display)
>  	 */
>  	intel_hdcp_component_init(display);
> 
> +	intel_flipq_init(display);
> +
>  	/*
>  	 * Force all active planes to recompute their states. So that on
>  	 * mode_setcrtc after probe, all the intel_plane_state variables diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 056219272c36..2f3fdf292d88 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1365,6 +1365,21 @@ struct intel_pipe_crc {
>  	enum intel_pipe_crc_source source;
>  };
> 
> +enum intel_flipq_id {
> +	INTEL_FLIPQ_PLANE_1,
> +	INTEL_FLIPQ_PLANE_2,
> +	INTEL_FLIPQ_PLANE_3,
> +	INTEL_FLIPQ_GENERAL,
> +	INTEL_FLIPQ_FAST,
> +	MAX_INTEL_FLIPQ,
> +};
> +
> +struct intel_flipq {
> +	u32 start_mmioaddr;
> +	enum intel_flipq_id flipq_id;
> +	u8 tail;
> +};
> +
>  struct intel_crtc {
>  	struct drm_crtc base;
>  	enum pipe pipe;
> @@ -1396,6 +1411,8 @@ struct intel_crtc {
>  	bool cpu_fifo_underrun_disabled;
>  	bool pch_fifo_underrun_disabled;
> 
> +	struct intel_flipq flipq[MAX_INTEL_FLIPQ];
> +
>  	/* per-pipe watermark state */
>  	struct {
>  		/* watermarks currently being used  */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index a7ba17361d63..2ff62740833c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -24,16 +24,19 @@
> 
>  #include <linux/debugfs.h>
>  #include <linux/firmware.h>
> +#include <drm/drm_vblank.h>
> 
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> +#include "intel_display_types.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_power_well.h"
>  #include "intel_display_types.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
> +#include "intel_flipq.h"
>  #include "intel_step.h"
> 
>  /**
> @@ -511,6 +514,8 @@ void intel_dmc_enable_pipe(struct intel_display *display,
> enum pipe pipe)
>  		return;
> 
>  	if (DISPLAY_VER(display) >= 20) {
> +		intel_flipq_reset(display, pipe);
> +
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe),
> pipedmc_interrupt_mask(display));
>  		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe),
> ~pipedmc_interrupt_mask(display));
>  	}
> @@ -536,6 +541,8 @@ void intel_dmc_disable_pipe(struct intel_display *display,
> enum pipe pipe)
>  	if (DISPLAY_VER(display) >= 20) {
>  		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe),
> pipedmc_interrupt_mask(display));
> +
> +		intel_flipq_reset(display, pipe);
>  	}
>  }
> 
> @@ -715,6 +722,13 @@ void intel_dmc_load_program(struct intel_display
> *display)
>  		}
>  	}
> 
> +	if (DISPLAY_VER(display) >= 20)
> +		intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL,
> +			       PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) |
> +			       PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) |
> +			       PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) |
> +			       PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A));
> +
>  	power_domains->dc_state = 0;
> 
>  	gen9_set_dc_state_debugmask(display);
> @@ -1243,6 +1257,17 @@ void intel_dmc_suspend(struct intel_display *display)
>  		intel_dmc_runtime_pm_put(display);
>  }
> 
> +void intel_dmc_wait_fw_load(struct intel_display *display) {
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +
> +	if (!HAS_DMC(display))
> +		return;
> +
> +	if (dmc)
> +		flush_work(&dmc->work);
> +}
> +
>  /**
>   * intel_dmc_resume() - init DMC firmware during system resume
>   * @display: display instance
> @@ -1478,3 +1503,30 @@ void intel_pipedmc_irq_handler(struct intel_display
> *display, enum pipe pipe)
>  		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt
> vector 0x%x\n",
>  			crtc->base.base.id, crtc->base.name, tmp);  }
> +
> +void intel_pipedmc_enable_event(struct intel_crtc *crtc,
> +				enum pipedmc_event_id event)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	dmc_configure_event(display, dmc_id, event, true); }
> +
> +void intel_pipedmc_disable_event(struct intel_crtc *crtc,
> +				 enum pipedmc_event_id event)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	dmc_configure_event(display, dmc_id, event, false); }
> +
> +u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe);
> +
> +	return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; }
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> b/drivers/gpu/drm/i915/display/intel_dmc.h
> index a98e8deff13a..b94aa2e7e50c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -9,12 +9,15 @@
>  #include <linux/types.h>
> 
>  enum pipe;
> +enum pipedmc_event_id;
>  struct drm_printer;
> +struct intel_crtc;
>  struct intel_display;
>  struct intel_dmc_snapshot;
> 
>  void intel_dmc_init(struct intel_display *display);  void
> intel_dmc_load_program(struct intel_display *display);
> +void intel_dmc_wait_fw_load(struct intel_display *display);
>  void intel_dmc_disable_program(struct intel_display *display);  void
> intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);  void
> intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe); @@ -36,4
> +39,12 @@ void assert_dmc_loaded(struct intel_display *display);
> 
>  void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe);
> 
> +u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc); void
> +intel_pipedmc_enable_event(struct intel_crtc *crtc,
> +				enum pipedmc_event_id event);
> +void intel_pipedmc_disable_event(struct intel_crtc *crtc,
> +				 enum pipedmc_event_id event);
> +
> +void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe
> +pipe);
> +
>  #endif /* __INTEL_DMC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 82cb58cf9c6a..8f022adfea18 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -13,6 +13,7 @@
>  #include "intel_de.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_types.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dsb.h"
>  #include "intel_dsb_buffer.h"
>  #include "intel_dsb_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> new file mode 100644
> index 000000000000..8677929b7ece
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -0,0 +1,306 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/pci.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "i915_utils.h"
> +#include "intel_step.h"
> +#include "intel_crtc.h"
> +#include "intel_de.h"
> +#include "intel_display_core.h"
> +#include "intel_display_types.h"
> +#include "intel_flipq.h"
> +#include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
> +#include "intel_dsb.h"
> +#include "intel_vblank.h"
> +
> +#define for_each_flipq(flipq_id) \
> +	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ;
> +(flipq_id)++)
> +
> +static int intel_flipq_offset(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +		return 0x008;
> +	case INTEL_FLIPQ_PLANE_2:
> +		return 0x108;
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 0x208;
> +	case INTEL_FLIPQ_GENERAL:
> +		return 0x308;
> +	case INTEL_FLIPQ_FAST:
> +		return 0x3c8;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_size_dw(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 64;
> +	case INTEL_FLIPQ_GENERAL:
> +	case INTEL_FLIPQ_FAST:
> +		return 48;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_elem_size_dw(enum intel_flipq_id flipq_id) {
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		return 4;
> +	case INTEL_FLIPQ_GENERAL:
> +	case INTEL_FLIPQ_FAST:
> +		return 6;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return 0;
> +	}
> +}
> +
> +static int intel_flipq_size_entries(enum intel_flipq_id flipq_id) {
> +	return intel_flipq_size_dw(flipq_id) /
> +intel_flipq_elem_size_dw(flipq_id);
> +}
> +
> +static void intel_flipq_crtc_init(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	enum intel_flipq_id flipq_id;
> +
> +	for_each_flipq(flipq_id) {
> +		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +
> +		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) +
> intel_flipq_offset(flipq_id);
> +		flipq->flipq_id = flipq_id;
> +
> +		drm_dbg_kms(display->drm, "[CRTC:%d:%s] flip queue %d: start
> 0x%x\n",
> +			    crtc->base.base.id, crtc->base.name,
> +			    flipq_id, flipq->start_mmioaddr);
> +	}
> +}
> +
> +void intel_flipq_init(struct intel_display *display) {
> +	struct intel_crtc *crtc;
> +
> +	intel_dmc_wait_fw_load(display);
> +
> +	for_each_intel_crtc(display->drm, crtc)
> +		intel_flipq_crtc_init(crtc);
> +}
> +
> +static void intel_flipq_preempt(struct intel_crtc *crtc, bool preempt)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	drm_dbg_kms(display->drm, "preempt %d\n", preempt);
> +
> +	intel_de_rmw(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +		     PIPEDMC_FQ_CTRL_PREEMPT, preempt ?
> PIPEDMC_FQ_CTRL_PREEMPT : 0);
> +	/* FIXME what timeout? */
> +	if (preempt &&
> +	    intel_de_wait_for_clear(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +				    PIPEDMC_FQ_CTRL_BUSY, 10))
> +		drm_err(display->drm, "[CRTC:%d:%s] flip queue preempt
> timeout\n",
> +			crtc->base.base.id, crtc->base.name); }
> +
> +static int intel_flipq_current_head(struct intel_crtc *crtc, enum
> +intel_flipq_id flipq_id) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id));
> +}
> +
> +static void intel_flipq_write_tail(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe),
> +		       PIPEDMC_FPQ_PLANEQ_3_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_3].tail) |
> +		       PIPEDMC_FPQ_PLANEQ_2_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_2].tail) |
> +		       PIPEDMC_FPQ_PLANEQ_1_TP(crtc-
> >flipq[INTEL_FLIPQ_PLANE_1].tail) |
> +		       PIPEDMC_FPQ_FASTQ_TP(crtc-
> >flipq[INTEL_FLIPQ_FAST].tail) |
> +
> +PIPEDMC_FPQ_GENERALQ_TP(crtc->flipq[INTEL_FLIPQ_GENERAL].tail));
> +}
> +
> +static void intel_flipq_sw_dmc_wake(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +
> +	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe),
> +PIPEDMC_SW_DMC_WAKE); }
> +
> +static int cdclk_factor(struct intel_display *display) {
> +	if (DISPLAY_VER(display) >= 30)
> +		return 120;
> +	else
> +		return 280;
> +}
> +
> +static int intel_flipq_exec_time_us(struct intel_display *display) {
> +	/* TODO ask the DSB code what this should be */
> +	int dsb_exec_time = 20;

I think optimum value would be 100.
From bspec: "For the flip queue use case, the recommended DSB execution time is 100us + one SAGV block time"

> +	/* FIXME how to deal with cdclk changes? */
> +	int cdclk_freq = 200000;
> +
> +	return dsb_exec_time + 540000 / cdclk_freq * cdclk_factor(display) +
> +		display->sagv.block_time_us;
> +}
> +
> +static int intel_flipq_exec_time_lines(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> +					intel_flipq_exec_time_us(display));
> +}
> +
> +void intel_flipq_reset(struct intel_display *display, enum pipe pipe) {
> +	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> +	enum intel_flipq_id flipq_id;
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0);
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0);
> +
> +	for_each_flipq(flipq_id) {
> +		struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +
> +		intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0);
> +		intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0);
> +
> +		flipq->tail = 0;
> +	}
> +
> +	intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0); }
> +
> +void intel_flipq_enable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	/* FIXME what to do with VRR? */
> +	int scanline = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode)
> -
> +		intel_flipq_exec_time_lines(crtc_state);
> +
> +	drm_dbg_kms(display->drm, "[CRTC:%d:%s] flipq queue scanlined %d-
> %d\n",
> +		    crtc->base.base.id, crtc->base.name, scanline - 2, scanline);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe),
> +		       PIPEDMC_SCANLINEINRANGECMP_EN |
> +		       PIPEDMC_SCANLINE_LOWER(scanline - 2));
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe),
> +		       PIPEDMC_SCANLINE_UPPER(scanline));
> +
> +	intel_pipedmc_enable_event(crtc,
> +PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> +PIPEDMC_FQ_CTRL_ENABLE); }
> +
> +void intel_flipq_disable(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> +	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
> +
> +	intel_pipedmc_disable_event(crtc,
> +PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> +
> +	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
> +	intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), 0); }
> +
> +static bool assert_flipq_has_room(struct intel_crtc *crtc,
> +				  enum intel_flipq_id flipq_id)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	int head, size = intel_flipq_size_entries(flipq_id);
> +
> +	head = intel_flipq_current_head(crtc, flipq_id);
> +
> +	return !drm_WARN(display->drm,
> +			 (flipq->tail + size - head) % size >= size - 1,
> +			 "[CRTC:%d:%s] FLIPQ %d overflow (head %d, tail %d,
> size %d)\n",
> +			 crtc->base.base.id, crtc->base.name, flipq_id,
> +			 head, flipq->tail, size);
> +}
> +
> +static void intel_flipq_write(struct intel_display *display,
> +			      struct intel_flipq *flipq, u32 data, int i) {
> +	intel_de_write(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, flipq-
> >tail *
> +					       intel_flipq_elem_size_dw(flipq-
> >flipq_id) + i), data); }
> +
> +void intel_flipq_add(struct intel_crtc *crtc,
> +		     enum intel_flipq_id flipq_id,
> +		     unsigned int pts,
> +		     enum intel_dsb_id dsb_id,
> +		     struct intel_dsb *dsb)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	int i = 0;
> +
> +	if (!assert_flipq_has_room(crtc, flipq_id))
> +		return;
> +
> +	pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe));
> +
> +	intel_flipq_preempt(crtc, true);
> +
> +	switch (flipq_id) {
> +	case INTEL_FLIPQ_GENERAL:
> +		intel_flipq_write(display, flipq, pts, i++);
> +		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
> +		intel_flipq_write(display, flipq, FQ_INTERRUPT |
> +				  FQ_DSB_ID(dsb_id) |
> +				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
> +		intel_flipq_write(display, flipq, 0, i++);
> +		intel_flipq_write(display, flipq, 0, i++); /* head for second DSB */
> +		intel_flipq_write(display, flipq, 0, i++); /* DSB engine + size for
> second DSB */
> +		break;
> +	case INTEL_FLIPQ_PLANE_1:
> +	case INTEL_FLIPQ_PLANE_2:
> +	case INTEL_FLIPQ_PLANE_3:
> +		intel_flipq_write(display, flipq, pts, i++);
> +		intel_flipq_write(display, flipq, intel_dsb_head(dsb), i++);
> +		intel_flipq_write(display, flipq, FQ_INTERRUPT |
> +				  FQ_DSB_ID(dsb_id) |
> +				  FQ_DSB_SIZE(intel_dsb_size(dsb) / 64), i++);
> +		intel_flipq_write(display, flipq, 0, i++);
> +		break;
> +	default:
> +		MISSING_CASE(flipq_id);
> +		return;
> +	}
> +
> +	flipq->tail = (flipq->tail + 1) % intel_flipq_size_entries(flipq->flipq_id);
> +	intel_flipq_write_tail(crtc);
> +
> +	intel_flipq_preempt(crtc, false);
> +
> +	intel_flipq_sw_dmc_wake(crtc);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h
> b/drivers/gpu/drm/i915/display/intel_flipq.h
> new file mode 100644
> index 000000000000..8483c93ecdb3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_FLIPQ_H__
> +#define __INTEL_FLIPQ_H__
> +
> +#include <linux/types.h>
> +
> +enum intel_dsb_id;
> +enum intel_flipq_id;
> +enum pipe;
> +struct intel_crtc;
> +struct intel_crtc_state;
> +struct intel_display;
> +struct intel_dsb;
> +
> +void intel_flipq_init(struct intel_display *display); void
> +intel_flipq_reset(struct intel_display *display, enum pipe pipe);
> +
> +void intel_flipq_enable(const struct intel_crtc_state *crtc_state);
> +void intel_flipq_disable(const struct intel_crtc_state
> +*old_crtc_state);
> +
> +void intel_flipq_add(struct intel_crtc *crtc,
> +		     enum intel_flipq_id flip_queue_id,
> +		     unsigned int pts,
> +		     enum intel_dsb_id dsb_id,
> +		     struct intel_dsb *dsb);
> +void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb); void
> +intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +
> +#endif /* __INTEL_FLIPQ_H__ */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> e4bf484d4121..558d282c7b90 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -254,6 +254,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>  	i915-display/intel_fbc.o \
>  	i915-display/intel_fdi.o \
>  	i915-display/intel_fifo_underrun.o \
> +	i915-display/intel_flipq.o \
>  	i915-display/intel_frontbuffer.o \
>  	i915-display/intel_global_state.o \
>  	i915-display/intel_gmbus.o \
> --
> 2.49.0

Re: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Ville Syrjälä]

On Tue, May 20, 2025 at 07:06:42AM +0000, Shankar, Uma wrote:
> > +static int intel_flipq_exec_time_us(struct intel_display *display) {
> > +	/* TODO ask the DSB code what this should be */
> > +	int dsb_exec_time = 20;
> 
> I think optimum value would be 100.
> From bspec: "For the flip queue use case, the recommended DSB execution time is 100us + one SAGV block time"

That's just a random number someone pulled out of a hat. We currently
use 20 usec for the arming registers writes, and we don't have any estimate
for the non-arming stuff since we don't need it. But for flip queue we need
to guesstimate the whole thing, so I suppose I might as well slap in a 80usec
for the non-arming part now. 

Ideally we should calculate this based on how many registers we are writing,
but that would require measuring the DSB execution speed and coming up with
a reasonable formula for it...

-- 
Ville Syrjälä
Intel

RE: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for flip queue

[Shankar, Uma]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, May 21, 2025 11:11 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH v2 07/12] drm/i915/flipq: Provide the nuts and bolts code for
> flip queue
> 
> On Tue, May 20, 2025 at 07:06:42AM +0000, Shankar, Uma wrote:
> > > +static int intel_flipq_exec_time_us(struct intel_display *display) {
> > > +	/* TODO ask the DSB code what this should be */
> > > +	int dsb_exec_time = 20;
> >
> > I think optimum value would be 100.
> > From bspec: "For the flip queue use case, the recommended DSB execution time
> is 100us + one SAGV block time"
> 
> That's just a random number someone pulled out of a hat. We currently use 20
> usec for the arming registers writes, and we don't have any estimate for the non-
> arming stuff since we don't need it. But for flip queue we need to guesstimate the
> whole thing, so I suppose I might as well slap in a 80usec for the non-arming part
> now.

Agree, this is more of an empirical value provided. Yeah would be good to have this
extra buffer.

> Ideally we should calculate this based on how many registers we are writing, but
> that would require measuring the DSB execution speed and coming up with a
> reasonable formula for it...

Agree, it depends on the number or registers. We can extend this later to get an optimum value,
especially where we have just 2-3 registers to update vs 1000 of regs for luts etc.

Regards,
Uma Shankar

> --
> Ville Syrjälä
> Intel

[PATCH 08/12] drm/i915/flipq: Implement flipq queue based commit path

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Support commits via the flip queue (as opposed to DSB or MMIO).

As it's somewhat unknown if we can actually use it is currently
gated behind the new use_flipq modparam, which defaults to disabled.

The implementation has a bunch of limitations that would need
real though to solve:
- disabled when PSR is used
- disabled when VRR is used
- color management updates not performed via the flip queue

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 63 +++++++++++++------
 .../drm/i915/display/intel_display_params.c   |  3 +
 .../drm/i915/display/intel_display_params.h   |  1 +
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dmc.c      | 20 +++++-
 5 files changed, 71 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b09f8ae76ff..3a42536247d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -93,6 +93,7 @@
 #include "intel_fbc.h"
 #include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
+#include "intel_flipq.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
@@ -6610,7 +6611,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
 
-	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
 
 	/*
 	 * During modesets pipe configuration was programmed as the
@@ -6639,7 +6640,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
 
 	/*
 	 * Disable the scaler(s) after the plane(s) so that we don't
@@ -6723,10 +6724,10 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 
 	if (!modeset &&
 	    intel_crtc_needs_color_update(new_crtc_state) &&
-	    !new_crtc_state->use_dsb)
+	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
 		intel_color_commit_noarm(NULL, new_crtc_state);
 
-	if (!new_crtc_state->use_dsb)
+	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
 		intel_crtc_planes_update_noarm(NULL, state, crtc);
 }
 
@@ -6738,7 +6739,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (new_crtc_state->use_dsb) {
+	if (new_crtc_state->use_flipq) {
+		intel_flipq_enable(new_crtc_state);
+
+		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event);
+
+		intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0,
+				new_crtc_state->dsb_commit);
+	} else if (new_crtc_state->use_dsb) {
 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
 
 		intel_dsb_commit(new_crtc_state->dsb_commit, false);
@@ -7176,7 +7184,18 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
 		return;
 
 	/* FIXME deal with everything */
+	new_crtc_state->use_flipq =
+		display->params.enable_flipq &&
+		DISPLAY_VER(display) >= 20 &&
+		!new_crtc_state->do_async_flip &&
+		!new_crtc_state->vrr.enable &&
+		!new_crtc_state->has_psr &&
+		!intel_crtc_needs_modeset(new_crtc_state) &&
+		!intel_crtc_needs_fastset(new_crtc_state) &&
+		!intel_crtc_needs_color_update(new_crtc_state);
+
 	new_crtc_state->use_dsb =
+		!new_crtc_state->use_flipq &&
 		!new_crtc_state->do_async_flip &&
 		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
 		!intel_crtc_needs_modeset(new_crtc_state) &&
@@ -7192,7 +7211,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
+	if (!new_crtc_state->use_flipq &&
+	    !new_crtc_state->use_dsb &&
+	    !new_crtc_state->dsb_color_vblank)
 		return;
 
 	/*
@@ -7201,14 +7222,16 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	 * Double that for pipe stuff and other overhead.
 	 */
 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
-						       new_crtc_state->use_dsb ? 1024 : 16);
+						       new_crtc_state->use_dsb ||
+						       new_crtc_state->use_flipq ? 1024 : 16);
 	if (!new_crtc_state->dsb_commit) {
+		new_crtc_state->use_flipq = false;
 		new_crtc_state->use_dsb = false;
 		intel_color_cleanup_commit(new_crtc_state);
 		return;
 	}
 
-	if (new_crtc_state->use_dsb) {
+	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7223,7 +7246,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
 						     state, crtc);
 
-		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
+		if (new_crtc_state->use_dsb)
+			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
 
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_arm(new_crtc_state->dsb_commit,
@@ -7238,21 +7262,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		if (DISPLAY_VER(display) >= 9)
 			skl_detach_scalers(new_crtc_state->dsb_commit,
 					   new_crtc_state);
-
-		if (!new_crtc_state->dsb_color_vblank) {
-			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
-
-			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
-			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
-			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
-			intel_dsb_interrupt(new_crtc_state->dsb_commit);
-		}
 	}
 
 	if (new_crtc_state->dsb_color_vblank)
 		intel_dsb_chain(state, new_crtc_state->dsb_commit,
 				new_crtc_state->dsb_color_vblank, true);
 
+	if (new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) {
+		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+
+		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
+		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
+		intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
+		intel_dsb_interrupt(new_crtc_state->dsb_commit);
+	}
+
 	intel_dsb_finish(new_crtc_state->dsb_commit);
 }
 
@@ -7397,6 +7421,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
 			intel_vrr_check_push_sent(NULL, new_crtc_state);
+
+		if (new_crtc_state->use_flipq)
+			intel_flipq_disable(new_crtc_state);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index c4f1ab43fc0c..75316247ee8a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -62,6 +62,9 @@ intel_display_param_named_unsafe(enable_dpt, bool, 0400,
 intel_display_param_named_unsafe(enable_dsb, bool, 0400,
 	"Enable display state buffer (DSB) (default: true)");
 
+intel_display_param_named_unsafe(enable_flipq, bool, 0400,
+	"Enable DMC flip queue (default: false)");
+
 intel_display_param_named_unsafe(enable_sagv, bool, 0400,
 	"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 5317138e6044..784e6bae8615 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -31,6 +31,7 @@ struct drm_printer;
 	param(int, enable_dc, -1, 0400) \
 	param(bool, enable_dpt, true, 0400) \
 	param(bool, enable_dsb, true, 0600) \
+	param(bool, enable_flipq, false, 0600) \
 	param(bool, enable_sagv, true, 0600) \
 	param(int, disable_power_well, -1, 0400) \
 	param(bool, enable_ips, true, 0600) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2f3fdf292d88..dd87099823d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1299,6 +1299,7 @@ struct intel_crtc_state {
 	/* For DSB based pipe updates */
 	struct intel_dsb *dsb_color_vblank, *dsb_commit;
 	bool use_dsb;
+	bool use_flipq;
 
 	u32 psr2_man_track_ctl;
 
@@ -1406,6 +1407,8 @@ struct intel_crtc {
 	struct drm_pending_vblank_event *flip_done_event;
 	/* armed event for DSB based updates */
 	struct drm_pending_vblank_event *dsb_event;
+	/* armed event for flip queue based updates */
+	struct drm_pending_vblank_event *flipq_event;
 
 	/* Access to these should be protected by display->irq.lock. */
 	bool cpu_fifo_underrun_disabled;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 7b28da58faec..10d1be68df79 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -502,7 +502,8 @@ static u32 pipedmc_interrupt_mask(struct intel_display *display)
 	 * triggering it during the first DC state transition. Figure
 	 * out what is going on...
 	 */
-	return PIPEDMC_GTT_FAULT |
+	return PIPEDMC_FLIPQ_PROG_DONE |
+		PIPEDMC_GTT_FAULT |
 		PIPEDMC_ATS_FAULT;
 }
 
@@ -1486,6 +1487,23 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 		tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
 
+		if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
+			spin_lock(&display->drm->event_lock);
+
+			if (crtc->flipq_event) {
+				/*
+				 * Update vblank counter/timestamp in case it
+				 * hasn't been done yet for this frame.
+				 */
+				drm_crtc_accurate_vblank_count(&crtc->base);
+
+				drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event);
+				crtc->flipq_event = NULL;
+			}
+
+			spin_unlock(&display->drm->event_lock);
+		}
+
 		if (tmp & PIPEDMC_ATS_FAULT)
 			drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",
 					    crtc->base.base.id, crtc->base.name);
-- 
2.49.0

RE: [PATCH 08/12] drm/i915/flipq: Implement flipq queue based commit path

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 08/12] drm/i915/flipq: Implement flipq queue based commit
> path

Nit: Drop the redundant q from flipq

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Support commits via the flip queue (as opposed to DSB or MMIO).
> 
> As it's somewhat unknown if we can actually use it is currently gated behind the
> new use_flipq modparam, which defaults to disabled.
> 
> The implementation has a bunch of limitations that would need real though to
> solve:
> - disabled when PSR is used
> - disabled when VRR is used
> - color management updates not performed via the flip queue
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 63 +++++++++++++------
>  .../drm/i915/display/intel_display_params.c   |  3 +
>  .../drm/i915/display/intel_display_params.h   |  1 +
>  .../drm/i915/display/intel_display_types.h    |  3 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 20 +++++-
>  5 files changed, 71 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1b09f8ae76ff..3a42536247d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -93,6 +93,7 @@
>  #include "intel_fbc.h"
>  #include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
> +#include "intel_flipq.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_hdmi.h"
>  #include "intel_hotplug.h"
> @@ -6610,7 +6611,7 @@ static void commit_pipe_pre_planes(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> 
> -	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
> +	drm_WARN_ON(display->drm, new_crtc_state->use_dsb ||
> +new_crtc_state->use_flipq);
> 
>  	/*
>  	 * During modesets pipe configuration was programmed as the @@ -
> 6639,7 +6640,7 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
> +	drm_WARN_ON(display->drm, new_crtc_state->use_dsb ||
> +new_crtc_state->use_flipq);
> 
>  	/*
>  	 * Disable the scaler(s) after the plane(s) so that we don't @@ -6723,10
> +6724,10 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
> 
>  	if (!modeset &&
>  	    intel_crtc_needs_color_update(new_crtc_state) &&
> -	    !new_crtc_state->use_dsb)
> +	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
>  		intel_color_commit_noarm(NULL, new_crtc_state);
> 
> -	if (!new_crtc_state->use_dsb)
> +	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
>  		intel_crtc_planes_update_noarm(NULL, state, crtc);  }
> 
> @@ -6738,7 +6739,14 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	if (new_crtc_state->use_dsb) {
> +	if (new_crtc_state->use_flipq) {
> +		intel_flipq_enable(new_crtc_state);
> +
> +		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc-
> >flipq_event);
> +
> +		intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0,
> +				new_crtc_state->dsb_commit);
> +	} else if (new_crtc_state->use_dsb) {
>  		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc-
> >dsb_event);
> 
>  		intel_dsb_commit(new_crtc_state->dsb_commit, false); @@ -
> 7176,7 +7184,18 @@ static void intel_atomic_dsb_prepare(struct
> intel_atomic_state *state,
>  		return;
> 
>  	/* FIXME deal with everything */
> +	new_crtc_state->use_flipq =
> +		display->params.enable_flipq &&
> +		DISPLAY_VER(display) >= 20 &&
> +		!new_crtc_state->do_async_flip &&
> +		!new_crtc_state->vrr.enable &&
> +		!new_crtc_state->has_psr &&
> +		!intel_crtc_needs_modeset(new_crtc_state) &&
> +		!intel_crtc_needs_fastset(new_crtc_state) &&
> +		!intel_crtc_needs_color_update(new_crtc_state);
> +
>  	new_crtc_state->use_dsb =
> +		!new_crtc_state->use_flipq &&
>  		!new_crtc_state->do_async_flip &&
>  		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
>  		!intel_crtc_needs_modeset(new_crtc_state) && @@ -7192,7
> +7211,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
> +	if (!new_crtc_state->use_flipq &&
> +	    !new_crtc_state->use_dsb &&
> +	    !new_crtc_state->dsb_color_vblank)
>  		return;
> 
>  	/*
> @@ -7201,14 +7222,16 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  	 * Double that for pipe stuff and other overhead.
>  	 */
>  	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc,
> INTEL_DSB_0,
> -						       new_crtc_state->use_dsb ?
> 1024 : 16);
> +						       new_crtc_state->use_dsb
> ||
> +						       new_crtc_state->use_flipq
> ? 1024 : 16);
>  	if (!new_crtc_state->dsb_commit) {
> +		new_crtc_state->use_flipq = false;
>  		new_crtc_state->use_dsb = false;
>  		intel_color_cleanup_commit(new_crtc_state);
>  		return;
>  	}
> 
> -	if (new_crtc_state->use_dsb) {
> +	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
>  		if (intel_crtc_needs_color_update(new_crtc_state))
>  			intel_color_commit_noarm(new_crtc_state-
> >dsb_commit,
>  						 new_crtc_state);
> @@ -7223,7 +7246,8 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  		intel_psr_trigger_frame_change_event(new_crtc_state-
> >dsb_commit,
>  						     state, crtc);
> 
> -		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> +		if (new_crtc_state->use_dsb)
> +			intel_dsb_vblank_evade(state, new_crtc_state-
> >dsb_commit);
> 
>  		if (intel_crtc_needs_color_update(new_crtc_state))
>  			intel_color_commit_arm(new_crtc_state->dsb_commit,
> @@ -7238,21 +7262,21 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  		if (DISPLAY_VER(display) >= 9)
>  			skl_detach_scalers(new_crtc_state->dsb_commit,
>  					   new_crtc_state);
> -
> -		if (!new_crtc_state->dsb_color_vblank) {
> -			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit,
> 1);
> -
> -			intel_vrr_send_push(new_crtc_state->dsb_commit,
> new_crtc_state);
> -			intel_dsb_wait_vblank_delay(state, new_crtc_state-
> >dsb_commit);
> -			intel_vrr_check_push_sent(new_crtc_state-
> >dsb_commit, new_crtc_state);
> -			intel_dsb_interrupt(new_crtc_state->dsb_commit);
> -		}
>  	}
> 
>  	if (new_crtc_state->dsb_color_vblank)
>  		intel_dsb_chain(state, new_crtc_state->dsb_commit,
>  				new_crtc_state->dsb_color_vblank, true);
> 
> +	if (new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) {
> +		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> +
> +		intel_vrr_send_push(new_crtc_state->dsb_commit,
> new_crtc_state);
> +		intel_dsb_wait_vblank_delay(state, new_crtc_state-
> >dsb_commit);
> +		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> new_crtc_state);
> +		intel_dsb_interrupt(new_crtc_state->dsb_commit);
> +	}
> +
>  	intel_dsb_finish(new_crtc_state->dsb_commit);
>  }
> 
> @@ -7397,6 +7421,9 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> 
>  		if (!state->base.legacy_cursor_update && !new_crtc_state-
> >use_dsb)
>  			intel_vrr_check_push_sent(NULL, new_crtc_state);
> +
> +		if (new_crtc_state->use_flipq)
> +			intel_flipq_disable(new_crtc_state);
>  	}
> 
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
> b/drivers/gpu/drm/i915/display/intel_display_params.c
> index c4f1ab43fc0c..75316247ee8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -62,6 +62,9 @@ intel_display_param_named_unsafe(enable_dpt, bool,
> 0400,  intel_display_param_named_unsafe(enable_dsb, bool, 0400,
>  	"Enable display state buffer (DSB) (default: true)");
> 
> +intel_display_param_named_unsafe(enable_flipq, bool, 0400,
> +	"Enable DMC flip queue (default: false)");
> +
>  intel_display_param_named_unsafe(enable_sagv, bool, 0400,
>  	"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
> b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 5317138e6044..784e6bae8615 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -31,6 +31,7 @@ struct drm_printer;
>  	param(int, enable_dc, -1, 0400) \
>  	param(bool, enable_dpt, true, 0400) \
>  	param(bool, enable_dsb, true, 0600) \
> +	param(bool, enable_flipq, false, 0600) \
>  	param(bool, enable_sagv, true, 0600) \
>  	param(int, disable_power_well, -1, 0400) \
>  	param(bool, enable_ips, true, 0600) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2f3fdf292d88..dd87099823d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1299,6 +1299,7 @@ struct intel_crtc_state {
>  	/* For DSB based pipe updates */
>  	struct intel_dsb *dsb_color_vblank, *dsb_commit;
>  	bool use_dsb;
> +	bool use_flipq;
> 
>  	u32 psr2_man_track_ctl;
> 
> @@ -1406,6 +1407,8 @@ struct intel_crtc {
>  	struct drm_pending_vblank_event *flip_done_event;
>  	/* armed event for DSB based updates */
>  	struct drm_pending_vblank_event *dsb_event;
> +	/* armed event for flip queue based updates */
> +	struct drm_pending_vblank_event *flipq_event;
> 
>  	/* Access to these should be protected by display->irq.lock. */
>  	bool cpu_fifo_underrun_disabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 7b28da58faec..10d1be68df79 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -502,7 +502,8 @@ static u32 pipedmc_interrupt_mask(struct intel_display
> *display)
>  	 * triggering it during the first DC state transition. Figure
>  	 * out what is going on...
>  	 */
> -	return PIPEDMC_GTT_FAULT |
> +	return PIPEDMC_FLIPQ_PROG_DONE |
> +		PIPEDMC_GTT_FAULT |
>  		PIPEDMC_ATS_FAULT;
>  }
> 
> @@ -1486,6 +1487,23 @@ void intel_pipedmc_irq_handler(struct intel_display
> *display, enum pipe pipe)
>  		tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
> 
> +		if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
> +			spin_lock(&display->drm->event_lock);
> +
> +			if (crtc->flipq_event) {
> +				/*
> +				 * Update vblank counter/timestamp in case it
> +				 * hasn't been done yet for this frame.
> +				 */
> +				drm_crtc_accurate_vblank_count(&crtc->base);
> +
> +				drm_crtc_send_vblank_event(&crtc->base,
> crtc->flipq_event);
> +				crtc->flipq_event = NULL;
> +			}
> +
> +			spin_unlock(&display->drm->event_lock);
> +		}
> +
>  		if (tmp & PIPEDMC_ATS_FAULT)
>  			drm_err_ratelimited(display->drm, "[CRTC:%d:%s]
> PIPEDMC ATS fault\n",
>  					    crtc->base.base.id, crtc-
> >base.name);
> --
> 2.49.0

[PATCH v2 08/12] drm/i915/flipq: Implement flipq queue based commit path

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Support commits via the flip queue (as opposed to DSB or MMIO).

As it's somewhat unknown if we can actually use it is currently
gated behind the new use_flipq modparam, which defaults to disabled.

The implementation has a bunch of limitations that would need
real though to solve:
- disabled when PSR is used
- disabled when VRR is used
- color management updates not performed via the flip queue

v2: Don't use flip queue if there is no dmc

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 64 +++++++++++++------
 .../drm/i915/display/intel_display_params.c   |  3 +
 .../drm/i915/display/intel_display_params.h   |  1 +
 .../drm/i915/display/intel_display_types.h    |  3 +
 drivers/gpu/drm/i915/display/intel_dmc.c      | 20 +++++-
 5 files changed, 72 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1b09f8ae76ff..8b0eecfd4b16 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -93,6 +93,7 @@
 #include "intel_fbc.h"
 #include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
+#include "intel_flipq.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
@@ -6610,7 +6611,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
 
-	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
 
 	/*
 	 * During modesets pipe configuration was programmed as the
@@ -6639,7 +6640,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
 
 	/*
 	 * Disable the scaler(s) after the plane(s) so that we don't
@@ -6723,10 +6724,10 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 
 	if (!modeset &&
 	    intel_crtc_needs_color_update(new_crtc_state) &&
-	    !new_crtc_state->use_dsb)
+	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
 		intel_color_commit_noarm(NULL, new_crtc_state);
 
-	if (!new_crtc_state->use_dsb)
+	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
 		intel_crtc_planes_update_noarm(NULL, state, crtc);
 }
 
@@ -6738,7 +6739,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (new_crtc_state->use_dsb) {
+	if (new_crtc_state->use_flipq) {
+		intel_flipq_enable(new_crtc_state);
+
+		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event);
+
+		intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0,
+				new_crtc_state->dsb_commit);
+	} else if (new_crtc_state->use_dsb) {
 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
 
 		intel_dsb_commit(new_crtc_state->dsb_commit, false);
@@ -7176,7 +7184,19 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
 		return;
 
 	/* FIXME deal with everything */
+	new_crtc_state->use_flipq =
+		display->params.enable_flipq &&
+		DISPLAY_VER(display) >= 20 &&
+		display->dmc.dmc &&
+		!new_crtc_state->do_async_flip &&
+		!new_crtc_state->vrr.enable &&
+		!new_crtc_state->has_psr &&
+		!intel_crtc_needs_modeset(new_crtc_state) &&
+		!intel_crtc_needs_fastset(new_crtc_state) &&
+		!intel_crtc_needs_color_update(new_crtc_state);
+
 	new_crtc_state->use_dsb =
+		!new_crtc_state->use_flipq &&
 		!new_crtc_state->do_async_flip &&
 		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
 		!intel_crtc_needs_modeset(new_crtc_state) &&
@@ -7192,7 +7212,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
+	if (!new_crtc_state->use_flipq &&
+	    !new_crtc_state->use_dsb &&
+	    !new_crtc_state->dsb_color_vblank)
 		return;
 
 	/*
@@ -7201,14 +7223,16 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	 * Double that for pipe stuff and other overhead.
 	 */
 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
-						       new_crtc_state->use_dsb ? 1024 : 16);
+						       new_crtc_state->use_dsb ||
+						       new_crtc_state->use_flipq ? 1024 : 16);
 	if (!new_crtc_state->dsb_commit) {
+		new_crtc_state->use_flipq = false;
 		new_crtc_state->use_dsb = false;
 		intel_color_cleanup_commit(new_crtc_state);
 		return;
 	}
 
-	if (new_crtc_state->use_dsb) {
+	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7223,7 +7247,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
 						     state, crtc);
 
-		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
+		if (new_crtc_state->use_dsb)
+			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
 
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_arm(new_crtc_state->dsb_commit,
@@ -7238,21 +7263,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		if (DISPLAY_VER(display) >= 9)
 			skl_detach_scalers(new_crtc_state->dsb_commit,
 					   new_crtc_state);
-
-		if (!new_crtc_state->dsb_color_vblank) {
-			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
-
-			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
-			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
-			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
-			intel_dsb_interrupt(new_crtc_state->dsb_commit);
-		}
 	}
 
 	if (new_crtc_state->dsb_color_vblank)
 		intel_dsb_chain(state, new_crtc_state->dsb_commit,
 				new_crtc_state->dsb_color_vblank, true);
 
+	if (new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) {
+		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+
+		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
+		intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
+		intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
+		intel_dsb_interrupt(new_crtc_state->dsb_commit);
+	}
+
 	intel_dsb_finish(new_crtc_state->dsb_commit);
 }
 
@@ -7397,6 +7422,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
 			intel_vrr_check_push_sent(NULL, new_crtc_state);
+
+		if (new_crtc_state->use_flipq)
+			intel_flipq_disable(new_crtc_state);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index c4f1ab43fc0c..75316247ee8a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -62,6 +62,9 @@ intel_display_param_named_unsafe(enable_dpt, bool, 0400,
 intel_display_param_named_unsafe(enable_dsb, bool, 0400,
 	"Enable display state buffer (DSB) (default: true)");
 
+intel_display_param_named_unsafe(enable_flipq, bool, 0400,
+	"Enable DMC flip queue (default: false)");
+
 intel_display_param_named_unsafe(enable_sagv, bool, 0400,
 	"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 5317138e6044..784e6bae8615 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -31,6 +31,7 @@ struct drm_printer;
 	param(int, enable_dc, -1, 0400) \
 	param(bool, enable_dpt, true, 0400) \
 	param(bool, enable_dsb, true, 0600) \
+	param(bool, enable_flipq, false, 0600) \
 	param(bool, enable_sagv, true, 0600) \
 	param(int, disable_power_well, -1, 0400) \
 	param(bool, enable_ips, true, 0600) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2f3fdf292d88..dd87099823d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1299,6 +1299,7 @@ struct intel_crtc_state {
 	/* For DSB based pipe updates */
 	struct intel_dsb *dsb_color_vblank, *dsb_commit;
 	bool use_dsb;
+	bool use_flipq;
 
 	u32 psr2_man_track_ctl;
 
@@ -1406,6 +1407,8 @@ struct intel_crtc {
 	struct drm_pending_vblank_event *flip_done_event;
 	/* armed event for DSB based updates */
 	struct drm_pending_vblank_event *dsb_event;
+	/* armed event for flip queue based updates */
+	struct drm_pending_vblank_event *flipq_event;
 
 	/* Access to these should be protected by display->irq.lock. */
 	bool cpu_fifo_underrun_disabled;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2ff62740833c..fa2df7582062 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -502,7 +502,8 @@ static u32 pipedmc_interrupt_mask(struct intel_display *display)
 	 * triggering it during the first DC state transition. Figure
 	 * out what is going on...
 	 */
-	return PIPEDMC_GTT_FAULT |
+	return PIPEDMC_FLIPQ_PROG_DONE |
+		PIPEDMC_GTT_FAULT |
 		PIPEDMC_ATS_FAULT;
 }
 
@@ -1487,6 +1488,23 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 		tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
 		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
 
+		if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
+			spin_lock(&display->drm->event_lock);
+
+			if (crtc->flipq_event) {
+				/*
+				 * Update vblank counter/timestamp in case it
+				 * hasn't been done yet for this frame.
+				 */
+				drm_crtc_accurate_vblank_count(&crtc->base);
+
+				drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event);
+				crtc->flipq_event = NULL;
+			}
+
+			spin_unlock(&display->drm->event_lock);
+		}
+
 		if (tmp & PIPEDMC_ATS_FAULT)
 			drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n",
 					    crtc->base.base.id, crtc->base.name);
-- 
2.49.0

RE: [PATCH v2 08/12] drm/i915/flipq: Implement flipq queue based commit path

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Monday, May 19, 2025 10:39 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH v2 08/12] drm/i915/flipq: Implement flipq queue based commit
> path

Nit: Drop the redundant q from flipq

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Support commits via the flip queue (as opposed to DSB or MMIO).
> 
> As it's somewhat unknown if we can actually use it is currently gated behind the
> new use_flipq modparam, which defaults to disabled.
> 
> The implementation has a bunch of limitations that would need real though to
> solve:
> - disabled when PSR is used
> - disabled when VRR is used
> - color management updates not performed via the flip queue
> 
> v2: Don't use flip queue if there is no dmc
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 64 +++++++++++++------
>  .../drm/i915/display/intel_display_params.c   |  3 +
>  .../drm/i915/display/intel_display_params.h   |  1 +
>  .../drm/i915/display/intel_display_types.h    |  3 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 20 +++++-
>  5 files changed, 72 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1b09f8ae76ff..8b0eecfd4b16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -93,6 +93,7 @@
>  #include "intel_fbc.h"
>  #include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
> +#include "intel_flipq.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_hdmi.h"
>  #include "intel_hotplug.h"
> @@ -6610,7 +6611,7 @@ static void commit_pipe_pre_planes(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
> 
> -	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
> +	drm_WARN_ON(display->drm, new_crtc_state->use_dsb ||
> +new_crtc_state->use_flipq);
> 
>  	/*
>  	 * During modesets pipe configuration was programmed as the @@ -
> 6639,7 +6640,7 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
>  	const struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
> +	drm_WARN_ON(display->drm, new_crtc_state->use_dsb ||
> +new_crtc_state->use_flipq);
> 
>  	/*
>  	 * Disable the scaler(s) after the plane(s) so that we don't @@ -6723,10
> +6724,10 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
> 
>  	if (!modeset &&
>  	    intel_crtc_needs_color_update(new_crtc_state) &&
> -	    !new_crtc_state->use_dsb)
> +	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
>  		intel_color_commit_noarm(NULL, new_crtc_state);
> 
> -	if (!new_crtc_state->use_dsb)
> +	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
>  		intel_crtc_planes_update_noarm(NULL, state, crtc);  }
> 
> @@ -6738,7 +6739,14 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	if (new_crtc_state->use_dsb) {
> +	if (new_crtc_state->use_flipq) {
> +		intel_flipq_enable(new_crtc_state);
> +
> +		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc-
> >flipq_event);
> +
> +		intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0,
> +				new_crtc_state->dsb_commit);
> +	} else if (new_crtc_state->use_dsb) {
>  		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc-
> >dsb_event);
> 
>  		intel_dsb_commit(new_crtc_state->dsb_commit, false); @@ -
> 7176,7 +7184,19 @@ static void intel_atomic_dsb_prepare(struct
> intel_atomic_state *state,
>  		return;
> 
>  	/* FIXME deal with everything */
> +	new_crtc_state->use_flipq =
> +		display->params.enable_flipq &&
> +		DISPLAY_VER(display) >= 20 &&
> +		display->dmc.dmc &&
> +		!new_crtc_state->do_async_flip &&
> +		!new_crtc_state->vrr.enable &&
> +		!new_crtc_state->has_psr &&
> +		!intel_crtc_needs_modeset(new_crtc_state) &&
> +		!intel_crtc_needs_fastset(new_crtc_state) &&
> +		!intel_crtc_needs_color_update(new_crtc_state);
> +
>  	new_crtc_state->use_dsb =
> +		!new_crtc_state->use_flipq &&
>  		!new_crtc_state->do_async_flip &&
>  		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
>  		!intel_crtc_needs_modeset(new_crtc_state) && @@ -7192,7
> +7212,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
> +	if (!new_crtc_state->use_flipq &&
> +	    !new_crtc_state->use_dsb &&
> +	    !new_crtc_state->dsb_color_vblank)
>  		return;
> 
>  	/*
> @@ -7201,14 +7223,16 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  	 * Double that for pipe stuff and other overhead.
>  	 */
>  	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc,
> INTEL_DSB_0,
> -						       new_crtc_state->use_dsb ?
> 1024 : 16);
> +						       new_crtc_state->use_dsb
> ||
> +						       new_crtc_state->use_flipq
> ? 1024 : 16);
>  	if (!new_crtc_state->dsb_commit) {
> +		new_crtc_state->use_flipq = false;
>  		new_crtc_state->use_dsb = false;
>  		intel_color_cleanup_commit(new_crtc_state);
>  		return;
>  	}
> 
> -	if (new_crtc_state->use_dsb) {
> +	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
>  		if (intel_crtc_needs_color_update(new_crtc_state))
>  			intel_color_commit_noarm(new_crtc_state-
> >dsb_commit,
>  						 new_crtc_state);
> @@ -7223,7 +7247,8 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  		intel_psr_trigger_frame_change_event(new_crtc_state-
> >dsb_commit,
>  						     state, crtc);
> 
> -		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
> +		if (new_crtc_state->use_dsb)
> +			intel_dsb_vblank_evade(state, new_crtc_state-
> >dsb_commit);
> 
>  		if (intel_crtc_needs_color_update(new_crtc_state))
>  			intel_color_commit_arm(new_crtc_state->dsb_commit,
> @@ -7238,21 +7263,21 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  		if (DISPLAY_VER(display) >= 9)
>  			skl_detach_scalers(new_crtc_state->dsb_commit,
>  					   new_crtc_state);
> -
> -		if (!new_crtc_state->dsb_color_vblank) {
> -			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit,
> 1);
> -
> -			intel_vrr_send_push(new_crtc_state->dsb_commit,
> new_crtc_state);
> -			intel_dsb_wait_vblank_delay(state, new_crtc_state-
> >dsb_commit);
> -			intel_vrr_check_push_sent(new_crtc_state-
> >dsb_commit, new_crtc_state);
> -			intel_dsb_interrupt(new_crtc_state->dsb_commit);
> -		}
>  	}
> 
>  	if (new_crtc_state->dsb_color_vblank)
>  		intel_dsb_chain(state, new_crtc_state->dsb_commit,
>  				new_crtc_state->dsb_color_vblank, true);
> 
> +	if (new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) {
> +		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> +
> +		intel_vrr_send_push(new_crtc_state->dsb_commit,
> new_crtc_state);
> +		intel_dsb_wait_vblank_delay(state, new_crtc_state-
> >dsb_commit);
> +		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> new_crtc_state);
> +		intel_dsb_interrupt(new_crtc_state->dsb_commit);
> +	}
> +
>  	intel_dsb_finish(new_crtc_state->dsb_commit);
>  }
> 
> @@ -7397,6 +7422,9 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> 
>  		if (!state->base.legacy_cursor_update && !new_crtc_state-
> >use_dsb)
>  			intel_vrr_check_push_sent(NULL, new_crtc_state);
> +
> +		if (new_crtc_state->use_flipq)
> +			intel_flipq_disable(new_crtc_state);
>  	}
> 
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
> b/drivers/gpu/drm/i915/display/intel_display_params.c
> index c4f1ab43fc0c..75316247ee8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -62,6 +62,9 @@ intel_display_param_named_unsafe(enable_dpt, bool,
> 0400,  intel_display_param_named_unsafe(enable_dsb, bool, 0400,
>  	"Enable display state buffer (DSB) (default: true)");
> 
> +intel_display_param_named_unsafe(enable_flipq, bool, 0400,
> +	"Enable DMC flip queue (default: false)");
> +
>  intel_display_param_named_unsafe(enable_sagv, bool, 0400,
>  	"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h
> b/drivers/gpu/drm/i915/display/intel_display_params.h
> index 5317138e6044..784e6bae8615 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -31,6 +31,7 @@ struct drm_printer;
>  	param(int, enable_dc, -1, 0400) \
>  	param(bool, enable_dpt, true, 0400) \
>  	param(bool, enable_dsb, true, 0600) \
> +	param(bool, enable_flipq, false, 0600) \
>  	param(bool, enable_sagv, true, 0600) \
>  	param(int, disable_power_well, -1, 0400) \
>  	param(bool, enable_ips, true, 0600) \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 2f3fdf292d88..dd87099823d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1299,6 +1299,7 @@ struct intel_crtc_state {
>  	/* For DSB based pipe updates */
>  	struct intel_dsb *dsb_color_vblank, *dsb_commit;
>  	bool use_dsb;
> +	bool use_flipq;
> 
>  	u32 psr2_man_track_ctl;
> 
> @@ -1406,6 +1407,8 @@ struct intel_crtc {
>  	struct drm_pending_vblank_event *flip_done_event;
>  	/* armed event for DSB based updates */
>  	struct drm_pending_vblank_event *dsb_event;
> +	/* armed event for flip queue based updates */
> +	struct drm_pending_vblank_event *flipq_event;
> 
>  	/* Access to these should be protected by display->irq.lock. */
>  	bool cpu_fifo_underrun_disabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 2ff62740833c..fa2df7582062 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -502,7 +502,8 @@ static u32 pipedmc_interrupt_mask(struct intel_display
> *display)
>  	 * triggering it during the first DC state transition. Figure
>  	 * out what is going on...
>  	 */
> -	return PIPEDMC_GTT_FAULT |
> +	return PIPEDMC_FLIPQ_PROG_DONE |
> +		PIPEDMC_GTT_FAULT |
>  		PIPEDMC_ATS_FAULT;
>  }
> 
> @@ -1487,6 +1488,23 @@ void intel_pipedmc_irq_handler(struct intel_display
> *display, enum pipe pipe)
>  		tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe));
>  		intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp);
> 
> +		if (tmp & PIPEDMC_FLIPQ_PROG_DONE) {
> +			spin_lock(&display->drm->event_lock);
> +
> +			if (crtc->flipq_event) {
> +				/*
> +				 * Update vblank counter/timestamp in case it
> +				 * hasn't been done yet for this frame.
> +				 */
> +				drm_crtc_accurate_vblank_count(&crtc->base);
> +
> +				drm_crtc_send_vblank_event(&crtc->base,
> crtc->flipq_event);
> +				crtc->flipq_event = NULL;
> +			}
> +
> +			spin_unlock(&display->drm->event_lock);
> +		}
> +
>  		if (tmp & PIPEDMC_ATS_FAULT)
>  			drm_err_ratelimited(display->drm, "[CRTC:%d:%s]
> PIPEDMC ATS fault\n",
>  					    crtc->base.base.id, crtc-
> >base.name);
> --
> 2.49.0

[PATCH 09/12] drm/i915/flipq: Implement Wa_18034343758

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Implement the driver side of Wa_18034343758, which is supposed to
prevent the DSB and DMC from accessing registers in parallel, and
thus potentially corrupting the registers due to a hardware issue
(which should be fixed in PTL-B0).

The w/a sequence goes as follows:
DMC starts the DSB
 |                 \
DMC halts itself    | DSB waits a while for DMC to have time to halt
 .                  | DSB executes normally
 .		    | DSB unhalts the DMC at the very end
 .             	   /
DMC resumes execution

TODO: figure out if PTL-B0+ firmware still implements the w/a

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  8 ++++++++
 drivers/gpu/drm/i915/display/intel_flipq.c   | 10 ++++++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3a42536247d8..76ed34adc08d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7232,6 +7232,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	}
 
 	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
+		/* Wa_18034343758 */
+		if (new_crtc_state->use_flipq)
+			intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit);
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7262,6 +7266,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		if (DISPLAY_VER(display) >= 9)
 			skl_detach_scalers(new_crtc_state->dsb_commit,
 					   new_crtc_state);
+
+		/* Wa_18034343758 */
+		if (new_crtc_state->use_flipq)
+			intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc);
 	}
 
 	if (new_crtc_state->dsb_color_vblank)
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
index 8677929b7ece..c4b4ecd44eb2 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.c
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -304,3 +304,13 @@ void intel_flipq_add(struct intel_crtc *crtc,
 
 	intel_flipq_sw_dmc_wake(crtc);
 }
+
+void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb)
+{
+	intel_dsb_wait_usec(dsb, 2);
+}
+
+void intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	intel_dsb_reg_write(dsb, PIPEDMC_CTL(crtc->pipe), 0);
+}
-- 
2.49.0

RE: [PATCH 09/12] drm/i915/flipq: Implement Wa_18034343758

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 09/12] drm/i915/flipq: Implement Wa_18034343758
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Implement the driver side of Wa_18034343758, which is supposed to prevent the
> DSB and DMC from accessing registers in parallel, and thus potentially corrupting
> the registers due to a hardware issue (which should be fixed in PTL-B0).
> 
> The w/a sequence goes as follows:
> DMC starts the DSB
>  |                 \
> DMC halts itself    | DSB waits a while for DMC to have time to halt
>  .                  | DSB executes normally
>  .		    | DSB unhalts the DMC at the very end
>  .             	   /
> DMC resumes execution
> 
> TODO: figure out if PTL-B0+ firmware still implements the w/a

Platform checks can be added later for the applicable platforms.

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  8 ++++++++
>  drivers/gpu/drm/i915/display/intel_flipq.c   | 10 ++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3a42536247d8..76ed34adc08d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7232,6 +7232,10 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  	}
> 
>  	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
> +		/* Wa_18034343758 */
> +		if (new_crtc_state->use_flipq)
> +			intel_flipq_wait_dmc_halt(new_crtc_state-
> >dsb_commit);
> +
>  		if (intel_crtc_needs_color_update(new_crtc_state))
>  			intel_color_commit_noarm(new_crtc_state-
> >dsb_commit,
>  						 new_crtc_state);
> @@ -7262,6 +7266,10 @@ static void intel_atomic_dsb_finish(struct
> intel_atomic_state *state,
>  		if (DISPLAY_VER(display) >= 9)
>  			skl_detach_scalers(new_crtc_state->dsb_commit,
>  					   new_crtc_state);
> +
> +		/* Wa_18034343758 */
> +		if (new_crtc_state->use_flipq)
> +			intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit,
> crtc);
>  	}
> 
>  	if (new_crtc_state->dsb_color_vblank)
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> index 8677929b7ece..c4b4ecd44eb2 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -304,3 +304,13 @@ void intel_flipq_add(struct intel_crtc *crtc,
> 
>  	intel_flipq_sw_dmc_wake(crtc);
>  }
> +
> +void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb) {
> +	intel_dsb_wait_usec(dsb, 2);
> +}
> +
> +void intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc
> +*crtc) {
> +	intel_dsb_reg_write(dsb, PIPEDMC_CTL(crtc->pipe), 0); }
> --
> 2.49.0

[PATCH 10/12] drm/i915/flipq: Implement Wa_16018781658 for LNL-A0

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The normal flip queue completion interrupt doesn't work on LNL-A0,
and instead the firmware implements a workaround via the delayed
vblank event handler. Implement said workaround on the driver side
by enabling the appropriate event and handling the result interrupt
vector value in the PIPEDMC irq handler.

Included here just for reference since LNL-A0 is pre-production
and we don't actually care about it anymore.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c   | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_flipq.c | 12 ++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 10d1be68df79..cd024254db7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1516,9 +1516,26 @@ void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe)
 	}
 
 	tmp = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK;
-	if (tmp)
+	/* Wa_16018781658 */
+	if (tmp == PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE) {
+		spin_lock(&display->drm->event_lock);
+
+		if (crtc->flipq_event) {
+			/*
+			 * Update vblank counter/timestamp in case it
+			 * hasn't been done yet for this frame.
+			 */
+			drm_crtc_accurate_vblank_count(&crtc->base);
+
+			drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event);
+			crtc->flipq_event = NULL;
+		}
+
+		spin_unlock(&display->drm->event_lock);
+	} else if (tmp) {
 		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n",
 			crtc->base.base.id, crtc->base.name, tmp);
+	}
 }
 
 void intel_pipedmc_enable_event(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
index c4b4ecd44eb2..fdda8d71c182 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.c
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -215,6 +215,14 @@ void intel_flipq_enable(const struct intel_crtc_state *crtc_state)
 
 	intel_pipedmc_enable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
 
+	/*
+	 * Wa_16018781658
+	 * PIPEDMC_FPQ_CTL2 bit 1 isn't working, firmware implements
+	 * a workaround via the delayed vblank handler.
+	 */
+	if (display->platform.lunarlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
+		intel_pipedmc_enable_event(crtc, PIPEDMC_EVENT_DELAYED_VBLANK);
+
 	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), PIPEDMC_FQ_CTRL_ENABLE);
 }
 
@@ -225,6 +233,10 @@ void intel_flipq_disable(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
 
+	/* Wa_16018781658 */
+	if (display->platform.lunarlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
+		intel_pipedmc_disable_event(crtc, PIPEDMC_EVENT_DELAYED_VBLANK);
+
 	intel_pipedmc_disable_event(crtc, PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
 
 	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
-- 
2.49.0

RE: [PATCH 10/12] drm/i915/flipq: Implement Wa_16018781658 for LNL-A0

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 10/12] drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The normal flip queue completion interrupt doesn't work on LNL-A0, and instead
> the firmware implements a workaround via the delayed vblank event handler.
> Implement said workaround on the driver side by enabling the appropriate event
> and handling the result interrupt vector value in the PIPEDMC irq handler.
> 
> Included here just for reference since LNL-A0 is pre-production and we don't
> actually care about it anymore.

Looks Good to me, but may not need to be merged upstream.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c   | 19 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_flipq.c | 12 ++++++++++++
>  2 files changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 10d1be68df79..cd024254db7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1516,9 +1516,26 @@ void intel_pipedmc_irq_handler(struct intel_display
> *display, enum pipe pipe)
>  	}
> 
>  	tmp = intel_de_read(display, PIPEDMC_STATUS(pipe)) &
> PIPEDMC_INT_VECTOR_MASK;
> -	if (tmp)
> +	/* Wa_16018781658 */
> +	if (tmp == PIPEDMC_INT_VECTOR_FLIPQ_PROG_DONE) {
> +		spin_lock(&display->drm->event_lock);
> +
> +		if (crtc->flipq_event) {
> +			/*
> +			 * Update vblank counter/timestamp in case it
> +			 * hasn't been done yet for this frame.
> +			 */
> +			drm_crtc_accurate_vblank_count(&crtc->base);
> +
> +			drm_crtc_send_vblank_event(&crtc->base, crtc-
> >flipq_event);
> +			crtc->flipq_event = NULL;
> +		}
> +
> +		spin_unlock(&display->drm->event_lock);
> +	} else if (tmp) {
>  		drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt
> vector 0x%x\n",
>  			crtc->base.base.id, crtc->base.name, tmp);
> +	}
>  }
> 
>  void intel_pipedmc_enable_event(struct intel_crtc *crtc, diff --git
> a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> index c4b4ecd44eb2..fdda8d71c182 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -215,6 +215,14 @@ void intel_flipq_enable(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_pipedmc_enable_event(crtc,
> PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> 
> +	/*
> +	 * Wa_16018781658
> +	 * PIPEDMC_FPQ_CTL2 bit 1 isn't working, firmware implements
> +	 * a workaround via the delayed vblank handler.
> +	 */
> +	if (display->platform.lunarlake && IS_DISPLAY_STEP(display, STEP_A0,
> STEP_B0))
> +		intel_pipedmc_enable_event(crtc,
> PIPEDMC_EVENT_DELAYED_VBLANK);
> +
>  	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe),
> PIPEDMC_FQ_CTRL_ENABLE);  }
> 
> @@ -225,6 +233,10 @@ void intel_flipq_disable(const struct intel_crtc_state
> *crtc_state)
> 
>  	intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0);
> 
> +	/* Wa_16018781658 */
> +	if (display->platform.lunarlake && IS_DISPLAY_STEP(display, STEP_A0,
> STEP_B0))
> +		intel_pipedmc_disable_event(crtc,
> PIPEDMC_EVENT_DELAYED_VBLANK);
> +
>  	intel_pipedmc_disable_event(crtc,
> PIPEDMC_EVENT_SCANLINE_INRANGE_FQ_TRIGGER);
> 
>  	intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), 0);
> --
> 2.49.0

[PATCH 11/12] drm/i915/flipq: Add intel_flipq_dump()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a function for dumping the entries of a specific flip queue.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_flipq.c | 46 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_flipq.h |  2 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
index fdda8d71c182..82a7996e7005 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.c
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -147,6 +147,52 @@ static void intel_flipq_sw_dmc_wake(struct intel_crtc *crtc)
 	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe), PIPEDMC_SW_DMC_WAKE);
 }
 
+void intel_flipq_dump(struct intel_crtc *crtc,
+		      enum intel_flipq_id flipq_id)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
+	u32 tmp;
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s] FQ %d @ 0x%x: ",
+		    crtc->base.base.id, crtc->base.name, flipq_id,
+		    flipq->start_mmioaddr);
+	for (int i = 0 ; i < intel_flipq_size_dw(flipq_id); i++) {
+		printk(KERN_CONT " 0x%08x",
+		       intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i)));
+		if (i % intel_flipq_elem_size_dw(flipq_id) == intel_flipq_elem_size_dw(flipq_id) - 1)
+			printk(KERN_CONT "\n");
+	}
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s] FQ %d: chp=0x%x, hp=0x%x\n",
+		    crtc->base.base.id, crtc->base.name, flipq_id,
+		    intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)),
+		    intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id)));
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s] FQ %d: current head %d\n",
+		    crtc->base.base.id, crtc->base.name, flipq_id,
+		    intel_flipq_current_head(crtc, flipq_id));
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s] flip queue timestamp: 0x%x\n",
+		    crtc->base.base.id, crtc->base.name,
+		    intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));
+
+	tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
+
+	drm_dbg_kms(display->drm,
+		    "[CRTC:%d:%s] flip queue atomic tails: P3 %d, P2 %d, P1 %d, G %d, F %d\n",
+		    crtc->base.base.id, crtc->base.name,
+		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),
+		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),
+		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),
+		    REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),
+		    REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp));
+}
+
 static int cdclk_factor(struct intel_display *display)
 {
 	if (DISPLAY_VER(display) >= 30)
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h b/drivers/gpu/drm/i915/display/intel_flipq.h
index 8483c93ecdb3..0179719df8a3 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.h
+++ b/drivers/gpu/drm/i915/display/intel_flipq.h
@@ -27,6 +27,8 @@ void intel_flipq_add(struct intel_crtc *crtc,
 		     unsigned int pts,
 		     enum intel_dsb_id dsb_id,
 		     struct intel_dsb *dsb);
+void intel_flipq_dump(struct intel_crtc *crtc,
+		      enum intel_flipq_id flip_queue_id);
 void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb);
 void intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
 
-- 
2.49.0

RE: [PATCH 11/12] drm/i915/flipq: Add intel_flipq_dump()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 11/12] drm/i915/flipq: Add intel_flipq_dump()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a function for dumping the entries of a specific flip queue.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_flipq.c | 46 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_flipq.h |  2 +
>  2 files changed, 48 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c
> b/drivers/gpu/drm/i915/display/intel_flipq.c
> index fdda8d71c182..82a7996e7005 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.c
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.c
> @@ -147,6 +147,52 @@ static void intel_flipq_sw_dmc_wake(struct intel_crtc
> *crtc)
>  	intel_de_write(display, PIPEDMC_FPQ_CTL1(crtc->pipe),
> PIPEDMC_SW_DMC_WAKE);  }
> 
> +void intel_flipq_dump(struct intel_crtc *crtc,
> +		      enum intel_flipq_id flipq_id)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_flipq *flipq = &crtc->flipq[flipq_id];
> +	u32 tmp;
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d @ 0x%x: ",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    flipq->start_mmioaddr);
> +	for (int i = 0 ; i < intel_flipq_size_dw(flipq_id); i++) {
> +		printk(KERN_CONT " 0x%08x",
> +		       intel_de_read(display, PIPEDMC_FQ_RAM(flipq-
> >start_mmioaddr, i)));
> +		if (i % intel_flipq_elem_size_dw(flipq_id) ==
> intel_flipq_elem_size_dw(flipq_id) - 1)
> +			printk(KERN_CONT "\n");
> +	}
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d: chp=0x%x, hp=0x%x\n",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe,
> flipq_id)),
> +		    intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe,
> flipq_id)));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] FQ %d: current head %d\n",
> +		    crtc->base.base.id, crtc->base.name, flipq_id,
> +		    intel_flipq_current_head(crtc, flipq_id));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] flip queue timestamp: 0x%x\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)));
> +
> +	tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe));
> +
> +	drm_dbg_kms(display->drm,
> +		    "[CRTC:%d:%s] flip queue atomic tails: P3 %d, P2 %d, P1 %d, G
> %d, F %d\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_3_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_2_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_PLANEQ_1_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_GENERALQ_TP_MASK, tmp),
> +		    REG_FIELD_GET(PIPEDMC_FPQ_FASTQ_TP_MASK, tmp)); }
> +
>  static int cdclk_factor(struct intel_display *display)  {
>  	if (DISPLAY_VER(display) >= 30)
> diff --git a/drivers/gpu/drm/i915/display/intel_flipq.h
> b/drivers/gpu/drm/i915/display/intel_flipq.h
> index 8483c93ecdb3..0179719df8a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_flipq.h
> +++ b/drivers/gpu/drm/i915/display/intel_flipq.h
> @@ -27,6 +27,8 @@ void intel_flipq_add(struct intel_crtc *crtc,
>  		     unsigned int pts,
>  		     enum intel_dsb_id dsb_id,
>  		     struct intel_dsb *dsb);
> +void intel_flipq_dump(struct intel_crtc *crtc,
> +		      enum intel_flipq_id flip_queue_id);
>  void intel_flipq_wait_dmc_halt(struct intel_dsb *dsb);  void
> intel_flipq_unhalt_dmc(struct intel_dsb *dsb, struct intel_crtc *crtc);
> 
> --
> 2.49.0

[PATCH 12/12] drm/i915/flipq: Enable flipq by default for testing

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Flip on the enable_flipq modparam to see if CI blows up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_params.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
index 75316247ee8a..2883663e06ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -63,7 +63,7 @@ intel_display_param_named_unsafe(enable_dsb, bool, 0400,
 	"Enable display state buffer (DSB) (default: true)");
 
 intel_display_param_named_unsafe(enable_flipq, bool, 0400,
-	"Enable DMC flip queue (default: false)");
+	"Enable DMC flip queue (default: true)");
 
 intel_display_param_named_unsafe(enable_sagv, bool, 0400,
 	"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
index 784e6bae8615..600bff5cddda 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -31,7 +31,7 @@ struct drm_printer;
 	param(int, enable_dc, -1, 0400) \
 	param(bool, enable_dpt, true, 0400) \
 	param(bool, enable_dsb, true, 0600) \
-	param(bool, enable_flipq, false, 0600) \
+	param(bool, enable_flipq, true, 0600) \
 	param(bool, enable_sagv, true, 0600) \
 	param(int, disable_power_well, -1, 0400) \
 	param(bool, enable_ips, true, 0600) \
-- 
2.49.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915/flipq: Rough flip queue implementation

[Patchwork]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation
URL   : https://patchwork.freedesktop.org/series/149110/
State : warning

== Summary ==

Error: dim checkpatch failed
bfc35bdaa441 drm/i915/dsb: Extract intel_dsb_ins_align()
1250cfb00d9f drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()
a9e8bcc41081 drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
e8cf6a4fb5f6 drm/i915/dsb: Extract intel_dsb_{head,tail}()
63c982ea1812 drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()
5a3ae628d4b3 drm/i915/dmc: Define flip queue related PIPEDMC registers
-:59: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:322:
+#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)

-:66: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:329:
+#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)

-:80: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:343:
+#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)

-:84: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:347:
+#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)

-:88: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:351:
+#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)

-:94: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:357:
+#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)

-:98: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:361:
+#define   PIPEDMC_SCANLINE_LOWER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))

-:102: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#102: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:365:
+#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)

-:104: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#104: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:367:
+#define   PIPEDMC_SCANLINE_UPPER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))

-:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#106: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:369:
+#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
+			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
+			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
+	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
+				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
+				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
+				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
+				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))

-:158: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#158: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:421:
+							  _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \

-:159: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:422:
+							  _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \

-:160: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:423:
+							  _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \

-:169: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#169: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:432:
+#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)

-:191: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#191: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:543:
+#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:193: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#193: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:545:
+#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:195: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:547:
+#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:197: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#197: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:549:
+#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

total: 0 errors, 17 warnings, 1 checks, 194 lines checked
f625e18093e6 drm/i915/flipq: Provide the nuts and bolts code for flip queue
-:37: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#37: 
      need to think what to about the cdclk dependency on the execution time

-:261: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#261: 
new file mode 100644

-:287: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'flipq_id' - possible side-effects?
#287: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:22:
+#define for_each_flipq(flipq_id) \
+	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ; (flipq_id)++)

-:354: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#354: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:89:
+		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id);

-:519: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#519: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:254:
+					       intel_flipq_elem_size_dw(flipq->flipq_id) + i), data);

total: 0 errors, 4 warnings, 1 checks, 525 lines checked
6488c5c1708d drm/i915/flipq: Implement flipq queue based commit path
-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:66:
+intel_display_param_named_unsafe(enable_flipq, bool, 0400,
+	"Enable DMC flip queue (default: false)");

total: 0 errors, 0 warnings, 1 checks, 207 lines checked
cc06d77a5509 drm/i915/flipq: Implement Wa_18034343758
5124d147ad7d drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
d55abf62553b drm/i915/flipq: Add intel_flipq_dump()
-:33: WARNING:PREFER_PR_LEVEL: Prefer [subsystem eg: netdev]_cont([subsystem]dev, ... then dev_cont(dev, ... then pr_cont(...  to printk(KERN_CONT ...
#33: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:162:
+		printk(KERN_CONT " 0x%08x",

-:33: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where feasible
#33: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:162:
+		printk(KERN_CONT " 0x%08x",

-:35: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:164:
+		if (i % intel_flipq_elem_size_dw(flipq_id) == intel_flipq_elem_size_dw(flipq_id) - 1)

-:36: WARNING:PREFER_PR_LEVEL: Prefer [subsystem eg: netdev]_cont([subsystem]dev, ... then dev_cont(dev, ... then pr_cont(...  to printk(KERN_CONT ...
#36: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:165:
+			printk(KERN_CONT "\n");

-:36: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where feasible
#36: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:165:
+			printk(KERN_CONT "\n");

total: 0 errors, 5 warnings, 0 checks, 60 lines checked
55a4275b6153 drm/i915/flipq: Enable flipq by default for testing

✗ Fi.CI.SPARSE: warning for drm/i915/flipq: Rough flip queue implementation

[Patchwork]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation
URL   : https://patchwork.freedesktop.org/series/149110/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ i915.CI.BAT: failure for drm/i915/flipq: Rough flip queue implementation

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 13071 bytes --]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation
URL   : https://patchwork.freedesktop.org/series/149110/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16557 -> Patchwork_149110v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_149110v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_149110v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/index.html

Participating hosts (45 -> 45)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_149110v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-ilk-650:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-ilk-650/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-ilk-650/igt@i915_module_load@load.html
    - fi-blb-e6850:       [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-blb-e6850/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-blb-e6850/igt@i915_module_load@load.html
    - fi-bsw-n3050:       [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-bsw-n3050/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-bsw-n3050/igt@i915_module_load@load.html
    - bat-adlp-6:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-adlp-6/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-adlp-6/igt@i915_module_load@load.html
    - bat-arlh-2:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-arlh-2/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-arlh-2/igt@i915_module_load@load.html
    - fi-rkl-11600:       [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-rkl-11600/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-rkl-11600/igt@i915_module_load@load.html
    - fi-skl-6600u:       [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-skl-6600u/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-skl-6600u/igt@i915_module_load@load.html
    - bat-arlh-3:         [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-arlh-3/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-arlh-3/igt@i915_module_load@load.html
    - fi-pnv-d510:        [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-pnv-d510/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-pnv-d510/igt@i915_module_load@load.html
    - bat-dg1-7:          [PASS][19] -> [ABORT][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg1-7/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg1-7/igt@i915_module_load@load.html
    - bat-dg2-13:         [PASS][21] -> [ABORT][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg2-13/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg2-13/igt@i915_module_load@load.html
    - fi-glk-j4005:       [PASS][23] -> [ABORT][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-glk-j4005/igt@i915_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-glk-j4005/igt@i915_module_load@load.html
    - bat-adlp-9:         [PASS][25] -> [ABORT][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-adlp-9/igt@i915_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-adlp-9/igt@i915_module_load@load.html
    - bat-twl-2:          [PASS][27] -> [ABORT][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-twl-2/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-twl-2/igt@i915_module_load@load.html
    - bat-dg2-11:         [PASS][29] -> [ABORT][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg2-11/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg2-11/igt@i915_module_load@load.html
    - bat-rpls-4:         [PASS][31] -> [ABORT][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-rpls-4/igt@i915_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-rpls-4/igt@i915_module_load@load.html
    - fi-kbl-7567u:       [PASS][33] -> [ABORT][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-kbl-7567u/igt@i915_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-kbl-7567u/igt@i915_module_load@load.html
    - fi-cfl-8700k:       [PASS][35] -> [ABORT][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-cfl-8700k/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-cfl-8700k/igt@i915_module_load@load.html
    - bat-twl-1:          [PASS][37] -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-twl-1/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-twl-1/igt@i915_module_load@load.html
    - fi-kbl-8809g:       [PASS][39] -> [ABORT][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-kbl-8809g/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-kbl-8809g/igt@i915_module_load@load.html
    - bat-apl-1:          [PASS][41] -> [ABORT][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-apl-1/igt@i915_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-apl-1/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][43] -> [ABORT][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg2-14/igt@i915_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg2-14/igt@i915_module_load@load.html
    - fi-elk-e7500:       [PASS][45] -> [ABORT][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-elk-e7500/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-elk-e7500/igt@i915_module_load@load.html
    - fi-bsw-nick:        [PASS][47] -> [ABORT][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-bsw-nick/igt@i915_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-bsw-nick/igt@i915_module_load@load.html
    - bat-kbl-2:          [PASS][49] -> [ABORT][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-kbl-2/igt@i915_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-kbl-2/igt@i915_module_load@load.html
    - bat-arls-5:         [PASS][51] -> [ABORT][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-arls-5/igt@i915_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-arls-5/igt@i915_module_load@load.html
    - bat-rplp-1:         [PASS][53] -> [ABORT][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-rplp-1/igt@i915_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-rplp-1/igt@i915_module_load@load.html
    - fi-tgl-1115g4:      [PASS][55] -> [ABORT][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-tgl-1115g4/igt@i915_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-tgl-1115g4/igt@i915_module_load@load.html
    - fi-cfl-guc:         [PASS][57] -> [ABORT][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-cfl-guc/igt@i915_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-cfl-guc/igt@i915_module_load@load.html
    - bat-mtlp-6:         [PASS][59] -> [ABORT][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-mtlp-6/igt@i915_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-mtlp-6/igt@i915_module_load@load.html
    - bat-mtlp-9:         [PASS][61] -> [ABORT][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-mtlp-9/igt@i915_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-mtlp-9/igt@i915_module_load@load.html
    - bat-arls-6:         [PASS][63] -> [ABORT][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-arls-6/igt@i915_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-arls-6/igt@i915_module_load@load.html
    - bat-dg2-9:          [PASS][65] -> [ABORT][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg2-9/igt@i915_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg2-9/igt@i915_module_load@load.html
    - fi-kbl-x1275:       [PASS][67] -> [ABORT][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-kbl-x1275/igt@i915_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-kbl-x1275/igt@i915_module_load@load.html
    - bat-adlp-11:        [PASS][69] -> [ABORT][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-adlp-11/igt@i915_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-adlp-11/igt@i915_module_load@load.html
    - fi-hsw-4770:        [PASS][71] -> [ABORT][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-hsw-4770/igt@i915_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-hsw-4770/igt@i915_module_load@load.html
    - fi-cfl-8109u:       [PASS][73] -> [ABORT][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-cfl-8109u/igt@i915_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-cfl-8109u/igt@i915_module_load@load.html
    - fi-ivb-3770:        [PASS][75] -> [ABORT][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-ivb-3770/igt@i915_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-ivb-3770/igt@i915_module_load@load.html
    - bat-mtlp-8:         [PASS][77] -> [ABORT][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-mtlp-8/igt@i915_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-mtlp-8/igt@i915_module_load@load.html
    - bat-dg1-6:          [PASS][79] -> [ABORT][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg1-6/igt@i915_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg1-6/igt@i915_module_load@load.html
    - bat-dg2-8:          [PASS][81] -> [ABORT][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-dg2-8/igt@i915_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-dg2-8/igt@i915_module_load@load.html
    - fi-kbl-guc:         [PASS][83] -> [ABORT][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/fi-kbl-guc/igt@i915_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/fi-kbl-guc/igt@i915_module_load@load.html
    - bat-adls-6:         [PASS][85] -> [ABORT][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16557/bat-adls-6/igt@i915_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/bat-adls-6/igt@i915_module_load@load.html

  


Build changes
-------------

  * Linux: CI_DRM_16557 -> Patchwork_149110v1

  CI-20190529: 20190529
  CI_DRM_16557: 6d2dd85ba4eb3df89dc816c03b5bf81a470865b2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8365: 8365
  Patchwork_149110v1: 6d2dd85ba4eb3df89dc816c03b5bf81a470865b2 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v1/index.html

[-- Attachment #2: Type: text/html, Size: 13855 bytes --]

✗ Fi.CI.CHECKPATCH: warning for drm/i915/flipq: Rough flip queue implementation (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/149110/
State : warning

== Summary ==

Error: dim checkpatch failed
5d1335d6c927 drm/i915/dsb: Extract intel_dsb_ins_align()
eaac55d2d020 drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()
b7f97172350e drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
11cf09d0f973 drm/i915/dsb: Extract intel_dsb_{head,tail}()
ab29e6755878 drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()
fcc6526986ce drm/i915/dmc: Define flip queue related PIPEDMC registers
-:59: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#59: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:322:
+#define PIPEDMC_FQ_STATUS(pipe)		_MMIO_PIPE((pipe), _PIPEDMC_FQ_STATUS_A, _PIPEDMC_FQ_STATUS_B)

-:66: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:329:
+#define PIPEDMC_FPQ_ATOMIC_TP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_FPQ_ATOMIC_TP_A, _PIPEDMC_FPQ_ATOMIC_TP_B)

-:80: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:343:
+#define PIPEDMC_FPQ_LINES_TO_W1		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W1_A, _PIPEDMC_FPQ_LINES_TO_W1_B)

-:84: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:347:
+#define PIPEDMC_FPQ_LINES_TO_W2		_MMIO_PIPE((pipe), _PIPEDMC_FPQ_LINES_TO_W2_A, _PIPEDMC_FPQ_LINES_TO_W2_B)

-:88: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:351:
+#define PIPEDMC_SCANLINECMP(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMP_A, _PIPEDMC_SCANLINECMP_B)

-:94: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:357:
+#define PIPEDMC_SCANLINECMPLOWER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPLOWER_A, _PIPEDMC_SCANLINECMPLOWER_B)

-:98: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:361:
+#define   PIPEDMC_SCANLINE_LOWER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_LOWER_MASK, (scanline))

-:102: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#102: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:365:
+#define PIPEDMC_SCANLINECMPUPPER(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINECMPUPPER_A, _PIPEDMC_SCANLINECMPUPPER_B)

-:104: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#104: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:367:
+#define   PIPEDMC_SCANLINE_UPPER(scanline)	REG_FIELD_PREP(PIPEDMC_SCANLINE_UPPER_MASK, (scanline))

-:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#106: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:369:
+#define _MMIO_PIPEDMC_FPQ(pipe, fq_id, \
+			  reg_fpq1_a, reg_fpq2_a, reg_fpq3_a, reg_fpq4_a, \
+			  reg_fpq1_b, reg_fpq2_b, reg_fpq3_b, reg_fpq4_b) \
+	_MMIO(_PICK_EVEN_2RANGES((fq_id), INTEL_FLIPQ_PLANE_3, \
+				 _PIPE((pipe), (reg_fpq1_a), (reg_fpq1_b)), \
+				 _PIPE((pipe), (reg_fpq2_a), (reg_fpq2_b)), \
+				 _PIPE((pipe), (reg_fpq3_a), (reg_fpq3_b)), \
+				 _PIPE((pipe), (reg_fpq4_a), (reg_fpq4_b))))

-:158: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#158: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:421:
+							  _PIPEDMC_FPQ1_CHP_A, _PIPEDMC_FPQ2_CHP_A, \

-:159: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:422:
+							  _PIPEDMC_FPQ3_CHP_A, _PIPEDMC_FPQ4_CHP_A, \

-:160: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:423:
+							  _PIPEDMC_FPQ1_CHP_B, _PIPEDMC_FPQ2_CHP_B, \

-:169: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#169: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:432:
+#define PIPEDMC_SCANLINE_RO(pipe)	_MMIO_PIPE((pipe), _PIPEDMC_SCANLINE_RO_A, _PIPEDMC_SCANLINE_RO_B)

-:191: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#191: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:543:
+#define   PIPE_D_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_D_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:193: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#193: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:545:
+#define   PIPE_C_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_C_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:195: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:547:
+#define   PIPE_B_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_B_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

-:197: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#197: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:549:
+#define   PIPE_A_DMC_W2_PTS_CONFIG_SELECT(pipe)	REG_FIELD_PREP(PIPE_A_DMC_W2_PTS_CONFIG_SELECT_MASK, (pipe))

total: 0 errors, 17 warnings, 1 checks, 194 lines checked
8d5bd7e3df2c drm/i915/flipq: Provide the nuts and bolts code for flip queue
-:37: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#37: 
      need to think what to about the cdclk dependency on the execution time

-:265: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#265: 
new file mode 100644

-:291: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'flipq_id' - possible side-effects?
#291: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:22:
+#define for_each_flipq(flipq_id) \
+	for ((flipq_id) = INTEL_FLIPQ_PLANE_1; (flipq_id) < MAX_INTEL_FLIPQ; (flipq_id)++)

-:358: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#358: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:89:
+		flipq->start_mmioaddr = intel_pipedmc_start_mmioaddr(crtc) + intel_flipq_offset(flipq_id);

-:523: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#523: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:254:
+					       intel_flipq_elem_size_dw(flipq->flipq_id) + i), data);

total: 0 errors, 4 warnings, 1 checks, 526 lines checked
399c569b08b3 drm/i915/flipq: Implement flipq queue based commit path
-:193: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#193: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:66:
+intel_display_param_named_unsafe(enable_flipq, bool, 0400,
+	"Enable DMC flip queue (default: false)");

total: 0 errors, 0 warnings, 1 checks, 208 lines checked
2f657482292e drm/i915/flipq: Implement Wa_18034343758
d3b25be4d6c1 drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
e776487b6548 drm/i915/flipq: Add intel_flipq_dump()
-:34: WARNING:PREFER_PR_LEVEL: Prefer [subsystem eg: netdev]_cont([subsystem]dev, ... then dev_cont(dev, ... then pr_cont(...  to printk(KERN_CONT ...
#34: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:162:
+		printk(KERN_CONT " 0x%08x",

-:34: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where feasible
#34: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:162:
+		printk(KERN_CONT " 0x%08x",

-:36: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:164:
+		if (i % intel_flipq_elem_size_dw(flipq_id) == intel_flipq_elem_size_dw(flipq_id) - 1)

-:37: WARNING:PREFER_PR_LEVEL: Prefer [subsystem eg: netdev]_cont([subsystem]dev, ... then dev_cont(dev, ... then pr_cont(...  to printk(KERN_CONT ...
#37: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:165:
+			printk(KERN_CONT "\n");

-:37: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where feasible
#37: FILE: drivers/gpu/drm/i915/display/intel_flipq.c:165:
+			printk(KERN_CONT "\n");

total: 0 errors, 5 warnings, 0 checks, 60 lines checked
3d0a6a3c893d drm/i915/flipq: Enable flipq by default for testing

✗ Fi.CI.SPARSE: warning for drm/i915/flipq: Rough flip queue implementation (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/149110/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for drm/i915/flipq: Rough flip queue implementation (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6338 bytes --]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/149110/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16567 -> Patchwork_149110v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_149110v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [PASS][1] -> [INCOMPLETE][2] ([i915#12904]) +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-apl-1/igt@dmabuf@all-tests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@i915_selftest@live@gt_engines:
    - bat-twl-2:          [PASS][3] -> [INCOMPLETE][4] ([i915#14211]) +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-twl-2/igt@i915_selftest@live@gt_engines.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-twl-2/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@slpc:
    - bat-arlh-2:         NOTRUN -> [INCOMPLETE][5] ([i915#14065])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-arlh-2/igt@i915_selftest@live@slpc.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][6] -> [DMESG-FAIL][7] ([i915#12061]) +1 other test dmesg-fail
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-arls-5:         [PASS][8] -> [DMESG-FAIL][9] ([i915#12061]) +1 other test dmesg-fail
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-arls-5/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][10] -> [DMESG-FAIL][11] ([i915#12061]) +1 other test dmesg-fail
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-tgl-1115g4:      [PASS][12] -> [FAIL][13] ([i915#13930])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-dg2-14:         [ABORT][14] ([i915#13465] / [i915#13571]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-dg2-14/igt@core_hotunplug@unbind-rebind.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-dg2-14/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_selftest@live@gem:
    - bat-arlh-2:         [ABORT][16] ([i915#13723]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-arlh-2/igt@i915_selftest@live@gem.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-arlh-2/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [DMESG-FAIL][18] ([i915#12061]) -> [PASS][19] +1 other test pass
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-arlh-2:         [ABORT][20] ([i915#13723]) -> [INCOMPLETE][21] ([i915#14046])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-arlh-2/igt@i915_selftest@live.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-arlh-2/igt@i915_selftest@live.html
    - bat-atsm-1:         [DMESG-FAIL][22] ([i915#12061] / [i915#14204]) -> [DMESG-FAIL][23] ([i915#12061] / [i915#13929])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-atsm-1/igt@i915_selftest@live.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][24] ([i915#14204]) -> [DMESG-FAIL][25] ([i915#13929])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/bat-atsm-1/igt@i915_selftest@live@mman.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13465
  [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
  [i915#13723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13723
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#13930]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13930
  [i915#14046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14046
  [i915#14065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14065
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#14211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14211


Build changes
-------------

  * Linux: CI_DRM_16567 -> Patchwork_149110v3

  CI-20190529: 20190529
  CI_DRM_16567: 9ef3b3ca5fada31ee49be0882e69fd516f29e070 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8367: 8367
  Patchwork_149110v3: 9ef3b3ca5fada31ee49be0882e69fd516f29e070 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/index.html

[-- Attachment #2: Type: text/html, Size: 7775 bytes --]

✗ i915.CI.Full: failure for drm/i915/flipq: Rough flip queue implementation (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 113540 bytes --]

== Series Details ==

Series: drm/i915/flipq: Rough flip queue implementation (rev3)
URL   : https://patchwork.freedesktop.org/series/149110/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16567_full -> Patchwork_149110v3_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_149110v3_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_149110v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_149110v3_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - shard-dg2:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-7/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-2/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_149110v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2-9:        NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@crc32:
    - shard-rkl:          NOTRUN -> [SKIP][4] ([i915#6230])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@api_intel_bb@crc32.html
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#6230])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@api_intel_bb@crc32.html

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#8411])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#11078])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][8] ([i915#11078])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#13008])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [PASS][11] -> [INCOMPLETE][12] ([i915#13356]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-8/igt@gem_ccs@suspend-resume.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-7/igt@gem_ccs@suspend-resume.html
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#9323])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_ccs@suspend-resume.html

  * igt@gem_create@create-ext-set-pat:
    - shard-tglu-1:       NOTRUN -> [SKIP][14] ([i915#8562])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][15] ([i915#8555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_ctx_persistence@hang.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1:
    - shard-mtlp:         [PASS][16] -> [ABORT][17] ([i915#13723]) +1 other test abort
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-mtlp-6/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-4/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd1.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2-9:        NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglu-1:       NOTRUN -> [SKIP][20] ([i915#280])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@hibernate:
    - shard-rkl:          [PASS][21] -> [ABORT][22] ([i915#7975] / [i915#8213])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-7/igt@gem_eio@hibernate.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-5/igt@gem_eio@hibernate.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [PASS][23] -> [FAIL][24] ([i915#5784])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-16/igt@gem_eio@reset-stress.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-15/igt@gem_eio@reset-stress.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][25] ([i915#4812])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#4812]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#4525]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@gem_exec_balancer@parallel-bb-first.html
    - shard-tglu:         NOTRUN -> [SKIP][28] ([i915#4525]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][29] ([i915#4525])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][31] ([i915#3539])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-dg2:          NOTRUN -> [SKIP][33] ([i915#5107])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-active:
    - shard-dg2:          NOTRUN -> [SKIP][34] ([i915#3281]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-concurrent16:
    - shard-mtlp:         NOTRUN -> [SKIP][35] ([i915#3281])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_exec_reloc@basic-concurrent16.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#3281]) +19 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg2-9:        NOTRUN -> [SKIP][37] ([i915#3281]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2-9:        NOTRUN -> [SKIP][38] ([i915#4537] / [i915#4812])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#4537] / [i915#4812])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_fence_thrash@bo-write-verify-none:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#4860])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_fence_thrash@bo-write-verify-none.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-none:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#4860])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@gem_fence_thrash@bo-write-verify-threaded-none.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2-9:        NOTRUN -> [SKIP][42] ([i915#4860])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#4613] / [i915#7582])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#4613]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][45] ([i915#4613]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-glk:          NOTRUN -> [SKIP][46] ([i915#4613]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][47] ([i915#4613]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_media_fill@media-fill:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#8289])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_media_fill@media-fill.html

  * igt@gem_media_vme:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#284])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@basic-short:
    - shard-mtlp:         NOTRUN -> [SKIP][50] ([i915#4077]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_mmap_gtt@basic-short.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-dg2-9:        NOTRUN -> [SKIP][51] ([i915#4077]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#4077]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2-9:        NOTRUN -> [SKIP][53] ([i915#4083]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_mmap_wc@pf-nonblock:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#4083])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_mmap_wc@pf-nonblock.html

  * igt@gem_mmap_wc@read-write:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4083])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_mmap_wc@read-write.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg2-9:        NOTRUN -> [SKIP][56] ([i915#3282]) +2 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#3282]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][58] ([i915#3282]) +8 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pread@exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][59] ([i915#2658])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-rkl:          NOTRUN -> [TIMEOUT][60] ([i915#12917] / [i915#12964]) +1 other test timeout
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-rkl:          NOTRUN -> [TIMEOUT][61] ([i915#12964])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-dg2-9:        NOTRUN -> [SKIP][62] ([i915#4270]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - shard-rkl:          [PASS][63] -> [TIMEOUT][64] ([i915#12917] / [i915#12964]) +1 other test timeout
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-buf-execution.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_pxp@verify-pxp-stale-buf-execution.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][65] ([i915#5190] / [i915#8428]) +4 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_render_copy@linear-to-vebox-yf-tiled.html

  * igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#5190] / [i915#8428]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][67] ([i915#4079]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#4079])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_unfence_active_buffers:
    - shard-dg2-9:        NOTRUN -> [SKIP][69] ([i915#4879])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@access-control:
    - shard-dg2-9:        NOTRUN -> [SKIP][70] ([i915#3297]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#3297]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#3297] / [i915#3323])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#3297])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#3297]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2-9:        NOTRUN -> [SKIP][75] ([i915#3297] / [i915#4880])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@relocations:
    - shard-mtlp:         NOTRUN -> [SKIP][76] ([i915#3281] / [i915#3297])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#3297]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gem_workarounds@suspend-resume:
    - shard-rkl:          [PASS][78] -> [INCOMPLETE][79] ([i915#13356])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@gem_workarounds@suspend-resume.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-3/igt@gem_workarounds@suspend-resume.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-rkl:          NOTRUN -> [SKIP][80] +32 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@gen7_exec_parse@chained-batch.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-mtlp:         NOTRUN -> [SKIP][81] +5 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2-9:        NOTRUN -> [SKIP][82] ([i915#2856]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@gen9_exec_parse@allowed-all.html
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#2527]) +5 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-dg2:          NOTRUN -> [SKIP][84] ([i915#2856]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#2527] / [i915#2856])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#2856])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_drm_fdinfo@most-busy-check-all@bcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][87] ([i915#14073]) +6 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@i915_drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@i915_drm_fdinfo@virtual-busy-idle:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#14118])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@i915_drm_fdinfo@virtual-busy-idle.html

  * igt@i915_drm_fdinfo@virtual-busy-idle-all:
    - shard-dg2-9:        NOTRUN -> [SKIP][89] ([i915#14118]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@i915_drm_fdinfo@virtual-busy-idle-all.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][90] ([i915#8399])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([i915#6590]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-rkl:          [PASS][92] -> [FAIL][93] ([i915#12942]) +1 other test fail
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-8/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rpm@gem-execbuf:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#13328])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@i915_pm_rpm@gem-execbuf.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][95] ([i915#12797])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk5/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#4387])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#5723])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_selftest@live@guc_multi_lrc:
    - shard-dg2:          [PASS][98] -> [INCOMPLETE][99] ([i915#14201])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-7/igt@i915_selftest@live@guc_multi_lrc.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-2/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@workarounds:
    - shard-dg2:          [PASS][100] -> [DMESG-FAIL][101] ([i915#12061])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-7/igt@i915_selftest@live@workarounds.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-2/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#7707])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg2-9:        NOTRUN -> [SKIP][103] ([i915#4215] / [i915#5190])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-dg2-9:        NOTRUN -> [SKIP][104] ([i915#12967] / [i915#6228])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2-9:        NOTRUN -> [SKIP][105] ([i915#9531])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking:
    - shard-glk:          [PASS][106] -> [FAIL][107] ([i915#12177])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
    - shard-glk:          [PASS][108] -> [FAIL][109] ([i915#11859])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#1769] / [i915#3555])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#1769] / [i915#3555])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][112] ([i915#5286]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#5286]) +11 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][114] ([i915#5286]) +4 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-dg2-9:        NOTRUN -> [SKIP][115] +8 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#3638]) +4 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#4538] / [i915#5190]) +5 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-dg2-9:        NOTRUN -> [SKIP][118] ([i915#4538] / [i915#5190]) +8 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#6095]) +131 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-19/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][121] ([i915#10307] / [i915#6095]) +38 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][122] ([i915#6095]) +24 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#6095]) +49 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][124] ([i915#6095]) +14 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#12313])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][126] ([i915#10307] / [i915#10434] / [i915#6095])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#12805])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#14098] / [i915#6095]) +68 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][129] ([i915#12805])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#6095]) +15 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][131] ([i915#12313])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#6095]) +69 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#10307] / [i915#6095]) +136 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][134] ([i915#12313]) +2 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][135] ([i915#12313]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#3742])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][137] ([i915#13781]) +3 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][138] +3 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#11151] / [i915#7828]) +3 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#11151] / [i915#7828]) +15 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#11151] / [i915#7828]) +5 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-dg2-9:        NOTRUN -> [SKIP][142] ([i915#11151] / [i915#7828]) +6 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#11151] / [i915#7828]) +3 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_color@deep-color:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#3555] / [i915#9979])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#7118] / [i915#9424])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#7118] / [i915#9424])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#3116] / [i915#3299])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-dg2-9:        NOTRUN -> [SKIP][148] ([i915#3299])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_content_protection@dp-mst-type-0.html
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#3116]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#3116] / [i915#3299])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-1:
    - shard-dg2-9:        NOTRUN -> [SKIP][152] ([i915#9424])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@srm@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][153] ([i915#7173])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-11/igt@kms_content_protection@srm@pipe-a-dp-3.html

  * igt@kms_content_protection@uevent:
    - shard-tglu-1:       NOTRUN -> [SKIP][154] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [FAIL][155] ([i915#13566]) +1 other test fail
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][156] ([i915#13566]) +2 other tests fail
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#13049])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#3555]) +7 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#3555]) +3 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-tglu-1:       NOTRUN -> [SKIP][160] ([i915#3555]) +3 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#13049]) +2 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-512x170.html
    - shard-tglu:         NOTRUN -> [SKIP][162] ([i915#13049])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_edge_walk@128x128-top-edge:
    - shard-rkl:          [PASS][163] -> [DMESG-WARN][164] ([i915#12964]) +11 other tests dmesg-warn
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-8/igt@kms_cursor_edge_walk@128x128-top-edge.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_cursor_edge_walk@128x128-top-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-dg2-9:        NOTRUN -> [SKIP][165] ([i915#13046] / [i915#5354]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#13046] / [i915#5354]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-rkl:          [PASS][167] -> [FAIL][168] ([i915#2346])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#9067])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-tglu:         NOTRUN -> [SKIP][170] ([i915#4103]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#4103])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-9:        NOTRUN -> [SKIP][172] ([i915#4103] / [i915#4213]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#9833])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][174] ([i915#13691])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_display_modes@extended-mode-basic.html
    - shard-rkl:          NOTRUN -> [SKIP][175] ([i915#13691])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#3804])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#1257])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#13749])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_dp_link_training@non-uhbr-mst.html
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#13749])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#13748])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#13748])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_dp_link_training@uhbr-sst.html
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#13748])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-mtlp:         NOTRUN -> [SKIP][183] ([i915#13707])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg2-9:        NOTRUN -> [SKIP][184] ([i915#13707])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#3555] / [i915#3840])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#3840])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-dg2-9:        NOTRUN -> [SKIP][187] ([i915#3555] / [i915#3840])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#3840] / [i915#9053])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-dg2-9:        NOTRUN -> [SKIP][189] ([i915#13798])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#2575])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg2-9:        NOTRUN -> [SKIP][191] ([i915#3469])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#4854])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#1839]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_feature_discovery@display-4x.html
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#1839]) +1 other test skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#658])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_feature_discovery@psr1.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2-9:        NOTRUN -> [SKIP][196] ([i915#658])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([i915#3637] / [i915#9934])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][198] ([i915#9934]) +11 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] ([i915#9934]) +1 other test skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-dg2-9:        NOTRUN -> [SKIP][200] ([i915#9934]) +2 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#3637] / [i915#9934]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][202] ([i915#3637] / [i915#9934]) +3 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@blocking-wf_vblank:
    - shard-dg1:          [PASS][203] -> [FAIL][204] ([i915#13734])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-17/igt@kms_flip@blocking-wf_vblank.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-12/igt@kms_flip@blocking-wf_vblank.html

  * igt@kms_flip@blocking-wf_vblank@a-hdmi-a2:
    - shard-dg2-9:        NOTRUN -> [FAIL][205] ([i915#13734]) +2 other tests fail
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_flip@blocking-wf_vblank@a-hdmi-a2.html

  * igt@kms_flip@blocking-wf_vblank@b-hdmi-a3:
    - shard-dg1:          NOTRUN -> [FAIL][206] ([i915#13734]) +1 other test fail
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-12/igt@kms_flip@blocking-wf_vblank@b-hdmi-a3.html

  * igt@kms_flip@blocking-wf_vblank@c-hdmi-a1:
    - shard-tglu:         [PASS][207] -> [FAIL][208] ([i915#13734]) +3 other tests fail
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-tglu-3/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_flip@blocking-wf_vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([i915#8381])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1:
    - shard-rkl:          NOTRUN -> [FAIL][210] ([i915#13734]) +3 other tests fail
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-hdmi-a1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-tglu:         NOTRUN -> [FAIL][211] ([i915#11832] / [i915#13734])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1:
    - shard-tglu:         NOTRUN -> [FAIL][212] ([i915#13734]) +3 other tests fail
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_flip@wf_vblank-ts-check@d-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
    - shard-dg2-9:        NOTRUN -> [SKIP][213] ([i915#2672]) +1 other test skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
    - shard-rkl:          NOTRUN -> [SKIP][214] ([i915#2672]) +4 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][215] ([i915#2672] / [i915#3555])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][216] ([i915#2587] / [i915#2672])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][217] ([i915#2672] / [i915#3555])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][218] ([i915#2587] / [i915#2672] / [i915#3555])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][219] ([i915#2672] / [i915#3555] / [i915#8813])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][220] ([i915#2672] / [i915#8813])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][221] ([i915#2672] / [i915#3555]) +4 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][222] ([i915#2672] / [i915#3555]) +1 other test skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#2587] / [i915#2672]) +2 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#2672] / [i915#3555] / [i915#5190])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][225] ([i915#2672]) +1 other test skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][226] ([i915#2672] / [i915#3555]) +3 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#8708]) +7 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-dg2-9:        NOTRUN -> [SKIP][228] ([i915#5354]) +22 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][229] +41 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][230] ([i915#10055])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2-9:        NOTRUN -> [SKIP][231] ([i915#3458]) +14 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#1825]) +54 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#5354]) +13 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-tglu:         NOTRUN -> [SKIP][234] +83 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#3023]) +36 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#10433] / [i915#3458])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][237] ([i915#5439])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-dg2-9:        NOTRUN -> [SKIP][238] ([i915#9766])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][239] ([i915#3458]) +6 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2-9:        NOTRUN -> [SKIP][240] ([i915#8708]) +13 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-mtlp:         NOTRUN -> [SKIP][241] ([i915#1825]) +7 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][242] ([i915#8708])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][243] ([i915#6118])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-9:        NOTRUN -> [SKIP][244] ([i915#3555] / [i915#8228])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          NOTRUN -> [SKIP][245] ([i915#3555] / [i915#8228]) +3 other tests skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-swap:
    - shard-tglu:         NOTRUN -> [SKIP][246] ([i915#3555] / [i915#8228]) +1 other test skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][247] ([i915#3555] / [i915#8228])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][248] ([i915#10656]) +1 other test skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][249] ([i915#12388])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_joiner@basic-force-big-joiner.html
    - shard-rkl:          NOTRUN -> [SKIP][250] ([i915#12388])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][251] ([i915#10656])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][252] ([i915#10656])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][253] ([i915#12339])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][254] ([i915#13522])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][255] ([i915#1839])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][256] ([i915#6301])
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][257] ([i915#12964]) +9 other tests dmesg-warn
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_plane_alpha_blend@alpha-basic@pipe-b-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][258] ([i915#10647] / [i915#12169])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][259] ([i915#10647]) +1 other test fail
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-dg2-9:        NOTRUN -> [SKIP][260] ([i915#3555] / [i915#8821])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg2:          NOTRUN -> [SKIP][261] ([i915#13958]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-rkl:          NOTRUN -> [SKIP][262] ([i915#13958]) +1 other test skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][263] ([i915#13958]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2-9:        NOTRUN -> [SKIP][264] ([i915#14259])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-dg2-9:        NOTRUN -> [SKIP][265] ([i915#13046] / [i915#5354] / [i915#9423])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-mtlp:         NOTRUN -> [SKIP][266] ([i915#6953])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][267] ([i915#12247]) +10 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
    - shard-tglu-1:       NOTRUN -> [SKIP][268] ([i915#12247]) +9 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][269] ([i915#12247] / [i915#6953])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
    - shard-tglu:         NOTRUN -> [SKIP][270] ([i915#12247]) +12 other tests skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][271] ([i915#12247] / [i915#3555])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][272] ([i915#12247] / [i915#6953]) +1 other test skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu-1:       NOTRUN -> [SKIP][273] ([i915#9812])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][274] ([i915#9812])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_pm_backlight@fade-with-suspend.html
    - shard-rkl:          NOTRUN -> [SKIP][275] ([i915#5354]) +1 other test skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg2-9:        NOTRUN -> [SKIP][276] ([i915#9685]) +2 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-rkl:          NOTRUN -> [SKIP][277] ([i915#9685]) +1 other test skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-tglu:         NOTRUN -> [SKIP][278] ([i915#9685])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][279] ([i915#3828])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-tglu-1:       NOTRUN -> [SKIP][280] ([i915#3828])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu-1:       NOTRUN -> [FAIL][281] ([i915#9295])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2-9:        NOTRUN -> [SKIP][282] ([i915#9340])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#9519]) +1 other test skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [PASS][284] -> [DMESG-WARN][285] ([i915#4423]) +3 other tests dmesg-warn
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-18/igt@kms_pm_rpm@i2c.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-18/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [PASS][286] -> [SKIP][287] ([i915#9519]) +1 other test skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2-9:        NOTRUN -> [SKIP][288] ([i915#6524] / [i915#6805])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][289] ([i915#6524])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_prime@basic-modeset-hybrid.html
    - shard-tglu-1:       NOTRUN -> [SKIP][290] ([i915#6524])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_properties@get_properties-sanity-non-atomic:
    - shard-tglu:         NOTRUN -> [FAIL][291] ([i915#14036]) +1 other test fail
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_properties@get_properties-sanity-non-atomic.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-mtlp:         NOTRUN -> [SKIP][292] ([i915#12316])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-dg2-9:        NOTRUN -> [SKIP][293] ([i915#11520]) +4 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2:          NOTRUN -> [SKIP][294] ([i915#11520]) +3 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][295] ([i915#11520]) +13 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][296] ([i915#11520]) +4 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][297] ([i915#11520]) +2 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][298] ([i915#11520]) +7 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][299] ([i915#9683])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-tglu-1:       NOTRUN -> [SKIP][300] ([i915#9683])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-tglu:         NOTRUN -> [SKIP][301] ([i915#9683])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-cursor-render:
    - shard-dg2:          NOTRUN -> [SKIP][302] ([i915#1072] / [i915#9732]) +9 other tests skip
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_psr@fbc-pr-cursor-render.html

  * igt@kms_psr@fbc-psr-primary-page-flip@edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][303] ([i915#9688]) +4 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@kms_psr@fbc-psr-primary-page-flip@edp-1.html

  * igt@kms_psr@fbc-psr2-suspend:
    - shard-dg2-9:        NOTRUN -> [SKIP][304] ([i915#1072] / [i915#9732]) +15 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_psr@fbc-psr2-suspend.html

  * igt@kms_psr@pr-sprite-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][305] ([i915#1072] / [i915#9732]) +32 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_psr@pr-sprite-mmap-gtt.html

  * igt@kms_psr@psr-cursor-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][306] ([i915#9732]) +19 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-6/igt@kms_psr@psr-cursor-mmap-gtt.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][307] ([i915#9732]) +9 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr-no-drrs:
    - shard-glk:          NOTRUN -> [SKIP][308] +88 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@kms_psr@psr-no-drrs.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-9:        NOTRUN -> [SKIP][309] ([i915#5190]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-tglu:         NOTRUN -> [SKIP][310] ([i915#5289])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg2:          NOTRUN -> [SKIP][311] ([i915#12755] / [i915#5190])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-tglu:         NOTRUN -> [SKIP][312] ([i915#3555]) +4 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-rkl:          NOTRUN -> [ABORT][313] ([i915#13179]) +1 other test abort
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-rkl:          NOTRUN -> [SKIP][314] ([i915#8623])
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][315] ([i915#8623])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-dg1:          NOTRUN -> [SKIP][316] ([i915#3555])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-18/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][317] ([i915#9906]) +1 other test skip
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-7/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flipline:
    - shard-dg2-9:        NOTRUN -> [SKIP][318] ([i915#3555]) +2 other tests skip
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_vrr@flipline.html

  * igt@kms_vrr@lobf:
    - shard-dg2:          NOTRUN -> [SKIP][319] ([i915#11920])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-dg2-9:        NOTRUN -> [SKIP][320] ([i915#9906])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_vrr@max-min.html

  * igt@kms_vrr@negative-basic:
    - shard-mtlp:         [PASS][321] -> [FAIL][322] ([i915#10393]) +1 other test fail
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-mtlp-8/igt@kms_vrr@negative-basic.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-6/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-dg2:          NOTRUN -> [SKIP][323] ([i915#9906])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_writeback@writeback-check-output:
    - shard-tglu-1:       NOTRUN -> [SKIP][324] ([i915#2437])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][325] ([i915#2437] / [i915#9412]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html
    - shard-tglu:         NOTRUN -> [SKIP][326] ([i915#2437] / [i915#9412])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-rkl:          NOTRUN -> [SKIP][327] ([i915#2437]) +1 other test skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-dg2-9:        NOTRUN -> [SKIP][328] ([i915#2437] / [i915#9412])
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-9/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][329] ([i915#2433])
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@busy-accuracy-98@rcs0:
    - shard-tglu:         [PASS][330] -> [FAIL][331] ([i915#4349]) +1 other test fail
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-tglu-9/igt@perf_pmu@busy-accuracy-98@rcs0.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-3/igt@perf_pmu@busy-accuracy-98@rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          NOTRUN -> [FAIL][332] ([i915#4349]) +4 other tests fail
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@module-unload:
    - shard-tglu-1:       NOTRUN -> [INCOMPLETE][333] ([i915#13029] / [i915#13520])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-tglu-1:       NOTRUN -> [SKIP][334] ([i915#8516]) +1 other test skip
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_mmap@test_aperture_limit:
    - shard-dg2:          NOTRUN -> [SKIP][335] ([i915#14121]) +1 other test skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@prime_mmap@test_aperture_limit.html

  * igt@prime_vgem@basic-write:
    - shard-dg2:          NOTRUN -> [SKIP][336] ([i915#3291] / [i915#3708])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][337] ([i915#3708] / [i915#4077])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg2:          NOTRUN -> [SKIP][338] ([i915#3708])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@prime_vgem@fence-read-hang.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          NOTRUN -> [SKIP][339] ([i915#3708])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2:          NOTRUN -> [SKIP][340] ([i915#9917])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-8/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-rkl:          NOTRUN -> [SKIP][341] ([i915#9917]) +1 other test skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-tglu-1:       NOTRUN -> [FAIL][342] ([i915#12910])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
#### Possible fixes ####

  * igt@gem_exec_capture@pi:
    - shard-dg2:          [FAIL][343] ([i915#14024]) -> [PASS][344]
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-11/igt@gem_exec_capture@pi.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-1/igt@gem_exec_capture@pi.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-dg2:          [FAIL][345] -> [PASS][346]
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-11/igt@gem_exec_capture@pi@rcs0.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-1/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [TIMEOUT][347] ([i915#14044] / [i915#5493]) -> [PASS][348] +1 other test pass
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-rkl:          [TIMEOUT][349] ([i915#12964]) -> [PASS][350]
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@gem_pxp@fail-invalid-protected-context.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-rkl:          [TIMEOUT][351] ([i915#12917] / [i915#12964]) -> [PASS][352] +1 other test pass
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-4/igt@gem_pxp@reject-modify-context-protection-off-3.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
    - shard-dg1:          [FAIL][353] ([i915#3591]) -> [PASS][354] +1 other test pass
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-tglu:         [FAIL][355] ([i915#13566]) -> [PASS][356] +1 other test pass
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-tglu-2/igt@kms_cursor_crc@cursor-random-128x42.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-10/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-rkl:          [FAIL][357] ([i915#13566]) -> [PASS][358] +2 other tests pass
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-rkl:          [INCOMPLETE][359] ([i915#12358] / [i915#14152]) -> [PASS][360]
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-4/igt@kms_cursor_crc@cursor-suspend.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_flip@blocking-wf_vblank@b-vga1:
    - shard-snb:          [FAIL][361] ([i915#13734]) -> [PASS][362] +3 other tests pass
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-snb2/igt@kms_flip@blocking-wf_vblank@b-vga1.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-snb6/igt@kms_flip@blocking-wf_vblank@b-vga1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg1:          [DMESG-WARN][363] ([i915#4423]) -> [PASS][364] +2 other tests pass
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-19/igt@kms_flip@flip-vs-suspend.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-16/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-tglu:         [FAIL][365] ([i915#13734]) -> [PASS][366] +3 other tests pass
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-tglu-5/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-tglu-4/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-rkl:          [FAIL][367] ([i915#13734]) -> [PASS][368] +1 other test pass
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-6/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1:
    - shard-mtlp:         [FAIL][369] ([i915#13734]) -> [PASS][370] +3 other tests pass
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          [SKIP][371] ([i915#3555] / [i915#8228]) -> [PASS][372]
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-2/igt@kms_hdr@bpc-switch-dpms.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-11/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [SKIP][373] ([i915#9519]) -> [PASS][374] +1 other test pass
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-4/igt@kms_pm_rpm@dpms-non-lpsp.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-5/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          [SKIP][375] ([i915#9519]) -> [PASS][376] +1 other test pass
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
    - shard-mtlp:         [FAIL][377] ([i915#9196]) -> [PASS][378] +1 other test pass
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html

  * igt@kms_vblank@query-forked-busy@pipe-a-hdmi-a-1:
    - shard-rkl:          [DMESG-WARN][379] ([i915#12964]) -> [PASS][380] +4 other tests pass
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-7/igt@kms_vblank@query-forked-busy@pipe-a-hdmi-a-1.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-4/igt@kms_vblank@query-forked-busy@pipe-a-hdmi-a-1.html

  * igt@perf_pmu@module-unload:
    - shard-mtlp:         [INCOMPLETE][381] ([i915#13520]) -> [PASS][382]
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-mtlp-2/igt@perf_pmu@module-unload.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-mtlp-1/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          [INCOMPLETE][383] ([i915#13197] / [i915#13390]) -> [INCOMPLETE][384] ([i915#13390])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-glk5/igt@gem_eio@in-flight-suspend.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk3/igt@gem_eio@in-flight-suspend.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][385] ([i915#14098] / [i915#6095]) -> [SKIP][386] ([i915#6095]) +3 other tests skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][387] ([i915#9433]) -> [SKIP][388] ([i915#9424])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-12/igt@kms_content_protection@mei-interface.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-18/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-dg2:          [SKIP][389] ([i915#7118]) -> [FAIL][390] ([i915#7173])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-2/igt@kms_content_protection@srm.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-11/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][391] ([i915#7118] / [i915#9424]) -> [SKIP][392] ([i915#7118] / [i915#7162] / [i915#9424])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-2/igt@kms_content_protection@type1.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-11/igt@kms_content_protection@type1.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][393] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][394] ([i915#12314] / [i915#12745] / [i915#4839])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-glk2/igt@kms_flip@2x-flip-vs-suspend.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][395] ([i915#4839]) -> [INCOMPLETE][396] ([i915#12314] / [i915#4839])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-glk2/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-glk8/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg1:          [SKIP][397] ([i915#8708]) -> [SKIP][398] ([i915#4423] / [i915#8708]) +1 other test skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg2:          [SKIP][399] ([i915#3458]) -> [SKIP][400] ([i915#10433] / [i915#3458]) +1 other test skip
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2:          [SKIP][401] ([i915#13331]) -> [SKIP][402] ([i915#12713])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg2-11/igt@kms_hdr@brightness-with-hdr.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg2-3/igt@kms_hdr@brightness-with-hdr.html
    - shard-dg1:          [SKIP][403] ([i915#12713]) -> [SKIP][404] ([i915#1187] / [i915#12713])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-dg1-18/igt@kms_hdr@brightness-with-hdr.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-dg1-13/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][405] ([i915#4070] / [i915#4816]) -> [SKIP][406] ([i915#1839] / [i915#4816])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][407] ([i915#9295]) -> [SKIP][408] ([i915#3361])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16567/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10393]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10393
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11832]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11832
  [i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
  [i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12797]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12797
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12942]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12942
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#12967]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12967
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13197
  [i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
  [i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13723
  [i915#13734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13734
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13798]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13798
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14024]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14024
  [i915#14036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14036
  [i915#14044]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14044
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14121
  [i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
  [i915#14201]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14201
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
  [i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_16567 -> Patchwork_149110v3

  CI-20190529: 20190529
  CI_DRM_16567: 9ef3b3ca5fada31ee49be0882e69fd516f29e070 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8367: 8367
  Patchwork_149110v3: 9ef3b3ca5fada31ee49be0882e69fd516f29e070 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_149110v3/index.html

[-- Attachment #2: Type: text/html, Size: 142922 bytes --]

RE: [PATCH 00/12] drm/i915/flipq: Rough flip queue implementation

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Friday, May 16, 2025 5:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 00/12] drm/i915/flipq: Rough flip queue implementation
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Initial stab at implementing the PIPEDMC based flip queue.
> Briefly smoke tested on LNL, not much more.
> 
> Still has quite a few warts..
> 
> Ville Syrjälä (12):
>   drm/i915/dsb: Extract intel_dsb_ins_align()
>   drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail()
>   drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
>   drm/i915/dsb: Extract intel_dsb_{head,tail}()

First 4 are already reviewed as part of Gosub series. Consider them Rb'ed.

>   drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size()
>   drm/i915/dmc: Define flip queue related PIPEDMC registers
>   drm/i915/flipq: Provide the nuts and bolts code for flip queue
>   drm/i915/flipq: Implement flipq queue based commit path
>   drm/i915/flipq: Implement Wa_18034343758
>   drm/i915/flipq: Implement Wa_16018781658 for LNL-A0
>   drm/i915/flipq: Add intel_flipq_dump()
>   drm/i915/flipq: Enable flipq by default for testing
> 
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  69 +++-
>  .../drm/i915/display/intel_display_driver.c   |   3 +
>  .../drm/i915/display/intel_display_params.c   |   3 +
>  .../drm/i915/display/intel_display_params.h   |   1 +
>  .../drm/i915/display/intel_display_types.h    |  20 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      |  90 ++++-
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  11 +
>  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 172 +++++++-
>  drivers/gpu/drm/i915/display/intel_dsb.c      |  63 ++-
>  drivers/gpu/drm/i915/display/intel_dsb.h      |   2 +
>  drivers/gpu/drm/i915/display/intel_flipq.c    | 374 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_flipq.h    |  35 ++
>  drivers/gpu/drm/xe/Makefile                   |   1 +
>  14 files changed, 811 insertions(+), 34 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/display/intel_flipq.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_flipq.h
> 
> --
> 2.49.0