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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: <intel-gfx@lists.freedesktop.org>,
	<intel-xe@lists.freedesktop.org>, <imre.deak@intel.com>
Subject: Re: [PATCH 1/3] drm/i915/power: move enum skl_power_gate under display
Date: Wed, 25 Jun 2025 09:52:19 -0400	[thread overview]
Message-ID: <aFv_E1ltKoRw5kW-@intel.com> (raw)
In-Reply-To: <495054983b74163ca7dcbf5a1b6a24099047bc64.1750855148.git.jani.nikula@intel.com>

On Wed, Jun 25, 2025 at 03:39:36PM +0300, Jani Nikula wrote:
> When the display registers were split off from i915_reg.h, enum
> skl_power_gate was left behind. Move it to intel_display_regs.h.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h |  9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
>  2 files changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index e101105da4af..fdac72fcebee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2195,6 +2195,15 @@
>  #define   HSW_PWR_WELL_FORCE_ON			(1 << 19)
>  #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
>  
> +/* SKL Fuse Status */
> +enum skl_power_gate {
> +	SKL_PG0,
> +	SKL_PG1,
> +	SKL_PG2,
> +	ICL_PG3,
> +	ICL_PG4,
> +};
> +
>  #define SKL_FUSE_STATUS				_MMIO(0x42000)
>  #define  SKL_FUSE_DOWNLOAD_STATUS		(1 << 31)
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 04fb40867cc0..cec6e2e2a262 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1204,16 +1204,6 @@
>   */
>  #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
>  
> -/* SKL Fuse Status */
> -enum skl_power_gate {
> -	SKL_PG0,
> -	SKL_PG1,
> -	SKL_PG2,
> -	ICL_PG3,
> -	ICL_PG4,
> -};
> -
> -
>  #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
>  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
>  #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
> -- 
> 2.39.5
> 

  reply	other threads:[~2025-06-25 13:52 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-25 12:39 [PATCH 0/3] drm/i915/power: power well register cleanups Jani Nikula
2025-06-25 12:39 ` [PATCH 1/3] drm/i915/power: move enum skl_power_gate under display Jani Nikula
2025-06-25 13:52   ` Rodrigo Vivi [this message]
2025-06-25 12:39 ` [PATCH 2/3] drm/i915/power: relocate {SKL,ICL}_PW_CTL_IDX_TO_PG() Jani Nikula
2025-06-25 13:52   ` [PATCH 2/3] drm/i915/power: relocate {SKL, ICL}_PW_CTL_IDX_TO_PG() Rodrigo Vivi
2025-06-25 12:39 ` [PATCH 3/3] drm/i915/power: convert {SKL, ICL}_PW_CTL_IDX_TO_PG() macros to a function Jani Nikula
2025-06-25 13:54   ` Rodrigo Vivi
2025-06-25 13:30 ` ✓ i915.CI.BAT: success for drm/i915/power: power well register cleanups Patchwork
2025-06-25 19:53 ` ✗ i915.CI.Full: failure " Patchwork

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