From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/irq: duplicate HAS_FBC() for irq error mask usage
Date: Mon, 29 Sep 2025 16:45:11 +0300 [thread overview]
Message-ID: <aNqNZwfs7SRRYaGd@intel.com> (raw)
In-Reply-To: <20250929133418.2033006-1-jani.nikula@intel.com>
On Mon, Sep 29, 2025 at 04:34:18PM +0300, Jani Nikula wrote:
> The error irq handling needs to mask page table errors on gen 2/3 with
> FBC. See commit e7e12f6ec8bf ("drm/i915: Mask page table errors on
> gen2/3 with FBC") for details.
>
> We want to avoid using display feature checks in i915 core code. Since
> FBC can't be fused off on gen 2/3, just list the platforms that support
> FBC. Add a macro purely for making the code self-documenting.
>
> With this, we can drop the intel_display_core.h include, and make struct
> intel_display opaque inside i915_irq.c.
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 11a727b74849..e0a0bd687f1b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -33,7 +33,6 @@
>
> #include <drm/drm_drv.h>
>
> -#include "display/intel_display_core.h"
> #include "display/intel_display_irq.h"
> #include "display/intel_hotplug.h"
> #include "display/intel_hotplug_irq.h"
> @@ -794,9 +793,10 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
> }
>
> +#define I9XX_HAS_FBC(i915) (IS_I85X(i915) || IS_I865G(i915) || IS_I915GM(i915) || IS_I945GM(i915))
Looks correct.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> static u32 i9xx_error_mask(struct drm_i915_private *i915)
> {
> - struct intel_display *display = i915->display;
> /*
> * On gen2/3 FBC generates (seemingly spurious)
> * display INVALID_GTT/INVALID_GTT_PTE table errors.
> @@ -809,7 +809,7 @@ static u32 i9xx_error_mask(struct drm_i915_private *i915)
> * Unfortunately we can't mask off individual PGTBL_ER bits,
> * so we just have to mask off all page table errors via EMR.
> */
> - if (HAS_FBC(display))
> + if (I9XX_HAS_FBC(i915))
> return I915_ERROR_MEMORY_REFRESH;
> else
> return I915_ERROR_PAGE_TABLE |
> --
> 2.47.3
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-09-29 13:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 13:34 [PATCH] drm/i915/irq: duplicate HAS_FBC() for irq error mask usage Jani Nikula
2025-09-29 13:45 ` Ville Syrjälä [this message]
2025-09-30 7:53 ` Jani Nikula
2025-09-29 15:35 ` ✓ i915.CI.BAT: success for " Patchwork
2025-09-29 19:07 ` ✗ i915.CI.Full: failure " Patchwork
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