Re: [PATCH 2/3] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Oct 28, 2025 at 10:05:01AM +0530, Ankit Nautiyal wrote:
> Adaptive Sync SDP is required when Panel replay is active and for
> supporting VRR on PCON.
> 
> Since VRR on PCON still needs some effort, enable adaptive sync SDP only
> when Panel replay with ALPM-Auxless is supported.
> 
> Set the AS_SDP mode for Fixed Vtotal mode for fixed refresh rate case.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ee113e118fed..8583cab37123 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2934,7 +2934,15 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  
> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> +	if (!intel_dp->as_sdp_supported)
> +		return;
> +
> +	/*
> +	 * Support Adaptive-Sync SDP only for PR+AUX-less ALPM for now.
> +	 * It can be enabled for PCON + VRR, but that is currently not supported.
> +	 */
> +	if (!CAN_PANEL_REPLAY(intel_dp) ||
> +	    !intel_alpm_aux_less_wake_supported(intel_dp))
>  		return;

You're not using any of the the psr/alpm crtc_state stuff in here,
so I'm not sure why you did the reordering in the previous patch?

>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> @@ -2948,9 +2956,12 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>  		as_sdp->target_rr_divider = true;
> -	} else {
> +	} else if (crtc_state->vrr.enable) {
>  		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;

We do not seem to configure the other bit in DOWNSPREAD_CTRL
properly for AS SDP v2, so technically this value looks to be
illegal. Same for the CMRR case.

The AS SDP (and SDP in general) code seems to have a myriad
of problems. Here are the ones off the top of my head:
- lack of SDP header validation in intel_compare_*_sdp()
- nothing seems to check that AS SDP v2 is actually
  supported and not just v1. I suppose maybe the PR+AUX-less
  check might be enough for that?
- intel_dp_as_sdp_unpack() target_rr readout looks broken
- intel_dp_as_sdp_pack() hardcodes HB2 instead of getting it
  from the input
- atomic updates/double buffering of all video DIPs is probably
  completely broken
- already discussed the vblank evasion issues in the previous mail

I suppose we don't need to fix it right now, but just a heads up 
that a significant amount of work os needed to get this code into
decent shape.

>  		as_sdp->target_rr = 0;
> +	} else {
> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
> +		as_sdp->target_rr = 0;

These target_rr assignments look completely redundant.

>  	}
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel