From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
"Ankit Nautiyal" <ankit.k.nautiyal@intel.com>,
"Dnyaneshwar Bhadane" <dnyaneshwar.bhadane@intel.com>,
"Jouni Högander" <jouni.hogander@intel.com>,
"Juha-pekka Heikkila" <juha-pekka.heikkila@intel.com>,
"Luca Coelho" <luciano.coelho@intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Matt Atwood" <matthew.s.atwood@intel.com>,
"Matt Roper" <matthew.d.roper@intel.com>,
"Ravi Kumar Vodapalli" <ravi.kumar.vodapalli@intel.com>,
"Shekhar Chauhan" <shekhar.chauhan@intel.com>,
"Vinod Govindapillai" <vinod.govindapillai@intel.com>
Subject: Re: [PATCH v2 14/32] drm/i915/wm: Reorder adjust_wm_latency() for Xe3_LPD
Date: Thu, 30 Oct 2025 00:22:01 +0200 [thread overview]
Message-ID: <aQKTXsWok4HaRCdv@intel.com> (raw)
In-Reply-To: <20251021-xe3p_lpd-basic-enabling-v2-14-10eae6d655b8@intel.com>
On Tue, Oct 21, 2025 at 09:28:39PM -0300, Gustavo Sousa wrote:
> In an upcoming change related to Xe3p_LPD, we will need to (i) update
> wm[0] in adjust_wm_latency() and (ii) do the same increase_wm_latency()
> that is currently done when (wm[0] == 0).
>
> Because make_wm_latency_monotonic() depends on wm[0], part (i) needs to
> be done before it gets called. In order to keep (i) and (ii) as a
> contiguous logical sequence, let's reorder adjust_wm_latency(), making
> make_wm_latency_monotonic() the last thing to be done.
>
> Also take this opportunity to simplify the code by doing the call to
> increase_wm_latency() only once.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index c141d575009f..57260a2a765a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3213,14 +3213,13 @@ static void
> adjust_wm_latency(struct intel_display *display)
> {
> u16 *wm = display->wm.skl_latency;
> + int inc = 0;
>
> if (display->platform.dg2)
> multiply_wm_latency(display, 2);
>
> sanitize_wm_latency(display);
>
> - make_wm_latency_monotonic(display);
> -
I was thinking that by doing this early we avoid potentially papering
over our own bugs in the later adjustments. But Windows does appear to
do this after the read latency adjustment.
And it looks like Windows actually stopped doing this for xe3 and now
it rejects non-monotonic values. And it also does that after the read
latency adjustment.
So I guess what we want to do is move this later, only call it for
pre-xe3, and add another step after it to validate that the latencies
are indeed monotonic.
> /*
> * WaWmMemoryReadLatency
> *
> @@ -3229,7 +3228,7 @@ adjust_wm_latency(struct intel_display *display)
> * from the punit when level 0 response data is 0us.
> */
> if (wm[0] == 0)
> - increase_wm_latency(display, wm_read_latency(display));
> + inc += wm_read_latency(display);
>
> /*
> * WA Level-0 adjustment for 16Gb+ DIMMs: SKL+
> @@ -3238,7 +3237,12 @@ adjust_wm_latency(struct intel_display *display)
> * to avoid any underrun.
> */
> if (need_16gb_dimm_wa(display))
> - increase_wm_latency(display, 1);
> + inc += 1;
> +
> + if (inc)
> + increase_wm_latency(display, inc);
I don't see that variable being helpful in any real way.
Just makes the function more complicated for no good reason.
It also has nothing to do with the rest of this patch.
> +
> + make_wm_latency_monotonic(display);
> }
>
> static void mtl_read_wm_latency(struct intel_display *display)
>
> --
> 2.51.0
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-10-29 22:22 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 0:28 [PATCH v2 00/32] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 01/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 02/32] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 03/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 04/32] drm/i915/dram: Add field ecc_impacting_de_bw Gustavo Sousa
2025-10-22 11:37 ` Gustavo Sousa
2025-10-22 11:53 ` Jani Nikula
2025-10-22 12:12 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 05/32] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
2025-10-22 14:56 ` Matt Roper
2025-10-27 22:26 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 06/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 07/32] drm/i915/xe3p_lpd: Support UINT16 formats Gustavo Sousa
2025-10-22 12:28 ` Ville Syrjälä
2025-10-22 17:58 ` Matt Roper
2025-10-27 19:41 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 08/32] drm/i915/xe3p_lpd: Extend FBC support to " Gustavo Sousa
2025-10-22 12:39 ` Ville Syrjälä
2025-10-22 0:28 ` [PATCH v2 09/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 10/32] drm/i915/xe3p_lpd: Wait for AUX channel power status Gustavo Sousa
2025-10-29 20:06 ` Matt Roper
2025-10-29 20:50 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 11/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints Gustavo Sousa
2025-10-29 20:54 ` Matt Roper
2025-10-30 21:56 ` Gustavo Sousa
2025-10-31 22:17 ` Matt Roper
2025-10-31 22:41 ` Gustavo Sousa
2025-11-11 0:44 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 12/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 13/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
2025-10-29 21:22 ` Matt Roper
2025-10-31 2:48 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 14/32] drm/i915/wm: Reorder adjust_wm_latency() for Xe3_LPD Gustavo Sousa
2025-10-29 21:53 ` Matt Roper
2025-10-29 22:22 ` Ville Syrjälä [this message]
2025-10-29 22:36 ` Ville Syrjälä
2025-10-30 13:45 ` Gustavo Sousa
2025-10-30 15:38 ` Ville Syrjälä
2025-10-30 13:48 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment Gustavo Sousa
2025-10-29 22:08 ` Matt Roper
2025-10-29 22:39 ` Ville Syrjälä
2025-10-30 13:53 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 16/32] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 17/32] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4 Gustavo Sousa
2025-10-29 22:14 ` Matt Roper
2025-10-31 17:36 ` Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 20/32] drm/i915/xe3p_lpd: Enable system caching for FBC Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 28/32] drm/i915/power: Use intel_encoder_is_tc() Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc() Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
2025-10-22 15:08 ` Shekhar Chauhan
2025-10-22 0:28 ` [PATCH v2 31/32] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation Gustavo Sousa
2025-10-22 0:28 ` [PATCH v2 32/32] drm/i915/nvls: Add NVL-S display support Gustavo Sousa
2025-10-22 15:12 ` Shekhar Chauhan
2025-10-22 1:46 ` ✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev2) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aQKTXsWok4HaRCdv@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=ankit.k.nautiyal@intel.com \
--cc=dnyaneshwar.bhadane@intel.com \
--cc=gustavo.sousa@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jouni.hogander@intel.com \
--cc=juha-pekka.heikkila@intel.com \
--cc=lucas.demarchi@intel.com \
--cc=luciano.coelho@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=matthew.s.atwood@intel.com \
--cc=ravi.kumar.vodapalli@intel.com \
--cc=shekhar.chauhan@intel.com \
--cc=vinod.govindapillai@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).