[PATCH 0/7] drm/i915: Stop the intel_de_wait_custom() abuse

[PATCH 0/7] drm/i915: Stop the intel_de_wait_custom() abuse

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of all the custom fast vs. slow intel_de_wait_custom()
timeouts that have started to spread like a cancer recently.

The eventual aim is to get rid of the fast vs. slow timeout
stuff entirely and switch over to poll_timeout_us()...

Ville Syrjälä (7):
  drm/i915/cx0: Undo the unjustified timeout change
  drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US
  drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/
  drm/i915/cx0:
    s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/
  drm/i915/ltphy: Nuke bogus weird timeouts
  drm/i915/hdcp: Use the default 2 usec fast polling timeout
  drm/i915/pmdemand: Use the default 2 usec fast polling timeout

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 19 +++++++++----------
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  5 ++---
 drivers/gpu/drm/i915/display/intel_hdcp.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 13 ++++++-------
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  1 -
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 6 files changed, 19 insertions(+), 23 deletions(-)

-- 
2.49.1

[PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Undo the bogus timeout change to
intel_cx0_powerdown_change_sequence(). If this was intentional
then it should have been justifie in the commit message.

This is also now abusing intel_de_wait_custom() in way that
prevents future conversion to poll_timeout_us().

Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b3b506d0e040..e7fe974129fe 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2830,7 +2830,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	/* Update Timeout Value */
 	if (intel_de_wait_custom(display, buf_ctl2_reg,
 				 intel_cx0_get_powerdown_update(lane_mask), 0,
-				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
+				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
-- 
2.49.1

[PATCH 2/7] drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

XELPDP_MSGBUS_TIMEOUT_FAST_US looks to be just a obfuscated version
of the default 2 microsecond fast timeout used by
intel_wait_for_register(). get rid of it to make it clear what's going
on here.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 3 +--
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e7fe974129fe..6f57ad751c9e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -168,8 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
 				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
 				 XELPDP_PORT_P2M_RESPONSE_READY,
 				 XELPDP_PORT_P2M_RESPONSE_READY,
-				 XELPDP_MSGBUS_TIMEOUT_FAST_US,
-				 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
 			    phy_name(phy), *val);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 635b35669348..67c6f06ab9a2 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -75,7 +75,6 @@
 #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
 
 #define XELPDP_MSGBUS_TIMEOUT_SLOW			1
-#define XELPDP_MSGBUS_TIMEOUT_FAST_US			2
 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
-- 
2.49.1

[PATCH 3/7] drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The slow vs. fast timeout stuff is really just an implementation
detail. Let's not spread that terminology in random timeout defines.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 12 ++++++------
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h |  2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c       |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6f57ad751c9e..55ce4f673c63 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -147,7 +147,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_RESET,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_err_once(display->drm,
 			     "Failed to bring PHY %c to idle.\n",
 			     phy_name(phy));
@@ -168,7 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
 				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
 				 XELPDP_PORT_P2M_RESPONSE_READY,
 				 XELPDP_PORT_P2M_RESPONSE_READY,
-				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+				 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
 			    phy_name(phy), *val);
@@ -215,7 +215,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -286,7 +286,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -302,7 +302,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
 		intel_cx0_bus_reset(encoder, lane);
@@ -2815,7 +2815,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
 	for_each_cx0_lane_in_mask(lane_mask, lane)
 		if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
-					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+					    XELPDP_MSGBUS_TIMEOUT_MS)) {
 			drm_dbg_kms(display->drm,
 				    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
 				    phy_name(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 67c6f06ab9a2..bd62c396c837 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -74,7 +74,7 @@
 #define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
 #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
 
-#define XELPDP_MSGBUS_TIMEOUT_SLOW			1
+#define XELPDP_MSGBUS_TIMEOUT_MS			1
 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index af48d6cde226..6fb68157b322 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1043,7 +1043,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
 				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
-				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+				    XELPDP_MSGBUS_TIMEOUT_MS)) {
 		drm_dbg_kms(display->drm,
 			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
 			    phy_name(phy));
-- 
2.49.1

[PATCH 4/7] drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT
to make it match all its other counterparts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 55ce4f673c63..7c9c181aba8a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2926,10 +2926,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
 
 	if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
 				    lane_phy_current_status,
-				    XELPDP_PORT_RESET_END_TIMEOUT))
+				    XELPDP_PORT_RESET_END_TIMEOUT_US))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dms.\n",
-			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
+			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT_US);
 }
 
 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bd62c396c837..77244a5d52d4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -80,7 +80,7 @@
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
 #define XELPDP_PORT_RESET_START_TIMEOUT_US		5
 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US		100
-#define XELPDP_PORT_RESET_END_TIMEOUT			15
+#define XELPDP_PORT_RESET_END_TIMEOUT_US		15
 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
 
 #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004
-- 
2.49.1

[PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
ways. Get rid of the weird slow timeouts. If these are actually needed
then the fast timeouts should really be specified as the default 2
microscond or something.

This will let us eventually nuke intel_de_wait_custom() and convert
over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
 drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6fb68157b322..cc1d6b7a7de4 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
 				 XELPDP_LANE_PCLK_PLL_ACK(0),
 				 XELPDP_LANE_PCLK_PLL_ACK(0),
-				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
-				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
+				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
 		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
-			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
+			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
 
 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
 		     XELPDP_FORWARD_CLOCK_UNGATE,
@@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
 
 	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
 				 lane_phy_current_status, 0,
-				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
+				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
 		drm_warn(display->drm,
 			 "PHY %c failed to bring out of Lane reset after %dus.\n",
 			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
@@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
 					 XELPDP_LANE_PCLK_PLL_ACK(0),
 					 XELPDP_LANE_PCLK_PLL_ACK(0),
-					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
+					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
 			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
 				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
 
@@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
 		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
 		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
 					 lane_phy_pulse_status, lane_phy_pulse_status,
-					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
+					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
 			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
 				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 9223487d764e..36abc2bdbd9b 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -7,7 +7,6 @@
 #define __INTEL_LT_PHY_REGS_H__
 
 #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
-#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
 #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
 #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
-- 
2.49.1

[PATCH 6/7] drm/i915/hdcp: Use the default 2 usec fast polling timeout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For whatever unknown reason the HDCP code is using a custom
10 usec fast polling timeout instead of the normal 2 usec
value. Switch to the standard value to get rid of the special
case.

The eventual aim is to get rid of the fast vs. slow timeout
entirely and switch over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7195e8cf671c..d01733b6460e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -412,7 +412,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
 	/* Wait for the keys to load (500us) */
 	ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
 				   HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
-				   10, 1, &val);
+				   2, 1, &val);
 	if (ret)
 		return ret;
 	else if (!(val & HDCP_KEY_LOAD_STATUS))
-- 
2.49.1

[PATCH 7/7] drm/i915/pmdemand: Use the default 2 usec fast polling timeout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For whatever unknown reason the pmdemand code is using a custom
50 usec fast polling timeout instead of the normal 2 usec
value. Switch to the standard value to get rid of the special
case.

The eventual aim is to get rid of the fast vs. slow timeout
entirely and switch over to poll_timeout_us().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f52abd4e2eb0..22d8f720ae7d 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -464,7 +464,7 @@ static void intel_pmdemand_poll(struct intel_display *display)
 
 	ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
 				   XELPDP_PMDEMAND_REQ_ENABLE, 0,
-				   50, timeout_ms, &status);
+				   2, timeout_ms, &status);
 
 	if (ret == -ETIMEDOUT)
 		drm_err(display->drm,
-- 
2.49.1

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
> ways. Get rid of the weird slow timeouts. If these are actually needed
> then the fast timeouts should really be specified as the default 2
> microscond or something.
>
> This will let us eventually nuke intel_de_wait_custom() and convert
> over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cc: Suraj, yeah, why are these intel_de_wait_custom() in the first
place?

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6fb68157b322..cc1d6b7a7de4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
> -			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE,
> @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				 lane_phy_current_status, 0,
> -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
> @@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> -					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> +					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>  				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
> @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
>  		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  					 lane_phy_pulse_status, lane_phy_pulse_status,
> -					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
>  				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..36abc2bdbd9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -7,7 +7,6 @@
>  #define __INTEL_LT_PHY_REGS_H__
>  
>  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

-- 
Jani Nikula, Intel

✗ i915.CI.BAT: failure for drm/i915: Stop the intel_de_wait_custom() abuse

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7162 bytes --]

== Series Details ==

Series: drm/i915: Stop the intel_de_wait_custom() abuse
URL   : https://patchwork.freedesktop.org/series/157097/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17492 -> Patchwork_157097v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157097v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157097v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/index.html

Participating hosts (45 -> 45)
------------------------------

  Additional (1): bat-adls-6 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157097v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@reload:
    - fi-cfl-8109u:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/fi-cfl-8109u/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/fi-cfl-8109u/igt@i915_module_load@reload.html

  
Known issues
------------

  Here are the changes found in Patchwork_157097v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adls-6:         NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - bat-adls-6:         NOTRUN -> [SKIP][4] ([i915#3282])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-arlh-2:         [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/bat-arlh-2/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-arlh-2/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#7707]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adls-6:         NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#3555] / [i915#3840])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adls-6:         NOTRUN -> [SKIP][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adls-6:         NOTRUN -> [SKIP][13] ([i915#5354])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-adls-6:         NOTRUN -> [SKIP][14] ([i915#1072] / [i915#9732]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adls-6:         NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adls-6:         NOTRUN -> [SKIP][16] ([i915#3291]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-adls-6/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][17] ([i915#12061]) -> [PASS][18] +1 other test pass
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][19] ([i915#12061] / [i915#14204]) -> [DMESG-FAIL][20] ([i915#12061] / [i915#13929])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/bat-atsm-1/igt@i915_selftest@live.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][21] ([i915#14204]) -> [DMESG-FAIL][22] ([i915#13929])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17492/bat-atsm-1/igt@i915_selftest@live@mman.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_17492 -> Patchwork_157097v1

  CI-20190529: 20190529
  CI_DRM_17492: d296e1cac1210831a20d7f0370346adfa037e422 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8607: 8607
  Patchwork_157097v1: d296e1cac1210831a20d7f0370346adfa037e422 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157097v1/index.html

[-- Attachment #2: Type: text/html, Size: 8673 bytes --]

Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Undo the bogus timeout change to
> intel_cx0_powerdown_change_sequence(). If this was intentional
> then it should have been justifie in the commit message.
>
> This is also now abusing intel_de_wait_custom() in way that
> prevents future conversion to poll_timeout_us().
>
> Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b3b506d0e040..e7fe974129fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2830,7 +2830,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>  	/* Update Timeout Value */
>  	if (intel_de_wait_custom(display, buf_ctl2_reg,
>  				 intel_cx0_get_powerdown_update(lane_mask), 0,
> -				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
> +				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);

-- 
Jani Nikula, Intel

Re: [PATCH 2/7] drm/i915/cx0: Get rid of XELPDP_MSGBUS_TIMEOUT_FAST_US

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> XELPDP_MSGBUS_TIMEOUT_FAST_US looks to be just a obfuscated version

*an

> of the default 2 microsecond fast timeout used by
> intel_wait_for_register(). get rid of it to make it clear what's going
> on here.

*Get

Moreover, I don't like timeouts being defined along with what are
supposed to be register *content* descriptions.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 3 +--
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 -
>  2 files changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index e7fe974129fe..6f57ad751c9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -168,8 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
>  				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
> -				 XELPDP_MSGBUS_TIMEOUT_FAST_US,
> -				 XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> +				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
>  			    phy_name(phy), *val);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 635b35669348..67c6f06ab9a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -75,7 +75,6 @@
>  #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
>  
>  #define XELPDP_MSGBUS_TIMEOUT_SLOW			1
> -#define XELPDP_MSGBUS_TIMEOUT_FAST_US			2
>  #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
>  #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100

-- 
Jani Nikula, Intel

Re: [PATCH 3/7] drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The slow vs. fast timeout stuff is really just an implementation
> detail. Let's not spread that terminology in random timeout defines.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 12 ++++++------
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c       |  2 +-
>  3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6f57ad751c9e..55ce4f673c63 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -147,7 +147,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_RESET,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_err_once(display->drm,
>  			     "Failed to bring PHY %c to idle.\n",
>  			     phy_name(phy));
> @@ -168,7 +168,7 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
>  				 XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
>  				 XELPDP_PORT_P2M_RESPONSE_READY,
> -				 2, XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> +				 2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
>  			    phy_name(phy), *val);
> @@ -215,7 +215,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -286,7 +286,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -302,7 +302,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
>  		intel_cx0_bus_reset(encoder, lane);
> @@ -2815,7 +2815,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>  	for_each_cx0_lane_in_mask(lane_mask, lane)
>  		if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  					    XELPDP_PORT_M2P_TRANSACTION_PENDING,
> -					    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +					    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  			drm_dbg_kms(display->drm,
>  				    "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
>  				    phy_name(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 67c6f06ab9a2..bd62c396c837 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -74,7 +74,7 @@
>  #define   XELPDP_PORT_P2M_DATA(val)			REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
>  #define   XELPDP_PORT_P2M_ERROR_SET			REG_BIT(15)
>  
> -#define XELPDP_MSGBUS_TIMEOUT_SLOW			1
> +#define XELPDP_MSGBUS_TIMEOUT_MS			1
>  #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US		3200
>  #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US		20
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index af48d6cde226..6fb68157b322 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1043,7 +1043,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
>  				    XELPDP_PORT_P2P_TRANSACTION_PENDING,
> -				    XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +				    XELPDP_MSGBUS_TIMEOUT_MS)) {
>  		drm_dbg_kms(display->drm,
>  			    "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n",
>  			    phy_name(phy));

-- 
Jani Nikula, Intel

Re: [PATCH 4/7] drm/i915/cx0: s/XELPDP_PORT_RESET_END_TIMEOUT/XELPDP_PORT_RESET_END_TIMEOUT_US/

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Include the units the in the define name for XELPDP_PORT_RESET_END_TIMEOUT
> to make it match all its other counterparts.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 55ce4f673c63..7c9c181aba8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2926,10 +2926,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				    lane_phy_current_status,
> -				    XELPDP_PORT_RESET_END_TIMEOUT))
> +				    XELPDP_PORT_RESET_END_TIMEOUT_US))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dms.\n",
> -			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> +			 phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT_US);
>  }
>  
>  static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index bd62c396c837..77244a5d52d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -80,7 +80,7 @@
>  #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US		100
>  #define XELPDP_PORT_RESET_START_TIMEOUT_US		5
>  #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US		100
> -#define XELPDP_PORT_RESET_END_TIMEOUT			15
> +#define XELPDP_PORT_RESET_END_TIMEOUT_US		15
>  #define XELPDP_REFCLK_ENABLE_TIMEOUT_US			1
>  
>  #define _XELPDP_PORT_BUF_CTL1_LN0_A			0x64004

-- 
Jani Nikula, Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
> ways. Get rid of the weird slow timeouts. If these are actually needed
> then the fast timeouts should really be specified as the default 2
> microscond or something.
>
> This will let us eventually nuke intel_de_wait_custom() and convert
> over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Suraj, any input here?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6fb68157b322..cc1d6b7a7de4 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
> +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
> -			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> +			 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
>  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  		     XELPDP_FORWARD_CLOCK_UNGATE,
> @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
>  
>  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  				 lane_phy_current_status, 0,
> -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>  		drm_warn(display->drm,
>  			 "PHY %c failed to bring out of Lane reset after %dus.\n",
>  			 phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
> @@ -1674,7 +1673,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> -					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> +					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
>  				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
>  
> @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
>  		if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
>  					 lane_phy_pulse_status, lane_phy_pulse_status,
> -					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> +					 XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>  			drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
>  				 phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..36abc2bdbd9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -7,7 +7,6 @@
>  #define __INTEL_LT_PHY_REGS_H__
>  
>  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

-- 
Jani Nikula, Intel

Re: [PATCH 6/7] drm/i915/hdcp: Use the default 2 usec fast polling timeout

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For whatever unknown reason the HDCP code is using a custom
> 10 usec fast polling timeout instead of the normal 2 usec
> value. Switch to the standard value to get rid of the special
> case.
>
> The eventual aim is to get rid of the fast vs. slow timeout
> entirely and switch over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 7195e8cf671c..d01733b6460e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -412,7 +412,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
>  	/* Wait for the keys to load (500us) */
>  	ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
>  				   HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
> -				   10, 1, &val);
> +				   2, 1, &val);
>  	if (ret)
>  		return ret;
>  	else if (!(val & HDCP_KEY_LOAD_STATUS))

-- 
Jani Nikula, Intel

Re: [PATCH 7/7] drm/i915/pmdemand: Use the default 2 usec fast polling timeout

[Jani Nikula]

On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For whatever unknown reason the pmdemand code is using a custom
> 50 usec fast polling timeout instead of the normal 2 usec
> value. Switch to the standard value to get rid of the special
> case.
>
> The eventual aim is to get rid of the fast vs. slow timeout
> entirely and switch over to poll_timeout_us().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f52abd4e2eb0..22d8f720ae7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -464,7 +464,7 @@ static void intel_pmdemand_poll(struct intel_display *display)
>  
>  	ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
>  				   XELPDP_PMDEMAND_REQ_ENABLE, 0,
> -				   50, timeout_ms, &status);
> +				   2, timeout_ms, &status);
>  
>  	if (ret == -ETIMEDOUT)
>  		drm_err(display->drm,

-- 
Jani Nikula, Intel

RE: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Kandpal, Suraj]

> Subject: Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change
> 
> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Undo the bogus timeout change to
> > intel_cx0_powerdown_change_sequence(). If this was intentional then it
> > should have been justifie in the commit message.
> >
> > This is also now abusing intel_de_wait_custom() in way that prevents
> > future conversion to poll_timeout_us().
> >
> > Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy
> > powerdown change sequence")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index b3b506d0e040..e7fe974129fe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2830,7 +2830,7 @@ void
> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> >  	/* Update Timeout Value */
> >  	if (intel_de_wait_custom(display, buf_ctl2_reg,
> >
> intel_cx0_get_powerdown_update(lane_mask), 0,
> > -
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
> > +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))

According to Bspec: 74494
The powerdown change update delay can go from anywhere to 2us to
1.2ms

Regards,
Suraj Kandpal

> >  		drm_warn(display->drm,
> >  			 "PHY %c failed to bring out of Lane reset after
> %dus.\n",
> >  			 phy_name(phy),
> XELPDP_PORT_RESET_START_TIMEOUT_US);
> 
> --
> Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > weird ways. Get rid of the weird slow timeouts. If these are actually
> > needed then the fast timeouts should really be specified as the
> > default 2 microscond or something.
> >
> > This will let us eventually nuke intel_de_wait_custom() and convert
> > over to poll_timeout_us().
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Suraj, any input here?
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> >  2 files changed, 5 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 6fb68157b322..cc1d6b7a7de4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> *encoder,
> >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> port),
> >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> NULL))
> > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> NULL))
> >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> not done after %dus.\n",
> > -			 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > +			 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_US);

According to Bspec: 74499
Latency can be either 21us for 1ms depending on what port is connected.

 > >
> >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> >
> >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> port),
> >  				 lane_phy_current_status, 0,
> > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))

Bspec : 74499
Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly


> >  		drm_warn(display->drm,
> >  			 "PHY %c failed to bring out of Lane reset after
> %dus.\n",
> >  			 phy_name(phy),
> XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >  		if (intel_de_wait_custom(display,
> XELPDP_PORT_CLOCK_CTL(display, port),
> >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > -
> XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > +
> XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))

Ditto here.

> >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> assertion Timeout after %dus.\n",
> >  				 phy_name(phy),
> XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >
> > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> *encoder,
> >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> for Owned PHY Lanes. */
> >  		if (intel_de_wait_custom(display,
> XELPDP_PORT_BUF_CTL2(display, port),
> >  					 lane_phy_pulse_status,
> lane_phy_pulse_status,
> > -
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > +
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))

Ditto here.
I would suggest giving this a CI run on NVLS before merging this.

Regards,
Suraj Kandpal

> >  			drm_warn(display->drm, "PHY %c PLL rate not
> changed after %dus.\n",
> >  				 phy_name(phy),
> XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > index 9223487d764e..36abc2bdbd9b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > @@ -7,7 +7,6 @@
> >  #define __INTEL_LT_PHY_REGS_H__
> >
> >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> 
> --
> Jani Nikula, Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjälä]

On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> > 
> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > > weird ways. Get rid of the weird slow timeouts. If these are actually
> > > needed then the fast timeouts should really be specified as the
> > > default 2 microscond or something.
> > >
> > > This will let us eventually nuke intel_de_wait_custom() and convert
> > > over to poll_timeout_us().
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Suraj, any input here?
> > 
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> > >  2 files changed, 5 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > index 6fb68157b322..cc1d6b7a7de4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > *encoder,
> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> > port),
> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> > NULL))
> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> > NULL))
> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> > not done after %dus.\n",
> > > -			 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > > +			 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> 
> According to Bspec: 74499
> Latency can be either 21us for 1ms depending on what port is connected.
> 
>  > >
> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > *encoder,
> > >
> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > port),
> > >  				 lane_phy_current_status, 0,
> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> 
> Bspec : 74499
> Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
> 
> 
> > >  		drm_warn(display->drm,
> > >  			 "PHY %c failed to bring out of Lane reset after
> > %dus.\n",
> > >  			 phy_name(phy),
> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > >  		if (intel_de_wait_custom(display,
> > XELPDP_PORT_CLOCK_CTL(display, port),
> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > -
> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > > +
> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> 
> Ditto here.
> 
> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> > assertion Timeout after %dus.\n",
> > >  				 phy_name(phy),
> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > >
> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > *encoder,
> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> > for Owned PHY Lanes. */
> > >  		if (intel_de_wait_custom(display,
> > XELPDP_PORT_BUF_CTL2(display, port),
> > >  					 lane_phy_pulse_status,
> > lane_phy_pulse_status,
> > > -
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > > +
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> 
> Ditto here.
> I would suggest giving this a CI run on NVLS before merging this.

Since you have some idea why these magic numbers were chosen
please redo all of these, and make sure to:
- don't use intel_de_wait_custom() unless absolutely necessary
- if you need to use intel_de_wait_custom() then either
  use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
- document all the used timeouts. This is especially important
  when they are not directly specified in bspec

> 
> Regards,
> Suraj Kandpal
> 
> > >  			drm_warn(display->drm, "PHY %c PLL rate not
> > changed after %dus.\n",
> > >  				 phy_name(phy),
> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > index 9223487d764e..36abc2bdbd9b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > @@ -7,7 +7,6 @@
> > >  #define __INTEL_LT_PHY_REGS_H__
> > >
> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> > 
> > --
> > Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

RE: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change

[Jani Nikula]

On Thu, 06 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: Re: [PATCH 1/7] drm/i915/cx0: Undo the unjustified timeout change
>> 
>> On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Undo the bogus timeout change to
>> > intel_cx0_powerdown_change_sequence(). If this was intentional then it
>> > should have been justifie in the commit message.
>> >
>> > This is also now abusing intel_de_wait_custom() in way that prevents
>> > future conversion to poll_timeout_us().
>> >
>> > Fixes: fc9be0a10ca4 ("drm/i915/ltphy: Add a wrapper for LT Phy
>> > powerdown change sequence")
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > index b3b506d0e040..e7fe974129fe 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> > @@ -2830,7 +2830,7 @@ void
>> intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
>> >  	/* Update Timeout Value */
>> >  	if (intel_de_wait_custom(display, buf_ctl2_reg,
>> >
>> intel_cx0_get_powerdown_update(lane_mask), 0,
>> > -
>> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
>> > +
>> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
>
> According to Bspec: 74494
> The powerdown change update delay can go from anywhere to 2us to
> 1.2ms

Then use intel_de_wait_for_clear() with a 2 ms timeout. There's no
reason to use intel_de_wait_custom().

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Ville Syrjälä]

On Thu, Nov 06, 2025 at 03:12:34PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> > > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> > > 
> > > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> > > > weird ways. Get rid of the weird slow timeouts. If these are actually
> > > > needed then the fast timeouts should really be specified as the
> > > > default 2 microscond or something.
> > > >
> > > > This will let us eventually nuke intel_de_wait_custom() and convert
> > > > over to poll_timeout_us().
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Suraj, any input here?
> > > 
> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> > > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> > > >  2 files changed, 5 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index 6fb68157b322..cc1d6b7a7de4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > *encoder,
> > > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
> > > port),
> > > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> > > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> > > NULL))
> > > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> > > NULL))
> > > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> > > not done after %dus.\n",
> > > > -			 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> > > > +			 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > 
> > According to Bspec: 74499
> > Latency can be either 21us for 1ms depending on what port is connected.
> > 
> >  > >
> > > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> > > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
> > > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
> > > > *encoder,
> > > >
> > > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> > > port),
> > > >  				 lane_phy_current_status, 0,
> > > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> > > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> > 
> > Bspec : 74499
> > Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
> > 
> > 
> > > >  		drm_warn(display->drm,
> > > >  			 "PHY %c failed to bring out of Lane reset after
> > > %dus.\n",
> > > >  			 phy_name(phy),
> > > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> > > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> > > >  		if (intel_de_wait_custom(display,
> > > XELPDP_PORT_CLOCK_CTL(display, port),
> > > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> > > > -
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> > > > +
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> > 
> > Ditto here.
> > 
> > > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> > > assertion Timeout after %dus.\n",
> > > >  				 phy_name(phy),
> > > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> > > >
> > > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
> > > *encoder,
> > > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> > > for Owned PHY Lanes. */
> > > >  		if (intel_de_wait_custom(display,
> > > XELPDP_PORT_BUF_CTL2(display, port),
> > > >  					 lane_phy_pulse_status,
> > > lane_phy_pulse_status,
> > > > -
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> > > > +
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> > 
> > Ditto here.
> > I would suggest giving this a CI run on NVLS before merging this.
> 
> Since you have some idea why these magic numbers were chosen
> please redo all of these, and make sure to:
> - don't use intel_de_wait_custom() unless absolutely necessary
> - if you need to use intel_de_wait_custom() then either
>   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> - document all the used timeouts. This is especially important
>   when they are not directly specified in bspec
> 
> > 
> > Regards,
> > Suraj Kandpal
> > 
> > > >  			drm_warn(display->drm, "PHY %c PLL rate not
> > > changed after %dus.\n",
> > > >  				 phy_name(phy),
> > > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > index 9223487d764e..36abc2bdbd9b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> > > > @@ -7,7 +7,6 @@
> > > >  #define __INTEL_LT_PHY_REGS_H__
> > > >
> > > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> > > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> > > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> > > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> > > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50

Oh,and these do not belong in the regs.h file. If you feel the need
to have names for these (eg. if they are used multiple times) then
just put them in the .c file.

-- 
Ville Syrjälä
Intel

Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Thu, 06 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
>> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
>> > 
>> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > >
>> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
>> > > weird ways. Get rid of the weird slow timeouts. If these are actually
>> > > needed then the fast timeouts should really be specified as the
>> > > default 2 microscond or something.
>> > >
>> > > This will let us eventually nuke intel_de_wait_custom() and convert
>> > > over to poll_timeout_us().
>> > >
>> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > 
>> > Suraj, any input here?
>> > 
>> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> > 
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
>> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
>> > >  2 files changed, 5 insertions(+), 7 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > index 6fb68157b322..cc1d6b7a7de4 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
>> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct intel_encoder
>> > *encoder,
>> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display,
>> > port),
>> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
>> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
>> > NULL))
>> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
>> > NULL))
>> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
>> > not done after %dus.\n",
>> > > -			 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
>> > > +			 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
>> 
>> According to Bspec: 74499
>> Latency can be either 21us for 1ms depending on what port is connected.
>> 
>>  > >
>> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
>> > >  		     XELPDP_FORWARD_CLOCK_UNGATE,
>> > > @@ -1192,7 +1191,7 @@ intel_lt_phy_lane_reset(struct intel_encoder
>> > > *encoder,
>> > >
>> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
>> > port),
>> > >  				 lane_phy_current_status, 0,
>> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
>> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
>> 
>> Bspec : 74499
>> Says 200us but 2ms (1.5ms to be precise) was the actual time we found the this to work properly
>> 
>> 
>> > >  		drm_warn(display->drm,
>> > >  			 "PHY %c failed to bring out of Lane reset after
>> > %dus.\n",
>> > >  			 phy_name(phy),
>> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
>> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
>> > >  		if (intel_de_wait_custom(display,
>> > XELPDP_PORT_CLOCK_CTL(display, port),
>> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
>> > > -
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
>> > > +
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
>> 
>> Ditto here.
>> 
>> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
>> > assertion Timeout after %dus.\n",
>> > >  				 phy_name(phy),
>> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
>> > >
>> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder
>> > *encoder,
>> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
>> > for Owned PHY Lanes. */
>> > >  		if (intel_de_wait_custom(display,
>> > XELPDP_PORT_BUF_CTL2(display, port),
>> > >  					 lane_phy_pulse_status,
>> > lane_phy_pulse_status,
>> > > -
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
>> > > +
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
>> 
>> Ditto here.
>> I would suggest giving this a CI run on NVLS before merging this.
>
> Since you have some idea why these magic numbers were chosen
> please redo all of these, and make sure to:
> - don't use intel_de_wait_custom() unless absolutely necessary
> - if you need to use intel_de_wait_custom() then either
>   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> - document all the used timeouts. This is especially important
>   when they are not directly specified in bspec

Yeah, should be intel_de_wait_for_{set,clear}() then probably.

We should probably change all of those from ms to us units to make them
more generally useful also for shorter waits.

BR,
Jni.


>
>> 
>> Regards,
>> Suraj Kandpal
>> 
>> > >  			drm_warn(display->drm, "PHY %c PLL rate not
>> > changed after %dus.\n",
>> > >  				 phy_name(phy),
>> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > index 9223487d764e..36abc2bdbd9b 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
>> > > @@ -7,7 +7,6 @@
>> > >  #define __INTEL_LT_PHY_REGS_H__
>> > >
>> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
>> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
>> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
>> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
>> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
>> > 
>> > --
>> > Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, November 6, 2025 6:49 PM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Thu, 06 Nov 2025, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Nov 06, 2025 at 12:03:28PM +0000, Kandpal, Suraj wrote:
> >> > Subject: Re: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> >> >
> >> > On Wed, 05 Nov 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > >
> >> > > The LT PHY code is abusing intel_de_wait_custom() in all kinds of
> >> > > weird ways. Get rid of the weird slow timeouts. If these are
> >> > > actually needed then the fast timeouts should really be specified
> >> > > as the default 2 microscond or something.
> >> > >
> >> > > This will let us eventually nuke intel_de_wait_custom() and
> >> > > convert over to poll_timeout_us().
> >> > >
> >> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > Suraj, any input here?
> >> >
> >> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >> >
> >> > > ---
> >> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c      | 11 +++++------
> >> > >  drivers/gpu/drm/i915/display/intel_lt_phy_regs.h |  1 -
> >> > >  2 files changed, 5 insertions(+), 7 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > index 6fb68157b322..cc1d6b7a7de4 100644
> >> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >> > > @@ -1178,10 +1178,9 @@ intel_lt_phy_lane_reset(struct
> >> > > intel_encoder
> >> > *encoder,
> >> > >  	if (intel_de_wait_custom(display,
> >> > > XELPDP_PORT_CLOCK_CTL(display,
> >> > port),
> >> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > >  				 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_US,
> >> > > -				 XE3PLPD_MACCLK_TURNON_LATENCY_MS,
> >> > NULL))
> >> > > +				 XE3PLPD_MACCLK_TURNON_LATENCY_US, 0,
> >> > NULL))
> >> > >  		drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack
> >> > not done after %dus.\n",
> >> > > -			 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
> >> > > +			 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >>
> >> According to Bspec: 74499
> >> Latency can be either 21us for 1ms depending on what port is connected.
> >>
> >>  > >
> >> > >  	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> >> > >  		     XELPDP_FORWARD_CLOCK_UNGATE, @@ -1192,7 +1191,7
> @@
> >> > > intel_lt_phy_lane_reset(struct intel_encoder *encoder,
> >> > >
> >> > >  	if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display,
> >> > port),
> >> > >  				 lane_phy_current_status, 0,
> >> > > -				 XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
> >> > > +				 XE3PLPD_RESET_END_LATENCY_US, 0, NULL))
> >>
> >> Bspec : 74499
> >> Says 200us but 2ms (1.5ms to be precise) was the actual time we found
> >> the this to work properly
> >>
> >>
> >> > >  		drm_warn(display->drm,
> >> > >  			 "PHY %c failed to bring out of Lane reset after
> >> > %dus.\n",
> >> > >  			 phy_name(phy),
> >> > XE3PLPD_RESET_END_LATENCY_US); @@ -1674,7 +1673,7
> >> > > @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
> >> > >  		if (intel_de_wait_custom(display,
> >> > XELPDP_PORT_CLOCK_CTL(display, port),
> >> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > >  					 XELPDP_LANE_PCLK_PLL_ACK(0),
> >> > > -
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
> >> > > +
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US, 0, NULL))
> >>
> >> Ditto here.
> >>
> >> > >  			drm_warn(display->drm, "PHY %c PLL MacCLK Ack
> >> > assertion Timeout after %dus.\n",
> >> > >  				 phy_name(phy),
> >> > XE3PLPD_MACCLK_TURNON_LATENCY_US);
> >> > >
> >> > > @@ -1702,7 +1701,7 @@ void intel_lt_phy_pll_enable(struct
> >> > > intel_encoder
> >> > *encoder,
> >> > >  		/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1
> >> > for Owned PHY Lanes. */
> >> > >  		if (intel_de_wait_custom(display,
> >> > XELPDP_PORT_BUF_CTL2(display, port),
> >> > >  					 lane_phy_pulse_status,
> >> > lane_phy_pulse_status,
> >> > > -
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
> >> > > +
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
> >>
> >> Ditto here.
> >> I would suggest giving this a CI run on NVLS before merging this.
> >
> > Since you have some idea why these magic numbers were chosen please
> > redo all of these, and make sure to:
> > - don't use intel_de_wait_custom() unless absolutely necessary
> > - if you need to use intel_de_wait_custom() then either
> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> > - document all the used timeouts. This is especially important
> >   when they are not directly specified in bspec
> 
> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
> 
> We should probably change all of those from ms to us units to make them
> more generally useful also for shorter waits.

Sure let me take care of the lt phy and cx0 phy stuff in a separate series then

Regards,
Suraj Kandpal

> 
> BR,
> Jni.
> 
> 
> >
> >>
> >> Regards,
> >> Suraj Kandpal
> >>
> >> > >  			drm_warn(display->drm, "PHY %c PLL rate not
> >> > changed after %dus.\n",
> >> > >  				 phy_name(phy),
> >> > XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > index 9223487d764e..36abc2bdbd9b 100644
> >> > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> >> > > @@ -7,7 +7,6 @@
> >> > >  #define __INTEL_LT_PHY_REGS_H__
> >> > >
> >> > >  #define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
> >> > > -#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	1
> >> > >  #define XE3PLPD_MACCLK_TURNON_LATENCY_US	21
> >> > >  #define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
> >> > >  #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US	50
> >> >
> >> > --
> >> > Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Jani Nikula]

On Fri, 07 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> > Since you have some idea why these magic numbers were chosen please
>> > redo all of these, and make sure to:
>> > - don't use intel_de_wait_custom() unless absolutely necessary
>> > - if you need to use intel_de_wait_custom() then either
>> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
>> > - document all the used timeouts. This is especially important
>> >   when they are not directly specified in bspec
>> 
>> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
>> 
>> We should probably change all of those from ms to us units to make them
>> more generally useful also for shorter waits.
>
> Sure let me take care of the lt phy and cx0 phy stuff in a separate series then

This is what Ville followed up with [1].

BR,
Jani.


[1] https://lore.kernel.org/r/20251106152049.21115-1-ville.syrjala@linux.intel.com


-- 
Jani Nikula, Intel

RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts

[Kandpal, Suraj]

> Subject: RE: [PATCH 5/7] drm/i915/ltphy: Nuke bogus weird timeouts
> 
> On Fri, 07 Nov 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> > Since you have some idea why these magic numbers were chosen please
> >> > redo all of these, and make sure to:
> >> > - don't use intel_de_wait_custom() unless absolutely necessary
> >> > - if you need to use intel_de_wait_custom() then either
> >> >   use the default '2,<whatever ms>' or '<whatever us>,0' timeouts
> >> > - document all the used timeouts. This is especially important
> >> >   when they are not directly specified in bspec
> >>
> >> Yeah, should be intel_de_wait_for_{set,clear}() then probably.
> >>
> >> We should probably change all of those from ms to us units to make
> >> them more generally useful also for shorter waits.
> >
> > Sure let me take care of the lt phy and cx0 phy stuff in a separate
> > series then
> 
> This is what Ville followed up with [1].
> 
> BR,
> Jani.
> 
> 
> [1] https://lore.kernel.org/r/20251106152049.21115-1-
> ville.syrjala@linux.intel.com

Yes saw this,
Shouldn't cause any issue the way it is done now.

Regards,
Suraj Kandpal

> 
> 
> --
> Jani Nikula, Intel