From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Hogander, Jouni" <jouni.hogander@intel.com>
Cc: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v4 0/3] Selective Fetch and async flip
Date: Wed, 10 Dec 2025 08:46:28 +0200 [thread overview]
Message-ID: <aTkXRD524f4yeT8g@intel.com> (raw)
In-Reply-To: <a7970dbeb7785e0f63cd50caae7c18e05384d9db.camel@intel.com>
On Wed, Dec 10, 2025 at 06:31:02AM +0000, Hogander, Jouni wrote:
> On Wed, 2025-12-10 at 08:23 +0200, Hogander, Jouni wrote:
> > On Tue, 2025-12-09 at 20:26 +0200, Ville Syrjälä wrote:
> > > On Thu, Dec 04, 2025 at 09:07:15AM +0200, Jouni Högander wrote:
> > > > This patch set contains fixes for Selective Fetch async flip
> > > > sequences. On async flip selective fetch is choosing full frame
> > > > update. Also subsequent flip/update is still using full frame
> > > > update
> > > > to ensure plane with pending async flip is not taken in to
> > > > selective
> > > > fetch/update.
> > > >
> > > > v4:
> > > > - rework if-else if to if-if
> > > > - added comment updated
> > > > - check crtc_state->async_flip_planes in
> > > > psr2_sel_fetch_pipe_state_supported
> > > > v3:
> > > > - rebase
> > > > - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > - fix using intel_atomic_get_new_crtc_state
> > > > v2:
> > > > - check also crtc_state->async_flip_planes in
> > > > psr2_sel_fetch_plane_state_supported
> > > >
> > > > Jouni Högander (3):
> > > > drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes
> > > > for
> > > > PSR
> > > > drm/i915/psr: Perform full frame update on async flip
> > > > drm/i915/psr: Allow async flip when Selective Fetch enabled
> > >
> > > Series is
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > When testing this I saw that we get stuck into full frame mode
> > > all the time. But that seems to be a pre-existing issues caused
> > > by the broken selective fetch area calculation code. I suppose
> > > now that I have a laptop with a PSR2 panel I might have to dig out
> > > that branch of mine where I attempted to rewrite the whoile thing
> > > and figure out what was wrong with it...
> > >
> >
> > What is the SW setup you are using and what kind of testing you are
> > doing? Could it be related to frontbuffer tracking?
>
> Also what is the HW/platform you are using?
This was a LNL.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-12-10 6:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-04 7:07 [PATCH v4 0/3] Selective Fetch and async flip Jouni Högander
2025-12-04 7:07 ` [PATCH v4 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
2025-12-04 7:07 ` [PATCH v4 2/3] drm/i915/psr: Perform full frame update on async flip Jouni Högander
2025-12-04 7:07 ` [PATCH v4 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled Jouni Högander
2025-12-04 8:35 ` ✓ i915.CI.BAT: success for Selective Fetch and async flip (rev5) Patchwork
2025-12-05 16:59 ` ✗ i915.CI.Full: failure " Patchwork
2025-12-10 13:21 ` Hogander, Jouni
2025-12-09 18:26 ` [PATCH v4 0/3] Selective Fetch and async flip Ville Syrjälä
2025-12-10 6:23 ` Hogander, Jouni
2025-12-10 6:31 ` Hogander, Jouni
2025-12-10 6:46 ` Ville Syrjälä [this message]
2025-12-10 6:42 ` Ville Syrjälä
2025-12-10 6:57 ` Hogander, Jouni
2025-12-10 7:06 ` Ville Syrjälä
2025-12-16 10:22 ` Hogander, Jouni
2025-12-10 13:41 ` Hogander, Jouni
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