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From: Imre Deak <imre.deak@intel.com>
To: Jouni Hogander <jouni.hogander@intel.com>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 50/50] drm/i915/dp: Use intel_dp_dsc_get_slice_config()
Date: Fri, 12 Dec 2025 20:03:20 +0200	[thread overview]
Message-ID: <aTxY6DfEJ-9_RCeI@ideak-desk> (raw)
In-Reply-To: <aTqbrglYFDv7krbV@ideak-desk>

On Thu, Dec 11, 2025 at 12:23:42PM +0200, Imre Deak wrote:
> On Thu, Dec 11, 2025 at 08:59:25AM +0200, Jouni Hogander wrote:
> > On Thu, 2025-11-27 at 19:50 +0200, Imre Deak wrote:
> > > Simplify things by computing the detailed slice configuration using
> > > intel_dp_dsc_get_slice_config(), instead of open-coding the same.
> > > 
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 35 +++--------------------
> > > --
> > >  1 file changed, 3 insertions(+), 32 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 003f4b18c1175..d41c75c6f7831 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2387,7 +2387,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > >  		&pipe_config->hw.adjusted_mode;
> > >  	int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
> > >  	bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
> > > -	int slices_per_line;
> > >  	int ret;
> > >  
> > >  	/*
> > > @@ -2413,39 +2412,11 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > >  		}
> > >  	}
> > >  
> > > -	/* Calculate Slice count */
> > > -	slices_per_line = intel_dp_dsc_get_slice_count(connector,
> > > -						       adjusted_mode->crtc_clock,
> > > -						       adjusted_mode->crtc_hdisplay,
> > > -						       num_joined_pipes);
> > > -	if (!slices_per_line)
> > > +	if (!intel_dp_dsc_get_slice_config(connector, adjusted_mode->crtc_clock,
> > > +					   adjusted_mode->crtc_hdisplay, num_joined_pipes,
> > > +					   &pipe_config->dsc.slice_config))
> > >  		return -EINVAL;
> > >  
> > > -	/*
> > > -	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
> > > -	 * is greater than the maximum Cdclock and if slice count is even
> > > -	 * then we need to use 2 VDSC instances.
> > > -	 * In case of Ultrajoiner along with 12 slices we need to use 3
> > > -	 * VDSC instances.
> > > -	 */
> > 
> > I'll guess you have considered this comment being useless?
> 
> A stricter condition between pixel clock (mode clock) vs. CD clock is
> described already in intel_dp_dsc_min_slice_count(). I can further
> clarify the comment in that function, mentioning also the above VDSC
> engine 1 ppc limit as a reason for the condition there.

After talking with Ville, the 1 pixel per clock vs. CDCLK limitation is
actually explained and accounted for (increasing the CDCLK if necessary)
in intel_vdsc_min_cdclk(). Another thing to do would be to increase the
number slices and with that the number of VDSC engine streams, so that a
lower CDCLK can be used. This optimization isn't attempted atm, but I'll
add a TODO comment to intel_dp_dsc_get_slice_config() to consider doing
that in the future.

> The 12 slices-per-line / 3 VDSC streams-per-pipe logic is already
> described in intel_dsc_get_slice_config().
> 
> > Anyways, patch looks ok:
> > 
> > Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> > 
> > > -	pipe_config->dsc.slice_config.pipes_per_line = num_joined_pipes;
> > > -
> > > -	if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
> > > -	    slices_per_line == 12)
> > > -		pipe_config->dsc.slice_config.streams_per_pipe = 3;
> > > -	else if (pipe_config->joiner_pipes || slices_per_line > 1)
> > > -		pipe_config->dsc.slice_config.streams_per_pipe = 2;
> > > -	else
> > > -		pipe_config->dsc.slice_config.streams_per_pipe = 1;
> > > -
> > > -	pipe_config->dsc.slice_config.slices_per_stream =
> > > -		slices_per_line /
> > > -		pipe_config->dsc.slice_config.pipes_per_line /
> > > -		pipe_config->dsc.slice_config.streams_per_pipe;
> > > -
> > > -	drm_WARN_ON(display->drm,
> > > -		    intel_dsc_line_slice_count(&pipe_config->dsc.slice_config) != slices_per_line);
> > > -
> > >  	ret = intel_dp_dsc_compute_params(connector, pipe_config);
> > >  	if (ret < 0) {
> > >  		drm_dbg_kms(display->drm,
> > 

  reply	other threads:[~2025-12-12 18:03 UTC|newest]

Thread overview: 137+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-27 17:49 [PATCH 00/50] drm/i915/dp: Clean up link BW/DSC slice config computation Imre Deak
2025-11-27 17:49 ` [PATCH 01/50] drm/dp: Parse all DSC slice count caps for eDP 1.5 Imre Deak
2025-12-08 11:24   ` Luca Coelho
2025-12-08 12:36     ` Imre Deak
2025-11-27 17:49 ` [PATCH 02/50] drm/dp: Add drm_dp_dsc_sink_slice_count_mask() Imre Deak
2025-12-09  8:48   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 03/50] drm/i915/dp: Fix DSC sink's slice count capability check Imre Deak
2025-12-09  8:51   ` Luca Coelho
2025-12-09  9:53     ` Imre Deak
2025-12-09 11:14       ` Luca Coelho
2025-11-27 17:49 ` [PATCH 04/50] drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp() Imre Deak
2025-12-09  9:10   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 05/50] drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation Imre Deak
2025-12-09 12:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 06/50] drm/i915/dp: Factor out intel_dp_link_bw_overhead() Imre Deak
2025-12-09 12:52   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 07/50] drm/i915/dp: Fix BW check in is_bw_sufficient_for_dsc_config() Imre Deak
2025-12-09 12:53   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 08/50] drm/i915/dp: Use the effective data rate for DP BW calculation Imre Deak
2025-12-10 12:48   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 09/50] drm/i915/dp: Use the effective data rate for DP compressed " Imre Deak
2025-12-10 12:50   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 10/50] drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW Imre Deak
2025-12-10 13:08   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 11/50] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST " Imre Deak
2025-12-10 13:39   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 12/50] drm/i915/dp: Account with pipe joiner max compressed BPP limit for DP-MST and eDP Imre Deak
2025-12-10 14:29   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 13/50] drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config() Imre Deak
2025-12-10 14:31   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 14/50] drm/i915/dp: Factor out align_max_sink_dsc_input_bpp() Imre Deak
2025-12-12 15:41   ` Govindapillai, Vinod
2025-12-15  7:46   ` Luca Coelho
2025-12-15 11:53     ` Imre Deak
2025-12-15 12:02       ` Luca Coelho
2025-12-15 12:33         ` Imre Deak
2025-11-27 17:49 ` [PATCH 15/50] drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16() Imre Deak
2025-12-12 15:46   ` Govindapillai, Vinod
2025-12-15  7:49   ` Luca Coelho
2025-12-15 12:00     ` Imre Deak
2025-12-15 12:08       ` Luca Coelho
2025-12-15 12:24         ` Imre Deak
2025-11-27 17:49 ` [PATCH 16/50] drm/i915/dp: Fail state computation for invalid min/max link BPP values Imre Deak
2025-12-12 15:48   ` Govindapillai, Vinod
2025-12-15  7:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 17/50] drm/i915/dp: Fail state computation for invalid max throughput BPP value Imre Deak
2025-12-12 15:51   ` Govindapillai, Vinod
2025-12-15  7:51   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 18/50] drm/i915/dp: Fail state computation for invalid max sink compressed " Imre Deak
2025-12-12 15:52   ` Govindapillai, Vinod
2025-12-15  7:52   ` Luca Coelho
2025-11-27 17:49 ` [PATCH 19/50] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-11  8:29   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 20/50] drm/i915/dp: Align min/max DSC input BPPs to sink caps Imre Deak
2025-12-11  8:51   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 21/50] drm/i915/dp: Align min/max compressed BPPs when calculating BPP limits Imre Deak
2025-12-12  9:17   ` Govindapillai, Vinod
2025-12-12 11:09     ` Imre Deak
2025-11-27 17:49 ` [PATCH 22/50] drm/i915/dp: Drop intel_dp parameter from intel_dp_compute_config_link_bpp_limits() Imre Deak
2025-12-12  9:23   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 23/50] drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp() Imre Deak
2025-12-12  9:27   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 24/50] drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16() Imre Deak
2025-12-12  9:31   ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 25/50] drm/i915/dp: Factor out compute_min_compressed_bpp_x16() Imre Deak
2025-12-12  9:39   ` Govindapillai, Vinod
2025-12-12 11:01     ` Imre Deak
2025-12-12 11:41       ` Govindapillai, Vinod
2025-11-27 17:49 ` [PATCH 26/50] drm/i915/dp: Factor out compute_max_compressed_bpp_x16() Imre Deak
2025-12-12  9:50   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 27/50] drm/i915/dp: Add intel_dp_mode_valid_with_dsc() Imre Deak
2025-12-12 11:43   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 28/50] drm/i915/dp: Unify detect and compute time DSC mode BW validation Imre Deak
2025-12-12 14:29   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 29/50] drm/i915/dp: Use helpers to align min/max compressed BPPs Imre Deak
2025-12-12 14:34   ` Govindapillai, Vinod
2025-12-12 14:39   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 30/50] drm/i915/dp: Simplify computing DSC BPPs for eDP Imre Deak
2025-12-12 14:45   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 31/50] drm/i915/dp: Simplify computing DSC BPPs for DP-SST Imre Deak
2025-12-12 14:59   ` Govindapillai, Vinod
2025-12-12 18:41     ` Imre Deak
2025-11-27 17:50 ` [PATCH 32/50] drm/i915/dp: Simplify computing forced DSC BPP " Imre Deak
2025-12-12 15:21   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 33/50] drm/i915/dp: Unify computing compressed BPP for DP-SST and eDP Imre Deak
2025-12-12 15:38   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 34/50] drm/i915/dp: Simplify eDP vs. DP compressed BPP computation Imre Deak
2025-12-12 15:39   ` Govindapillai, Vinod
2025-11-27 17:50 ` [PATCH 35/50] drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MST Imre Deak
2025-12-08 13:08   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 36/50] drm/i915/dsc: Track the detaild DSC slice configuration Imre Deak
2025-12-09  8:24   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 37/50] drm/i915/dsc: Track the DSC stream count in the DSC slice config state Imre Deak
2025-12-09  8:28   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 38/50] drm/i915/dsi: Move initialization of DSI DSC streams-per-pipe to fill_dsc() Imre Deak
2025-12-09  8:47   ` Hogander, Jouni
2025-12-09 10:38     ` Imre Deak
2025-12-09 11:37       ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 39/50] drm/i915/dsi: Track the detailed DSC slice configuration Imre Deak
2025-12-09 12:43   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 40/50] drm/i915/dp: " Imre Deak
2025-12-09 14:06   ` Hogander, Jouni
2025-12-09 14:30     ` Imre Deak
2025-12-09 17:50       ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 41/50] drm/i915/dsc: Switch to using intel_dsc_line_slice_count() Imre Deak
2025-12-09 17:14   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 42/50] drm/i915/dp: Factor out intel_dp_dsc_min_slice_count() Imre Deak
2025-12-09 17:26   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 43/50] drm/i915/dp: Use int for DSC slice count variables Imre Deak
2025-12-09 17:30   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 44/50] drm/i915/dp: Rename test_slice_count to slices_per_line Imre Deak
2025-12-09 17:34   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 45/50] drm/i915/dp: Simplify the DSC slice config loop's slices-per-pipe iteration Imre Deak
2025-12-10 12:38   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 46/50] drm/i915/dsc: Add intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:06   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 47/50] drm/i915/dsi: Use intel_dsc_get_slice_config() Imre Deak
2025-12-10 14:44   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 48/50] drm/i915/dp: Unify DP and eDP slice count computation Imre Deak
2025-12-11  6:48   ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 49/50] drm/i915/dp: Add intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11  6:55   ` Hogander, Jouni
2025-12-11  9:52     ` Imre Deak
2025-12-12 18:17   ` [PATCH v2 " Imre Deak
2025-12-15  6:06     ` Hogander, Jouni
2025-11-27 17:50 ` [PATCH 50/50] drm/i915/dp: Use intel_dp_dsc_get_slice_config() Imre Deak
2025-12-11  6:59   ` Hogander, Jouni
2025-12-11 10:23     ` Imre Deak
2025-12-12 18:03       ` Imre Deak [this message]
2025-12-12 18:17   ` [PATCH v2 " Imre Deak
2025-11-28 16:20 ` [CI 09/50] drm/i915/dp: Use the effective data rate for DP compressed BW calculation Imre Deak
2025-12-12 13:23   ` Govindapillai, Vinod
2025-11-28 18:48 ` ✗ i915.CI.BAT: failure for drm/i915/dp: Clean up link BW/DSC slice config computation Patchwork
2025-11-28 20:49   ` Imre Deak
2025-12-01  9:46 ` ✗ i915.CI.Full: " Patchwork
2025-12-12 20:01 ` ✓ i915.CI.BAT: success for drm/i915/dp: Clean up link BW/DSC slice config computation (rev3) Patchwork
2025-12-13  4:00 ` ✓ i915.CI.Full: " Patchwork

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