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d="scan'208";a="210004324" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.245.148]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2026 08:34:37 -0800 Date: Tue, 3 Feb 2026 18:34:34 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Uma Shankar Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, jani.nikula@intel.com Subject: Re: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Message-ID: References: <20260129211358.1240283-1-uma.shankar@intel.com> <20260129211358.1240283-18-uma.shankar@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260129211358.1240283-18-uma.shankar@intel.com> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote: > Make intel_display_power_well.c free from including i915_reg.h. > > v2: Include specific pcode header, drop common header (Jani) > > Signed-off-by: Uma Shankar > --- > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +- > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 3 --- > 3 files changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 6f9bc6f9615e..f98de1baa63d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -6,8 +6,8 @@ > #include > > #include > +#include > > -#include "i915_reg.h" > #include "intel_backlight_regs.h" > #include "intel_combo_phy.h" > #include "intel_combo_phy_regs.h" > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 4a9b7560ce8c..758749c5c322 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -359,6 +359,8 @@ > #define FW_CSPWRDWNEN (1 << 15) > > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) > +/* Disable display A/B trickle feed */ > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) > > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) > #define CDCLK_FREQ_SHIFT 4 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9cd7fce09ebe..e4fc61dcd384 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -428,9 +428,6 @@ > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) > > -/* Disable display A/B trickle feed */ > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) > - Instead of confusing where this bit lives on most platforms (MI_ARB_STATE) we should probably just add a separate defition for the VLV bit (since it has a separate register offset definition as well). > /* Set display plane priority */ > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ > -- > 2.50.1 -- Ville Syrjälä Intel