From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
arun.r.murthy@intel.com
Subject: Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
Date: Tue, 10 Mar 2026 11:08:21 +0200 [thread overview]
Message-ID: <aa_fhRxsFcftI2Nv@intel.com> (raw)
In-Reply-To: <aarCQYHTCCEKtB2R@intel.com>
On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
> > Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
> > value used when programming the double‑buffering point and transmission
> > line for VRR packets.
> > Also improve the documentation: the AS SDP transmission line corresponds
> > to the T1 position, which maps to the start of the Vsync pulse.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> > 3 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 86390553800d..9204a813639a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> > return true;
> > }
> >
> > +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> > +{
> > + /*
> > + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
> > + * that corresponds to the start of the Vsync pulse.
> > + */
> > + return crtc_state->vrr.vsync_start;
> > +}
>
> Other parts of the code (eg. ALPM) still just directly use the
> adjusted_mode timings to calculate the same stuff. So this doesn't
> really seem to help us.
>
> Feels like all of our abstractions around this SDP transmission line
> stuff are way too low level, and thus the same information is
> calculated in different ways in different parts of the code. There
> should be a single place that defines the transmission line(s),
> and everyone should just consult that stuff (regardless of whether
> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
> the new stuff).
I think instead of tracking the low level stagger values directly, what
we want to track is just the transmission line itself for each type of
SDP. That seems like a form that is easier to use elsewhere in the code.
And to accommodate VRR I suppose we should use the "transmission line
is specified relative to the end of vblank/vtotal" convention for all
of these.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2026-03-10 9:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 1/5] drm/i915/nvl: Add register definitions for common " Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state Ankit Nautiyal
2026-03-06 11:55 ` Ville Syrjälä
2026-03-10 4:54 ` Nautiyal, Ankit K
2026-03-05 4:01 ` [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Ankit Nautiyal
2026-03-06 12:02 ` Ville Syrjälä
2026-03-10 4:57 ` Nautiyal, Ankit K
2026-03-10 9:08 ` Ville Syrjälä [this message]
2026-03-11 11:54 ` Nautiyal, Ankit K
2026-03-11 12:04 ` Ville Syrjälä
2026-03-11 12:10 ` Nautiyal, Ankit K
2026-03-05 4:01 ` [PATCH 4/5] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 5/5] drm/i915/dp: Enable Common " Ankit Nautiyal
2026-03-06 11:56 ` Ville Syrjälä
2026-03-10 5:01 ` Nautiyal, Ankit K
2026-03-05 5:40 ` ✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line Patchwork
2026-03-06 4:34 ` ✗ i915.CI.Full: failure " Patchwork
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