From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FF99F3C27D for ; Tue, 10 Mar 2026 09:08:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3033610E6A6; Tue, 10 Mar 2026 09:08:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D6CvyPzD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC2E910E6A4; Tue, 10 Mar 2026 09:08:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773133707; x=1804669707; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=g8Njy6UmMyZ696/0mFzf/F5nJk1m8XSwedpwfhul80U=; b=D6CvyPzDnWUIQtnQ++peGHxPPgoUq2tboYpxyM1UGnMXZyF5wV3oW0ID vt5wGalNP/9avURE408z+a8um1P42F/CUmNWI0LWovhZeLnF7gcnQe6ms bIkjse+qzw01SSR+7Mcb70b6zI5xKt+RFkw6tLfZIep9kdNELUtEzDoQ6 09X458US1L18Q7HPbHKtRxaJopypdU3LP2bS2OF+XnLHVJgGfm3pROBmu u4Px69la56TfIyShvI4NToH84PAeRsAvoNWyfbpTB0w2Ri6mCgEYkvqo2 x89P2fFLu46McHsMW3DWw7ixUpIdER+8ThUEVC2+ndmu+P7Y4d4YGRGFw w==; X-CSE-ConnectionGUID: kg8FUse0R4OIkd/hpyXLew== X-CSE-MsgGUID: gwLN3D1UQ0SBwlnDGmD7lw== X-IronPort-AV: E=McAfee;i="6800,10657,11724"; a="73874058" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="73874058" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 02:08:26 -0700 X-CSE-ConnectionGUID: GlITQYpqR2+4GSr4ooqtJw== X-CSE-MsgGUID: YGmLrajuRFmJ2R1+ouMJJQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="257960280" Received: from zzombora-mobl1 (HELO localhost) ([10.245.244.33]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 02:08:25 -0700 Date: Tue, 10 Mar 2026 11:08:21 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, arun.r.murthy@intel.com Subject: Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Message-ID: References: <20260305040118.2576312-1-ankit.k.nautiyal@intel.com> <20260305040118.2576312-4-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote: > On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote: > > Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL > > value used when programming the double‑buffering point and transmission > > line for VRR packets. > > Also improve the documentation: the AS SDP transmission line corresponds > > to the T1 position, which maps to the start of the Vsync pulse. > > > > Signed-off-by: Ankit Nautiyal > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++ > > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++-- > > 3 files changed, 12 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 86390553800d..9204a813639a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector, > > return true; > > } > > > > +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state) > > +{ > > + /* > > + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position > > + * that corresponds to the start of the Vsync pulse. > > + */ > > + return crtc_state->vrr.vsync_start; > > +} > > Other parts of the code (eg. ALPM) still just directly use the > adjusted_mode timings to calculate the same stuff. So this doesn't > really seem to help us. > > Feels like all of our abstractions around this SDP transmission line > stuff are way too low level, and thus the same information is > calculated in different ways in different parts of the code. There > should be a single place that defines the transmission line(s), > and everyone should just consult that stuff (regardless of whether > the platform uses implicit transmission lines, EMP_AS_SDP_TL, or > the new stuff). I think instead of tracking the low level stagger values directly, what we want to track is just the transmission line itself for each type of SDP. That seems like a form that is easier to use elsewhere in the code. And to accommodate VRR I suppose we should use the "transmission line is specified relative to the end of vblank/vtotal" convention for all of these. -- Ville Syrjälä Intel