* [PATCH 0/5] Add support for Common SDP Transmission Line
@ 2026-03-05 4:01 Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 1/5] drm/i915/nvl: Add register definitions for common " Ankit Nautiyal
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
Xe3p_lpd introduces new register bits to program a common SDP
Transmission line that will be used by the Hardware to position the
SDPs. Along with this, another new register is also added to stagger
the different SDPs.
This series adds support for programming the Common SDP Transmission Line
(CMN_SDP_TL) and its stagger control registers.
Ankit Nautiyal (4):
drm/i915/dp: Add fields to store CMN_SDP_TL register state in
crtc_state
drm/i915/dp: Add helper for AS SDP TL and fix documentation
drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
line
drm/i915/dp: Enable Common SDP Transmission line
Ankit Nautiyal (4):
drm/i915/dp: Add fields to store CMN_SDP_TL register state in
crtc_state
drm/i915/dp: Add helper for AS SDP TL and fix documentation
drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
line
drm/i915/dp: Enable Common SDP Transmission line
Arun R Murthy (1):
drm/i915/nvl: Add register definitions for common SDP Transmission
Line
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +
drivers/gpu/drm/i915/display/intel_display.c | 6 +
.../drm/i915/display/intel_display_device.h | 1 +
.../gpu/drm/i915/display/intel_display_regs.h | 19 +++
.../drm/i915/display/intel_display_types.h | 9 ++
drivers/gpu/drm/i915/display/intel_dp.c | 123 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 5 +
drivers/gpu/drm/i915/display/intel_vrr.c | 4 +-
8 files changed, 169 insertions(+), 2 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] drm/i915/nvl: Add register definitions for common SDP Transmission Line
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
@ 2026-03-05 4:01 ` Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state Ankit Nautiyal
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
From: Arun R Murthy <arun.r.murthy@intel.com>
Add registers definitions for common SDP transmission line CMN_SDP_TL
and CMN_SDP_TL_STGR_CTL.
Bspec: 74384
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 49e2a9e3ee0e..5cfe4114b7dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2124,6 +2124,25 @@
_VLV_VIDEO_DIP_DATA_B, \
_CHV_VIDEO_DIP_DATA_C)
+/* COMMON SDP TRANSMISSION LINE */
+#define _CMN_SDP_TL_A 0x6020c
+#define CMN_SDP_TL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A)
+#define TRANSMISSION_LINE_ENABLE REG_BIT(31)
+#define BASE_TRANSMISSION_LINE_MASK REG_GENMASK(12, 0)
+#define BASE_TRANSMISSION_LINE(x) REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x)
+
+#define _CMN_SDP_TL_STGR_CTL_A 0x60214
+#define CMN_SDP_TL_STGR_CTL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_STGR_CTL_A)
+#define VSC_EXT_STAGGER_MASK REG_GENMASK(11, 8)
+#define VSC_EXT_STAGGER(x) REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x)
+#define VSC_EXT_STAGGER_DEFAULT 0x2
+#define PPS_STAGGER_MASK REG_GENMASK(7, 4)
+#define PPS_STAGGER(x) REG_FIELD_PREP(PPS_STAGGER_MASK, x)
+#define PPS_STAGGER_DEFAULT 0x1
+#define GMP_STAGGER_MASK REG_GENMASK(3, 0)
+#define GMP_STAGGER(x) REG_FIELD_PREP(GMP_STAGGER_MASK, x)
+#define GMP_STAGGER_DEFAULT 0x0
+
#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
--
2.45.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 1/5] drm/i915/nvl: Add register definitions for common " Ankit Nautiyal
@ 2026-03-05 4:01 ` Ankit Nautiyal
2026-03-06 11:55 ` Ville Syrjälä
2026-03-05 4:01 ` [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Ankit Nautiyal
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
Xe3p_lpd introduces new register bits to program a common SDP
Transmission Line, which the hardware uses to position various
SDPs. It also adds a separate control register to stagger the different
SDPs (VSC EXT, PPS, GMP).
Add fields in struct intel_crtc_state to store the state of these new
registers. Add register readback and pipe config comparison for the new
fields.
Also add a display version check (HAS_CMN_SDP_TL) to gate access to the
new registers.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 9 ++++++++
drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
6 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 94ae583e907f..bdbd89600bee 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4217,6 +4217,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+ intel_dp_cmn_sdp_transmission_line_get_config(pipe_config);
intel_audio_codec_get_config(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27354585ba92..76eea9d23766 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5461,6 +5461,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
+ PIPE_CONF_CHECK_BOOL(cmn_sdp_tl.enable);
+ PIPE_CONF_CHECK_I(cmn_sdp_tl.transmission_line);
+ PIPE_CONF_CHECK_I(cmn_sdp_tl.vsc_ext_stagger);
+ PIPE_CONF_CHECK_I(cmn_sdp_tl.pps_stagger);
+ PIPE_CONF_CHECK_I(cmn_sdp_tl.gmp_stagger);
+
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
PIPE_CONF_CHECK_X(joiner_pipes);
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index e84c190dcc4f..43e259761048 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -154,6 +154,7 @@ struct intel_display_platforms {
#define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20)
#define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
+#define HAS_CMN_SDP_TL(__display) (DISPLAY_VER(__display) >= 35)
#define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
#define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
#define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8a2b37c7bccf..474d6e2ae34b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1298,6 +1298,15 @@ struct intel_crtc_state {
struct drm_dp_as_sdp as_sdp;
} infoframes;
+ struct {
+ /* Common SDP Transmission line */
+ bool enable;
+ int transmission_line;
+ int vsc_ext_stagger;
+ int pps_stagger;
+ int gmp_stagger;
+ } cmn_sdp_tl;
+
u8 eld[MAX_ELD_BYTES];
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 025e906b63a9..86390553800d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7287,3 +7287,24 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
return true;
}
+
+void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val;
+
+ if (!HAS_CMN_SDP_TL(display))
+ return;
+
+ val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
+
+ crtc_state->cmn_sdp_tl.enable = val & TRANSMISSION_LINE_ENABLE;
+ crtc_state->cmn_sdp_tl.transmission_line = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
+
+ val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
+
+ crtc_state->cmn_sdp_tl.vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
+ crtc_state->cmn_sdp_tl.pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
+ crtc_state->cmn_sdp_tl.gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b0bbd5981f57..24df234a43d3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -237,4 +237,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
+void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_DP_H__ */
--
2.45.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 1/5] drm/i915/nvl: Add register definitions for common " Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state Ankit Nautiyal
@ 2026-03-05 4:01 ` Ankit Nautiyal
2026-03-06 12:02 ` Ville Syrjälä
2026-03-05 4:01 ` [PATCH 4/5] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line Ankit Nautiyal
` (3 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
value used when programming the double‑buffering point and transmission
line for VRR packets.
Also improve the documentation: the AS SDP transmission line corresponds
to the T1 position, which maps to the start of the Vsync pulse.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 86390553800d..9204a813639a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
return true;
}
+int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+ /*
+ * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
+ * that corresponds to the start of the Vsync pulse.
+ */
+ return crtc_state->vrr.vsync_start;
+}
+
void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 24df234a43d3..abb2fcdea352 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -237,6 +237,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
+int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00ca76dbdd6c..2b4e4e55d008 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -642,12 +642,12 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
* double buffering point and transmission line for VRR packets for
* HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
* Since currently we support VRR only for DP/eDP, so this is programmed
- * to for Adaptive Sync SDP to Vsync start.
+ * only for Adaptive Sync SDP.
*/
if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
intel_de_write(display,
EMP_AS_SDP_TL(display, cpu_transcoder),
- EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+ EMP_AS_SDP_DB_TL(intel_dp_emp_as_sdp_tl(crtc_state)));
}
void
--
2.45.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
` (2 preceding siblings ...)
2026-03-05 4:01 ` [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Ankit Nautiyal
@ 2026-03-05 4:01 ` Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 5/5] drm/i915/dp: Enable Common " Ankit Nautiyal
` (2 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
Introduce helpers to program or disable CMN_SDP_TL and stagger registers
using the state stored in crtc_state.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 29 +++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9204a813639a..59a8fa5e5ba9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7317,3 +7317,32 @@ void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc
crtc_state->cmn_sdp_tl.pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
crtc_state->cmn_sdp_tl.gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
}
+
+void intel_dp_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (!crtc_state->cmn_sdp_tl.enable)
+ return;
+
+ intel_de_write(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder),
+ GMP_STAGGER(crtc_state->cmn_sdp_tl.gmp_stagger) |
+ PPS_STAGGER(crtc_state->cmn_sdp_tl.pps_stagger) |
+ VSC_EXT_STAGGER(crtc_state->cmn_sdp_tl.vsc_ext_stagger));
+
+ intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder),
+ TRANSMISSION_LINE_ENABLE |
+ BASE_TRANSMISSION_LINE(crtc_state->cmn_sdp_tl.transmission_line));
+}
+
+void intel_dp_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state)
+{
+ struct intel_display *display = to_intel_display(old_crtc_state);
+ enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+ if (!old_crtc_state->cmn_sdp_tl.enable)
+ return;
+
+ intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index abb2fcdea352..ace7d142182f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -239,5 +239,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+void intel_dp_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state);
+void intel_dp_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state);
#endif /* __INTEL_DP_H__ */
--
2.45.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] drm/i915/dp: Enable Common SDP Transmission line
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
` (3 preceding siblings ...)
2026-03-05 4:01 ` [PATCH 4/5] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line Ankit Nautiyal
@ 2026-03-05 4:01 ` Ankit Nautiyal
2026-03-06 11:56 ` Ville Syrjälä
2026-03-05 5:40 ` ✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line Patchwork
2026-03-06 4:34 ` ✗ i915.CI.Full: failure " Patchwork
6 siblings, 1 reply; 18+ messages in thread
From: Ankit Nautiyal @ 2026-03-05 4:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, arun.r.murthy, Ankit Nautiyal
Enable the Common SDP Transmission line for the SDP packets.
We get the clear picture about the SDPs and guardband only in
intel_dp_sdp_compute_config_late() therefore we must configure the
crtc_state members related to Common SDP Transmission line at this
point.
Currently, the stagger values are set as per the default policy of the
Hardware. This can be optimized later if we come up with a specific
driver policy to sequence the SDPs better.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 64 ++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bdbd89600bee..e1e95f18f0ed 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2726,6 +2726,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 6.o Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
+ intel_dp_cmn_sdp_transmission_line_enable(crtc_state);
+
/* 7.a 128b/132b SST. */
if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
/* VCPID 1, start slot 0 for 128b/132b, tu slots */
@@ -3113,6 +3115,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
DP_TP_CTL_ENABLE, 0);
}
+ intel_dp_cmn_sdp_transmission_line_disable(crtc_state);
intel_ddi_disable_fec(encoder, crtc_state);
if (DISPLAY_VER(display) < 14)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 59a8fa5e5ba9..87d73d0239bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7189,6 +7189,68 @@ void intel_dp_mst_resume(struct intel_display *display)
}
}
+static
+void intel_dp_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ bool as_sdp, gmp_sdp, pps_sdp, vsc_sdp, vsc_ext_sdp;
+
+ if (!HAS_CMN_SDP_TL(display))
+ return;
+
+ as_sdp = crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+
+ gmp_sdp = crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+
+ pps_sdp = crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_PPS);
+
+ vsc_sdp = crtc_state->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+ vsc_ext_sdp = crtc_state->infoframes.enable &
+ (intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_VESA) |
+ intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_CEA));
+
+ if (!gmp_sdp && !pps_sdp && !vsc_sdp && !vsc_ext_sdp)
+ return;
+
+ crtc_state->cmn_sdp_tl.enable = true;
+
+ /*
+ * When AS SDP is enabled :
+ * - The common SDP Transmission Line matches the EMP SDP Transmission Line.
+ *
+ * When AS SDP is disabled:
+ * - Bspec mentions the positions as lines of delayed vblank.
+ * - Guardband = 1st line of delayed vblank
+ * - Common SDP Transmission line is set to 2nd line of delayed vblank.
+ */
+
+ if (as_sdp)
+ crtc_state->cmn_sdp_tl.transmission_line =
+ intel_dp_emp_as_sdp_tl(crtc_state);
+ else
+ crtc_state->cmn_sdp_tl.transmission_line =
+ crtc_state->vrr.guardband - 1;
+
+ /*
+ * Currently we are programming the default stagger values, but these
+ * can be optimized if required, based on number of SDPs enabled.
+ *
+ * Default values of the Transmission lines for SDPs other than AS SDP:
+ * VSC : CMN SDP Transmission line
+ * GMP : CMN SDP Transmission line
+ * PPS : CMN SDP Transmission line + 1
+ * VSC_EXT: CMN SDP Transmission line + 2
+ */
+ crtc_state->cmn_sdp_tl.gmp_stagger = GMP_STAGGER_DEFAULT;
+ crtc_state->cmn_sdp_tl.pps_stagger = PPS_STAGGER_DEFAULT;
+ crtc_state->cmn_sdp_tl.vsc_ext_stagger = VSC_EXT_STAGGER_DEFAULT;
+}
+
static
int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
{
@@ -7202,6 +7264,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
return -EINVAL;
}
+ intel_dp_cmn_sdp_tl_compute_config_late(crtc_state);
+
return 0;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
` (4 preceding siblings ...)
2026-03-05 4:01 ` [PATCH 5/5] drm/i915/dp: Enable Common " Ankit Nautiyal
@ 2026-03-05 5:40 ` Patchwork
2026-03-06 4:34 ` ✗ i915.CI.Full: failure " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-05 5:40 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3593 bytes --]
== Series Details ==
Series: Add support for Common SDP Transmission Line
URL : https://patchwork.freedesktop.org/series/162622/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_18094 -> Patchwork_162622v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/index.html
Participating hosts (41 -> 40)
------------------------------
Missing (1): bat-dg2-13
Known issues
------------
Here are the changes found in Patchwork_162622v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@basic@lmem0:
- bat-atsm-1: [PASS][1] -> [ABORT][2] ([i915#15759]) +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/bat-atsm-1/igt@gem_exec_create@basic@lmem0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/bat-atsm-1/igt@gem_exec_create@basic@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-dg2-9: [PASS][3] -> [ABORT][4] ([i915#15759]) +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/bat-dg2-9/igt@gem_lmem_swapping@parallel-random-engines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/bat-dg2-9/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-14: [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/bat-dg2-14/igt@i915_selftest@live@workarounds.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-mtlp-9: [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
- bat-arls-6: [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/bat-arls-6/igt@i915_selftest@live@workarounds.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/bat-arls-6/igt@i915_selftest@live@workarounds.html
* igt@kms_hdmi_inject@inject-audio:
- fi-tgl-1115g4: [FAIL][11] ([i915#14867]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#14867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14867
[i915#15759]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15759
Build changes
-------------
* Linux: CI_DRM_18094 -> Patchwork_162622v1
CI-20190529: 20190529
CI_DRM_18094: d7689f077339984fa4c23c972f591ee318b3c56f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_162622v1: d7689f077339984fa4c23c972f591ee318b3c56f @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/index.html
[-- Attachment #2: Type: text/html, Size: 4537 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ i915.CI.Full: failure for Add support for Common SDP Transmission Line
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
` (5 preceding siblings ...)
2026-03-05 5:40 ` ✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line Patchwork
@ 2026-03-06 4:34 ` Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2026-03-06 4:34 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 115689 bytes --]
== Series Details ==
Series: Add support for Common SDP Transmission Line
URL : https://patchwork.freedesktop.org/series/162622/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_18094_full -> Patchwork_162622v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_162622v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_162622v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_162622v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][1] -> [CRASH][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-3/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@runner@aborted:
- shard-mtlp: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-4/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_162622v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-tglu-1: NOTRUN -> [SKIP][4] ([i915#11078])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu: NOTRUN -> [SKIP][5] ([i915#11078])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@device_reset@unbind-cold-reset-rebind.html
* igt@gem_basic@multigpu-create-close:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#7697])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu-1: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-1: NOTRUN -> [SKIP][8] ([i915#9323])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@gem_ccs@suspend-resume.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [PASS][10] -> [INCOMPLETE][11] ([i915#13356])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-4/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-1: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8562])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_isolation@nonpriv:
- shard-dg1: [PASS][15] -> [ABORT][16] ([i915#15759]) +8 other tests abort
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-12/igt@gem_ctx_isolation@nonpriv.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-19/igt@gem_ctx_isolation@nonpriv.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-1: NOTRUN -> [SKIP][18] ([i915#280])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@parallel:
- shard-tglu: NOTRUN -> [SKIP][19] ([i915#4525]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-tglu-1: NOTRUN -> [SKIP][20] ([i915#4525])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#4525])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][22] ([i915#3281]) +15 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#3281]) +3 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#7276])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s3:
- shard-glk: NOTRUN -> [INCOMPLETE][25] ([i915#13196] / [i915#13356]) +1 other test incomplete
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk9/igt@gem_exec_suspend@basic-s3.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#4613]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu-1: NOTRUN -> [SKIP][27] ([i915#4613]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg2: [PASS][28] -> [FAIL][29] ([i915#15734])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-1/igt@gem_lmem_swapping@smem-oom.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-3/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4077]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-5/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@gem_mmap_wc@write-wc-read-gtt:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4083]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@gem_mmap_wc@write-wc-read-gtt.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#3282]) +3 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pxp@display-protected-crc:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#4270])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#4270])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3282]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#5190] / [i915#8428]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#8411])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4079])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@gem_set_tiling_vs_gtt.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#3297]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglu-1: NOTRUN -> [SKIP][40] ([i915#3297] / [i915#3323])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@relocations:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#3281] / [i915#3297])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@gem_userptr_blits@relocations.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglu-1: NOTRUN -> [SKIP][42] ([i915#3297]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@basic-offset:
- shard-dg2: NOTRUN -> [SKIP][43] +6 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglu: NOTRUN -> [SKIP][44] ([i915#2527] / [i915#2856])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-large:
- shard-tglu-1: NOTRUN -> [SKIP][45] ([i915#2527] / [i915#2856]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@shadow-peek:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#2527]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_drm_fdinfo@virtual-busy-hang:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#14118])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@i915_drm_fdinfo@virtual-busy-hang.html
* igt@i915_fb_tiling@basic-x-tiling:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#13786])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@i915_fb_tiling@basic-x-tiling.html
* igt@i915_module_load@fault-injection@__uc_init:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#15479]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@i915_module_load@fault-injection@__uc_init.html
* igt@i915_module_load@fault-injection@intel_connector_register:
- shard-rkl: NOTRUN -> [ABORT][50] ([i915#15342]) +1 other test abort
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@i915_module_load@fault-injection@intel_connector_register.html
- shard-snb: NOTRUN -> [ABORT][51] ([i915#15342]) +1 other test abort
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-snb7/igt@i915_module_load@fault-injection@intel_connector_register.html
- shard-glk: NOTRUN -> [ABORT][52] ([i915#15342]) +1 other test abort
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk4/igt@i915_module_load@fault-injection@intel_connector_register.html
* igt@i915_module_load@fault-injection@intel_guc_ct_init:
- shard-snb: NOTRUN -> [SKIP][53] +40 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-snb7/igt@i915_module_load@fault-injection@intel_guc_ct_init.html
* igt@i915_module_load@load:
- shard-mtlp: ([PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78]) -> ([PASS][79], [SKIP][80], [PASS][81], [SKIP][82], [PASS][83], [PASS][84], [SKIP][85], [PASS][86], [PASS][87], [PASS][88], [SKIP][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [SKIP][94], [PASS][95], [PASS][96], [SKIP][97]) ([i915#14785])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-1/igt@i915_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-4/igt@i915_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-1/igt@i915_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-1/igt@i915_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-4/igt@i915_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-1/igt@i915_module_load@load.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-4/igt@i915_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-3/igt@i915_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-5/igt@i915_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-5/igt@i915_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-5/igt@i915_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-3/igt@i915_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-6/igt@i915_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-6/igt@i915_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-2/igt@i915_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-6/igt@i915_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-7/igt@i915_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-8/igt@i915_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-2/igt@i915_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-8/igt@i915_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-7/igt@i915_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-8/igt@i915_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-7/igt@i915_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-3/igt@i915_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-8/igt@i915_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-4/igt@i915_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-7/igt@i915_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-7/igt@i915_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-5/igt@i915_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-5/igt@i915_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-3/igt@i915_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-3/igt@i915_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-8/igt@i915_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-2/igt@i915_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-1/igt@i915_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-4/igt@i915_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-6/igt@i915_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-6/igt@i915_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-1/igt@i915_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-4/igt@i915_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-8/igt@i915_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-6/igt@i915_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-1/igt@i915_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-2/igt@i915_module_load@load.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-tglu-1: NOTRUN -> [SKIP][98] ([i915#8399])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#8399])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-rkl: [PASS][100] -> [INCOMPLETE][101] ([i915#13356])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@i915_pm_rpm@system-suspend-execbuf.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#11681] / [i915#6621])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-glk10: NOTRUN -> [INCOMPLETE][103] ([i915#4817])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk10/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@fence-restore-untiled:
- shard-rkl: [PASS][104] -> [ABORT][105] ([i915#15131]) +1 other test abort
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@i915_suspend@fence-restore-untiled.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu-1: NOTRUN -> [SKIP][106] ([i915#12454] / [i915#12712])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#4212])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#1769] / [i915#3555]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-glk11: NOTRUN -> [SKIP][109] ([i915#1769])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][110] -> [FAIL][111] ([i915#15662]) +1 other test fail
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-tglu-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-2/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
- shard-dg2: [PASS][112] -> [FAIL][113] ([i915#5956]) +1 other test fail
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglu-1: NOTRUN -> [SKIP][114] ([i915#5286]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#5286]) +4 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][116] ([i915#5286]) +3 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][117] -> [FAIL][118] ([i915#15733] / [i915#5138])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-addfb:
- shard-dg1: [PASS][119] -> [DMESG-WARN][120] ([i915#4391] / [i915#4423])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_big_fb@linear-addfb.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_big_fb@linear-addfb.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
- shard-tglu: NOTRUN -> [SKIP][121] ([i915#3828])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#3638]) +3 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#5190]) +2 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][124] +24 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#4538] / [i915#5190]) +5 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#14544] / [i915#6095]) +5 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#12313]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#6095]) +155 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-hdmi-a-2:
- shard-glk11: NOTRUN -> [SKIP][129] +156 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#14098] / [i915#14544] / [i915#6095]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][131] ([i915#6095]) +54 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#10307] / [i915#6095]) +75 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#6095]) +51 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#12805])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#6095]) +11 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#14098] / [i915#6095]) +35 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][137] ([i915#6095]) +19 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][138] ([i915#12313])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-tglu: NOTRUN -> [SKIP][139] ([i915#12313]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-4/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@mode-transition:
- shard-tglu: NOTRUN -> [SKIP][141] ([i915#3742])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu-1: NOTRUN -> [SKIP][142] ([i915#3742])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-glk10: NOTRUN -> [SKIP][143] +30 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk10/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-tglu: NOTRUN -> [SKIP][144] ([i915#11151] / [i915#7828]) +3 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-tglu-1: NOTRUN -> [SKIP][145] ([i915#11151] / [i915#7828]) +5 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#11151] / [i915#7828]) +2 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#11151] / [i915#7828]) +7 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: NOTRUN -> [SKIP][148] ([i915#6944] / [i915#7118] / [i915#9424]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@content-type-change:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#6944] / [i915#9424])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#15330] / [i915#3116])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1-suspend-resume:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#15330])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
* igt@kms_content_protection@lic-type-0-hdcp14:
- shard-tglu-1: NOTRUN -> [SKIP][152] ([i915#6944])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_content_protection@lic-type-0-hdcp14.html
* igt@kms_content_protection@lic-type-1:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#6944] / [i915#9424])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#6944])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_content_protection@suspend-resume.html
* igt@kms_content_protection@type1:
- shard-tglu-1: NOTRUN -> [SKIP][155] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent:
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-256x85:
- shard-tglu: NOTRUN -> [FAIL][157] ([i915#13566]) +5 other tests fail
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-256x85.html
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
- shard-rkl: [PASS][158] -> [FAIL][159] ([i915#13566]) +1 other test fail
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-3/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-tglu-1: NOTRUN -> [SKIP][160] ([i915#3555]) +4 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [FAIL][161] ([i915#13566]) +1 other test fail
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#13049]) +2 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][163] ([i915#13049])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#3555])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][165] ([i915#13566]) +2 other tests fail
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-tglu: NOTRUN -> [SKIP][166] ([i915#13049])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#4103]) +1 other test skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#4103] / [i915#4213])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#13046] / [i915#5354]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-tglu-1: NOTRUN -> [SKIP][170] ([i915#4103])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#4103])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-tglu: NOTRUN -> [SKIP][172] ([i915#1769] / [i915#3555] / [i915#3804])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][173] ([i915#3804])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-tglu-1: NOTRUN -> [SKIP][174] ([i915#13749])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dsc@dsc-with-formats:
- shard-tglu: NOTRUN -> [SKIP][175] ([i915#3555] / [i915#3840]) +1 other test skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_dsc@dsc-with-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu-1: NOTRUN -> [SKIP][176] ([i915#3469])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@display-2x:
- shard-tglu-1: NOTRUN -> [SKIP][177] ([i915#1839])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#1839])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@psr1:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#658])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_feature_discovery@psr1.html
* igt@kms_feature_discovery@psr2:
- shard-tglu-1: NOTRUN -> [SKIP][180] ([i915#658])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#9934]) +4 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-5/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#9934]) +7 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-tglu: NOTRUN -> [SKIP][183] ([i915#9934])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#8381])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-glk11: NOTRUN -> [INCOMPLETE][185] ([i915#12745] / [i915#4839]) +1 other test incomplete
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
- shard-glk11: NOTRUN -> [INCOMPLETE][186] ([i915#4839]) +1 other test incomplete
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-tglu: NOTRUN -> [SKIP][187] ([i915#3637] / [i915#9934])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][188] ([i915#3637] / [i915#9934]) +2 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-rkl: [PASS][189] -> [INCOMPLETE][190] ([i915#6113]) +1 other test incomplete
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_flip@flip-vs-suspend.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html
- shard-glk: NOTRUN -> [INCOMPLETE][191] ([i915#12745] / [i915#4839] / [i915#6113])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk3/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
- shard-glk: NOTRUN -> [INCOMPLETE][192] ([i915#12745] / [i915#6113])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk3/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-tglu: NOTRUN -> [SKIP][193] ([i915#15643]) +1 other test skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#15643]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][195] ([i915#15643]) +1 other test skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#15643] / [i915#5190])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_force_connector_basic@force-edid:
- shard-mtlp: [PASS][197] -> [SKIP][198] ([i915#15672])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-4/igt@kms_force_connector_basic@force-edid.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-1/igt@kms_force_connector_basic@force-edid.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-dg1: [PASS][199] -> [DMESG-WARN][200] ([i915#4423]) +1 other test dmesg-warn
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-tglu-1: NOTRUN -> [SKIP][201] +38 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#5354]) +12 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-dg2: [PASS][203] -> [FAIL][204] ([i915#15389] / [i915#6880]) +1 other test fail
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#15104]) +2 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#15102])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#15102] / [i915#3458]) +6 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#1825]) +34 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-tglu-1: NOTRUN -> [SKIP][209] ([i915#15102]) +19 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#15102]) +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#15102] / [i915#3023]) +14 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#15102]) +13 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#8708]) +3 other tests skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#3555] / [i915#8228]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle-suspend:
- shard-rkl: NOTRUN -> [SKIP][215] ([i915#3555] / [i915#8228]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-tglu: NOTRUN -> [SKIP][216] ([i915#15458])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][217] ([i915#15460])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#15458])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#15638] / [i915#15722])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-tglu-1: NOTRUN -> [SKIP][220] ([i915#6301])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-tglu-1: NOTRUN -> [SKIP][221] ([i915#14712])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier:
- shard-rkl: NOTRUN -> [SKIP][222] ([i915#15709])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier.html
* igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
- shard-rkl: NOTRUN -> [SKIP][223] ([i915#15608]) +3 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7:
- shard-tglu-1: NOTRUN -> [SKIP][224] ([i915#15608]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
- shard-tglu: NOTRUN -> [SKIP][225] ([i915#15709]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
- shard-tglu-1: NOTRUN -> [SKIP][226] ([i915#15709]) +2 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb:
- shard-glk11: NOTRUN -> [FAIL][227] ([i915#10647] / [i915#12169])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk11: NOTRUN -> [FAIL][228] ([i915#10647]) +1 other test fail
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-tglu-1: NOTRUN -> [SKIP][229] ([i915#13958])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#13958])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][231] ([i915#14259])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#6953])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d:
- shard-tglu-1: NOTRUN -> [SKIP][233] ([i915#15329]) +4 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#12343])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][235] ([i915#5354])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: NOTRUN -> [FAIL][236] ([i915#15752])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][237] ([i915#3828])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu-1: NOTRUN -> [SKIP][238] ([i915#15073])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg2: [PASS][239] -> [SKIP][240] ([i915#12916])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-6/igt@kms_pm_rpm@i2c.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-4/igt@kms_pm_rpm@i2c.html
- shard-dg1: [PASS][241] -> [SKIP][242] ([i915#12916])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_pm_rpm@i2c.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@package-g7:
- shard-tglu-1: NOTRUN -> [SKIP][243] ([i915#15403])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_pm_rpm@package-g7.html
* igt@kms_pm_rpm@system-suspend-idle:
- shard-dg2: [PASS][244] -> [INCOMPLETE][245] ([i915#14419])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-8/igt@kms_pm_rpm@system-suspend-idle.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-7/igt@kms_pm_rpm@system-suspend-idle.html
* igt@kms_prime@d3hot:
- shard-tglu: NOTRUN -> [SKIP][246] ([i915#6524])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#11520]) +4 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-glk10: NOTRUN -> [SKIP][248] ([i915#11520]) +1 other test skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk10/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-glk: NOTRUN -> [SKIP][249] ([i915#11520]) +2 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
- shard-rkl: NOTRUN -> [SKIP][250] ([i915#11520]) +4 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-glk11: NOTRUN -> [SKIP][251] ([i915#11520]) +4 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk11/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-tglu: NOTRUN -> [SKIP][252] ([i915#11520]) +4 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-tglu-1: NOTRUN -> [SKIP][253] ([i915#11520]) +4 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu-1: NOTRUN -> [SKIP][254] ([i915#9683])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#9683])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-rkl: NOTRUN -> [SKIP][256] ([i915#1072] / [i915#9732]) +16 other tests skip
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-8/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@psr-cursor-plane-onoff:
- shard-tglu: NOTRUN -> [SKIP][257] ([i915#9732]) +10 other tests skip
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@kms_psr@psr-cursor-plane-onoff.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#1072] / [i915#9732]) +9 other tests skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-tglu-1: NOTRUN -> [SKIP][259] ([i915#9732]) +14 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#4235])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-dg2: [PASS][261] -> [ABORT][262] ([i915#15759]) +6 other tests abort
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
- shard-rkl: NOTRUN -> [SKIP][263] ([i915#5289])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
- shard-dg2: NOTRUN -> [ABORT][264] ([i915#15759]) +1 other test abort
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2: NOTRUN -> [SKIP][265] ([i915#12755])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-5/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-rkl: NOTRUN -> [SKIP][266] ([i915#3555]) +2 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_selftest@drm_framebuffer:
- shard-rkl: NOTRUN -> [ABORT][267] ([i915#13179]) +1 other test abort
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@kms_selftest@drm_framebuffer.html
- shard-glk: NOTRUN -> [ABORT][268] ([i915#13179]) +1 other test abort
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk1/igt@kms_selftest@drm_framebuffer.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-tglu: NOTRUN -> [SKIP][269] ([i915#3555])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2: NOTRUN -> [SKIP][270] ([i915#8623])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-glk10: NOTRUN -> [INCOMPLETE][271] ([i915#12276]) +1 other test incomplete
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk10/igt@kms_vblank@ts-continuation-dpms-suspend.html
* igt@kms_vrr@flip-basic-fastset:
- shard-tglu: NOTRUN -> [SKIP][272] ([i915#9906]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-10/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@lobf:
- shard-dg2: NOTRUN -> [SKIP][273] ([i915#11920])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_vrr@lobf.html
* igt@kms_vrr@negative-basic:
- shard-glk: NOTRUN -> [SKIP][274] +108 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk4/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#9906])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-1/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][276] ([i915#2436])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf_pmu@module-unload:
- shard-glk: NOTRUN -> [ABORT][277] ([i915#15778])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-glk9/igt@perf_pmu@module-unload.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][278] ([i915#3291] / [i915#3708])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@fence-write-hang:
- shard-tglu: NOTRUN -> [SKIP][279] +28 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-7/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][280] ([i915#9917])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7:
- shard-tglu-1: NOTRUN -> [FAIL][281] ([i915#12910]) +9 other tests fail
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-7.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- shard-rkl: [ABORT][282] ([i915#15131]) -> [PASS][283] +1 other test pass
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-1/igt@gem_exec_suspend@basic-s0.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@gem_exec_suspend@basic-s0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg1: [FAIL][284] ([i915#15734]) -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-19/igt@gem_lmem_swapping@smem-oom.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [CRASH][286] ([i915#5493]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_suspend@debugfs-reader:
- shard-rkl: [INCOMPLETE][288] ([i915#4817]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@i915_suspend@debugfs-reader.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][290] ([i915#15733] / [i915#5138]) -> [PASS][291]
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_color@invalid-degamma-lut-sizes:
- shard-dg1: [DMESG-WARN][292] ([i915#4423]) -> [PASS][293]
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-19/igt@kms_color@invalid-degamma-lut-sizes.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@kms_color@invalid-degamma-lut-sizes.html
* igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-a-hdmi-a-3:
- shard-dg2: [ABORT][294] ([i915#15759]) -> [PASS][295] +4 other tests pass
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-5/igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-a-hdmi-a-3.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-8/igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-a-hdmi-a-3.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-rkl: [INCOMPLETE][296] ([i915#12358] / [i915#14152]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-3/igt@kms_cursor_crc@cursor-suspend.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-2/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_flip@flip-vs-panning:
- shard-snb: [INCOMPLETE][298] ([i915#12314]) -> [PASS][299] +1 other test pass
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-snb5/igt@kms_flip@flip-vs-panning.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-snb7/igt@kms_flip@flip-vs-panning.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: [SKIP][300] ([i915#15073]) -> [PASS][301]
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-6/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg1: [SKIP][302] ([i915#15073]) -> [PASS][303]
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-12/igt@kms_pm_rpm@modeset-lpsp.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [SKIP][304] ([i915#15073]) -> [PASS][305] +1 other test pass
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@system-suspend-idle:
- shard-rkl: [INCOMPLETE][306] ([i915#14419]) -> [PASS][307]
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-4/igt@kms_pm_rpm@system-suspend-idle.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-5/igt@kms_pm_rpm@system-suspend-idle.html
#### Warnings ####
* igt@gem_ccs@large-ctrl-surf-copy:
- shard-rkl: [SKIP][308] ([i915#13008]) -> [SKIP][309] ([i915#13008] / [i915#14544])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@gem_ccs@large-ctrl-surf-copy.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-rkl: [SKIP][310] ([i915#14544] / [i915#6335]) -> [SKIP][311] ([i915#6335])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_create@create-ext-cpu-access-big.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_sseu@invalid-args:
- shard-rkl: [SKIP][312] ([i915#14544] / [i915#280]) -> [SKIP][313] ([i915#280])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_ctx_sseu@invalid-args.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-rkl: [SKIP][314] ([i915#14544] / [i915#3281]) -> [SKIP][315] ([i915#3281]) +1 other test skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_exec_reloc@basic-concurrent0.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_reloc@basic-cpu-read:
- shard-rkl: [SKIP][316] ([i915#3281]) -> [SKIP][317] ([i915#14544] / [i915#3281])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-read.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: [SKIP][318] ([i915#14544] / [i915#2190]) -> [SKIP][319] ([i915#2190])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_huc_copy@huc-copy.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@massive-random:
- shard-rkl: [SKIP][320] ([i915#4613]) -> [SKIP][321] ([i915#14544] / [i915#4613]) +1 other test skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@gem_lmem_swapping@massive-random.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gem_lmem_swapping@massive-random.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-rkl: [SKIP][322] ([i915#14544] / [i915#4613]) -> [SKIP][323] ([i915#4613])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_lmem_swapping@verify-ccs.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_pwrite_snooped:
- shard-rkl: [SKIP][324] ([i915#3282]) -> [SKIP][325] ([i915#14544] / [i915#3282]) +1 other test skip
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@gem_pwrite_snooped.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gem_pwrite_snooped.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: [SKIP][326] ([i915#14544] / [i915#8411]) -> [SKIP][327] ([i915#8411])
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-3/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-rkl: [SKIP][328] ([i915#8411]) -> [SKIP][329] ([i915#14544] / [i915#8411])
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: [SKIP][330] ([i915#14544] / [i915#3282]) -> [SKIP][331] ([i915#3282]) +3 other tests skip
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gem_set_tiling_vs_pwrite.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: [SKIP][332] ([i915#14544] / [i915#2527]) -> [SKIP][333] ([i915#2527])
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@gen9_exec_parse@bb-chained.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@valid-registers:
- shard-rkl: [SKIP][334] ([i915#2527]) -> [SKIP][335] ([i915#14544] / [i915#2527]) +2 other tests skip
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: [SKIP][336] ([i915#14544] / [i915#4387]) -> [SKIP][337] ([i915#4387])
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@i915_pm_sseu@full-enable.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@i915_pm_sseu@full-enable.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-rkl: [SKIP][338] ([i915#5286]) -> [SKIP][339] ([i915#14544] / [i915#5286]) +2 other tests skip
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-180:
- shard-dg1: [SKIP][340] ([i915#4538] / [i915#5286]) -> [SKIP][341] ([i915#4423] / [i915#4538] / [i915#5286])
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-rkl: [SKIP][342] ([i915#14544] / [i915#5286]) -> [SKIP][343] ([i915#5286])
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: [SKIP][344] ([i915#3638]) -> [SKIP][345] ([i915#14544] / [i915#3638]) +1 other test skip
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_big_fb@linear-8bpp-rotate-270.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-rkl: [SKIP][346] ([i915#14544] / [i915#3638]) -> [SKIP][347] ([i915#3638])
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-rkl: [SKIP][348] ([i915#14544]) -> [SKIP][349] +4 other tests skip
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
- shard-rkl: [SKIP][350] ([i915#14098] / [i915#6095]) -> [SKIP][351] ([i915#14098] / [i915#14544] / [i915#6095]) +4 other tests skip
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-rkl: [SKIP][352] ([i915#12313]) -> [SKIP][353] ([i915#12313] / [i915#14544])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-rkl: [SKIP][354] ([i915#12805] / [i915#14544]) -> [SKIP][355] ([i915#12805])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: [SKIP][356] ([i915#6095]) -> [SKIP][357] ([i915#14544] / [i915#6095])
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: [SKIP][358] ([i915#14544] / [i915#6095]) -> [SKIP][359] ([i915#6095]) +9 other tests skip
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2:
- shard-rkl: [SKIP][360] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][361] ([i915#14098] / [i915#6095]) +9 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: [SKIP][362] ([i915#3742]) -> [SKIP][363] ([i915#14544] / [i915#3742])
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_cdclk@plane-scaling.html
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-rkl: [SKIP][364] ([i915#11151] / [i915#7828]) -> [SKIP][365] ([i915#11151] / [i915#14544] / [i915#7828]) +1 other test skip
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm:
- shard-dg1: [SKIP][366] ([i915#11151] / [i915#4423] / [i915#7828]) -> [SKIP][367] ([i915#11151] / [i915#7828])
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_chamelium_hpd@hdmi-hpd-storm.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-rkl: [SKIP][368] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][369] ([i915#11151] / [i915#7828]) +1 other test skip
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_content_protection@dp-mst-type-0-hdcp14:
- shard-rkl: [SKIP][370] ([i915#15330]) -> [SKIP][371] ([i915#14544] / [i915#15330])
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: [SKIP][372] ([i915#14544] / [i915#15330] / [i915#3116]) -> [SKIP][373] ([i915#15330] / [i915#3116])
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic-type-1:
- shard-rkl: [SKIP][374] ([i915#6944] / [i915#9424]) -> [SKIP][375] ([i915#14544] / [i915#6944] / [i915#9424])
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_content_protection@lic-type-1.html
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][376] ([i915#6944] / [i915#9424]) -> [SKIP][377] ([i915#9433])
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-14/igt@kms_content_protection@mei-interface.html
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-13/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-rkl: [SKIP][378] -> [SKIP][379] ([i915#14544]) +7 other tests skip
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: [SKIP][380] ([i915#4103]) -> [SKIP][381] ([i915#14544] / [i915#4103])
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-rkl: [SKIP][382] ([i915#13748] / [i915#14544]) -> [SKIP][383] ([i915#13748])
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_dp_link_training@uhbr-mst.html
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][384] ([i915#3955]) -> [SKIP][385] ([i915#14544] / [i915#3955])
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][386] ([i915#14544] / [i915#3955]) -> [SKIP][387] ([i915#3955])
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-rkl: [SKIP][388] ([i915#14544] / [i915#4854]) -> [SKIP][389] ([i915#4854])
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_feature_discovery@chamelium.html
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@psr2:
- shard-rkl: [SKIP][390] ([i915#658]) -> [SKIP][391] ([i915#14544] / [i915#658])
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_feature_discovery@psr2.html
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-rkl: [SKIP][392] ([i915#9934]) -> [SKIP][393] ([i915#14544] / [i915#9934]) +2 other tests skip
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_flip@2x-absolute-wf_vblank.html
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-rkl: [SKIP][394] ([i915#15643]) -> [SKIP][395] ([i915#14544] / [i915#15643]) +1 other test skip
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
- shard-rkl: [SKIP][396] ([i915#14544] / [i915#15643]) -> [SKIP][397] ([i915#15643]) +1 other test skip
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-dg1: [SKIP][398] -> [ABORT][399] ([i915#4423])
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_force_connector_basic@force-load-detect.html
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_force_connector_basic@force-load-detect.html
- shard-mtlp: [SKIP][400] -> [SKIP][401] ([i915#15672])
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-mtlp-2/igt@kms_force_connector_basic@force-load-detect.html
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-mtlp-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg1: [SKIP][402] ([i915#4423]) -> [SKIP][403]
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][404] ([i915#1825]) -> [SKIP][405] ([i915#14544] / [i915#1825]) +12 other tests skip
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
- shard-rkl: [SKIP][406] ([i915#15102]) -> [SKIP][407] ([i915#14544] / [i915#15102]) +2 other tests skip
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][408] ([i915#15102] / [i915#3458]) -> [SKIP][409] ([i915#10433] / [i915#15102] / [i915#3458])
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-dg1: [SKIP][410] -> [SKIP][411] ([i915#4423])
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
- shard-rkl: [SKIP][412] ([i915#14544] / [i915#15102]) -> [SKIP][413] ([i915#15102])
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt:
- shard-dg1: [SKIP][414] ([i915#15102] / [i915#4423]) -> [SKIP][415] ([i915#15102])
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt.html
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-rkl: [SKIP][416] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][417] ([i915#15102] / [i915#3023]) +3 other tests skip
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-rkl: [SKIP][418] ([i915#15102] / [i915#3023]) -> [SKIP][419] ([i915#14544] / [i915#15102] / [i915#3023]) +7 other tests skip
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-dg1: [SKIP][420] ([i915#15102] / [i915#3458]) -> [SKIP][421] ([i915#15102] / [i915#3458] / [i915#4423])
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
- shard-rkl: [SKIP][422] ([i915#14544] / [i915#1825]) -> [SKIP][423] ([i915#1825]) +10 other tests skip
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-dg1: [SKIP][424] ([i915#3555] / [i915#8228]) -> [SKIP][425] ([i915#3555] / [i915#4423] / [i915#8228])
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_hdr@bpc-switch-dpms.html
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg1: [SKIP][426] ([i915#15459] / [i915#4423]) -> [SKIP][427] ([i915#15459])
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-19/igt@kms_joiner@basic-force-big-joiner.html
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-17/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-rkl: [SKIP][428] ([i915#15460]) -> [SKIP][429] ([i915#14544] / [i915#15460])
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_joiner@invalid-modeset-big-joiner.html
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-rkl: [SKIP][430] ([i915#14544] / [i915#15458]) -> [SKIP][431] ([i915#15458])
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-yftiled:
- shard-rkl: [SKIP][432] ([i915#14712]) -> [SKIP][433] ([i915#14544] / [i915#14712])
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
- shard-rkl: [SKIP][434] ([i915#15709]) -> [SKIP][435] ([i915#14544] / [i915#15709]) +2 other tests skip
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
- shard-rkl: [SKIP][436] ([i915#14544] / [i915#15709]) -> [SKIP][437] ([i915#15709]) +1 other test skip
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-rkl: [SKIP][438] ([i915#13958]) -> [SKIP][439] ([i915#13958] / [i915#14544])
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_plane_multiple@2x-tiling-none.html
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-rkl: [SKIP][440] ([i915#14544] / [i915#15329]) -> [SKIP][441] ([i915#15329]) +3 other tests skip
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-rkl: [SKIP][442] ([i915#14544] / [i915#5354]) -> [SKIP][443] ([i915#5354])
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_pm_backlight@fade-with-suspend.html
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][444] ([i915#3828]) -> [SKIP][445] ([i915#9340])
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
- shard-dg1: [SKIP][446] ([i915#11520]) -> [SKIP][447] ([i915#11520] / [i915#4423])
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-16/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-18/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
- shard-rkl: [SKIP][448] ([i915#11520] / [i915#14544]) -> [SKIP][449] ([i915#11520])
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
- shard-rkl: [SKIP][450] ([i915#11520]) -> [SKIP][451] ([i915#11520] / [i915#14544]) +2 other tests skip
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-rkl: [SKIP][452] ([i915#9683]) -> [SKIP][453] ([i915#14544] / [i915#9683])
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr-sprite-mmap-gtt:
- shard-rkl: [SKIP][454] ([i915#1072] / [i915#9732]) -> [SKIP][455] ([i915#1072] / [i915#14544] / [i915#9732]) +6 other tests skip
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-5/igt@kms_psr@fbc-psr-sprite-mmap-gtt.html
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_psr@fbc-psr-sprite-mmap-gtt.html
* igt@kms_psr@fbc-psr-sprite-plane-onoff:
- shard-dg1: [SKIP][456] ([i915#1072] / [i915#9732]) -> [SKIP][457] ([i915#1072] / [i915#4423] / [i915#9732])
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_psr@fbc-psr-sprite-plane-onoff.html
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_psr@fbc-psr-sprite-plane-onoff.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: [SKIP][458] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][459] ([i915#1072] / [i915#9732]) +5 other tests skip
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg1: [SKIP][460] ([i915#3555]) -> [SKIP][461] ([i915#3555] / [i915#4423])
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-dg1-13/igt@kms_scaling_modes@scaling-mode-center.html
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-dg1-16/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-rkl: [SKIP][462] ([i915#14544] / [i915#3555]) -> [SKIP][463] ([i915#3555])
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_vrr@flip-dpms:
- shard-rkl: [SKIP][464] ([i915#14544] / [i915#15243] / [i915#3555]) -> [SKIP][465] ([i915#15243] / [i915#3555])
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-6/igt@kms_vrr@flip-dpms.html
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-4/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@max-min:
- shard-rkl: [SKIP][466] ([i915#9906]) -> [SKIP][467] ([i915#14544] / [i915#9906])
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@kms_vrr@max-min.html
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@kms_vrr@max-min.html
* igt@prime_vgem@basic-read:
- shard-rkl: [SKIP][468] ([i915#3291] / [i915#3708]) -> [SKIP][469] ([i915#14544] / [i915#3291] / [i915#3708])
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18094/shard-rkl-7/igt@prime_vgem@basic-read.html
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/shard-rkl-6/igt@prime_vgem@basic-read.html
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
[i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
[i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
[i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
[i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#12916]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12916
[i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
[i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
[i915#13196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13196
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
[i915#13786]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13786
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
[i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
[i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
[i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
[i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
[i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
[i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
[i915#14785]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14785
[i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
[i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
[i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
[i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
[i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
[i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
[i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
[i915#15342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15342
[i915#15389]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15389
[i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
[i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
[i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
[i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
[i915#15479]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15479
[i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
[i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
[i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
[i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
[i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
[i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
[i915#15722]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15722
[i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
[i915#15734]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15734
[i915#15752]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15752
[i915#15759]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15759
[i915#15778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15778
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_18094 -> Patchwork_162622v1
CI-20190529: 20190529
CI_DRM_18094: d7689f077339984fa4c23c972f591ee318b3c56f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8777: a50285a68dbef0fe11140adef4016a756f57b324 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_162622v1: d7689f077339984fa4c23c972f591ee318b3c56f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v1/index.html
[-- Attachment #2: Type: text/html, Size: 154802 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state
2026-03-05 4:01 ` [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state Ankit Nautiyal
@ 2026-03-06 11:55 ` Ville Syrjälä
2026-03-10 4:54 ` Nautiyal, Ankit K
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2026-03-06 11:55 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, arun.r.murthy
On Thu, Mar 05, 2026 at 09:31:15AM +0530, Ankit Nautiyal wrote:
> Xe3p_lpd introduces new register bits to program a common SDP
> Transmission Line, which the hardware uses to position various
> SDPs. It also adds a separate control register to stagger the different
> SDPs (VSC EXT, PPS, GMP).
>
> Add fields in struct intel_crtc_state to store the state of these new
> registers. Add register readback and pipe config comparison for the new
> fields.
>
> Also add a display version check (HAS_CMN_SDP_TL) to gate access to the
> new registers.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 9 ++++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> 6 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 94ae583e907f..bdbd89600bee 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4217,6 +4217,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
> + intel_dp_cmn_sdp_transmission_line_get_config(pipe_config);
>
> intel_audio_codec_get_config(encoder, pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 27354585ba92..76eea9d23766 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5461,6 +5461,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> }
> PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>
> + PIPE_CONF_CHECK_BOOL(cmn_sdp_tl.enable);
> + PIPE_CONF_CHECK_I(cmn_sdp_tl.transmission_line);
> + PIPE_CONF_CHECK_I(cmn_sdp_tl.vsc_ext_stagger);
> + PIPE_CONF_CHECK_I(cmn_sdp_tl.pps_stagger);
> + PIPE_CONF_CHECK_I(cmn_sdp_tl.gmp_stagger);
This will make things fail every time until you add the actual
code to program these. Ie. you are intentionally introducing
broken bisection steps here.
> +
> PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
> PIPE_CONF_CHECK_I(master_transcoder);
> PIPE_CONF_CHECK_X(joiner_pipes);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index e84c190dcc4f..43e259761048 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -154,6 +154,7 @@ struct intel_display_platforms {
> #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20)
> #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
> #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
> +#define HAS_CMN_SDP_TL(__display) (DISPLAY_VER(__display) >= 35)
> #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
> #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
> #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8a2b37c7bccf..474d6e2ae34b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1298,6 +1298,15 @@ struct intel_crtc_state {
> struct drm_dp_as_sdp as_sdp;
> } infoframes;
>
> + struct {
> + /* Common SDP Transmission line */
> + bool enable;
> + int transmission_line;
> + int vsc_ext_stagger;
> + int pps_stagger;
> + int gmp_stagger;
> + } cmn_sdp_tl;
> +
> u8 eld[MAX_ELD_BYTES];
>
> /* HDMI scrambling status */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 025e906b63a9..86390553800d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7287,3 +7287,24 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>
> return true;
> }
> +
> +void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 val;
> +
> + if (!HAS_CMN_SDP_TL(display))
> + return;
> +
> + val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
> +
> + crtc_state->cmn_sdp_tl.enable = val & TRANSMISSION_LINE_ENABLE;
Tracking the enable bit seems fairly pointless. If it's not set we could
just skip the readout. I don't think we should ever want TL==0?
> + crtc_state->cmn_sdp_tl.transmission_line = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
> +
> + val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
> +
> + crtc_state->cmn_sdp_tl.vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
> + crtc_state->cmn_sdp_tl.pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
> + crtc_state->cmn_sdp_tl.gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index b0bbd5981f57..24df234a43d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -237,4 +237,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>
> +void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_DP_H__ */
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] drm/i915/dp: Enable Common SDP Transmission line
2026-03-05 4:01 ` [PATCH 5/5] drm/i915/dp: Enable Common " Ankit Nautiyal
@ 2026-03-06 11:56 ` Ville Syrjälä
2026-03-10 5:01 ` Nautiyal, Ankit K
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2026-03-06 11:56 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, arun.r.murthy
On Thu, Mar 05, 2026 at 09:31:18AM +0530, Ankit Nautiyal wrote:
> Enable the Common SDP Transmission line for the SDP packets.
> We get the clear picture about the SDPs and guardband only in
> intel_dp_sdp_compute_config_late() therefore we must configure the
> crtc_state members related to Common SDP Transmission line at this
> point.
>
> Currently, the stagger values are set as per the default policy of the
> Hardware. This can be optimized later if we come up with a specific
> driver policy to sequence the SDPs better.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 64 ++++++++++++++++++++++++
> 2 files changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bdbd89600bee..e1e95f18f0ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2726,6 +2726,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> /* 6.o Configure and enable FEC if needed */
> intel_ddi_enable_fec(encoder, crtc_state);
>
> + intel_dp_cmn_sdp_transmission_line_enable(crtc_state);
> +
> /* 7.a 128b/132b SST. */
> if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> /* VCPID 1, start slot 0 for 128b/132b, tu slots */
> @@ -3113,6 +3115,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
> DP_TP_CTL_ENABLE, 0);
> }
>
> + intel_dp_cmn_sdp_transmission_line_disable(crtc_state);
> intel_ddi_disable_fec(encoder, crtc_state);
>
> if (DISPLAY_VER(display) < 14)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 59a8fa5e5ba9..87d73d0239bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7189,6 +7189,68 @@ void intel_dp_mst_resume(struct intel_display *display)
> }
> }
>
> +static
> +void intel_dp_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + bool as_sdp, gmp_sdp, pps_sdp, vsc_sdp, vsc_ext_sdp;
> +
> + if (!HAS_CMN_SDP_TL(display))
> + return;
> +
> + as_sdp = crtc_state->infoframes.enable &
> + intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> +
> + gmp_sdp = crtc_state->infoframes.enable &
> + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> +
> + pps_sdp = crtc_state->infoframes.enable &
> + intel_hdmi_infoframe_enable(DP_SDP_PPS);
> +
> + vsc_sdp = crtc_state->infoframes.enable &
> + intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> + vsc_ext_sdp = crtc_state->infoframes.enable &
> + (intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_VESA) |
> + intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_CEA));
> +
> + if (!gmp_sdp && !pps_sdp && !vsc_sdp && !vsc_ext_sdp)
> + return;
I don't see why we wouldn't just always program this stuff.
> +
> + crtc_state->cmn_sdp_tl.enable = true;
> +
> + /*
> + * When AS SDP is enabled :
> + * - The common SDP Transmission Line matches the EMP SDP Transmission Line.
> + *
> + * When AS SDP is disabled:
> + * - Bspec mentions the positions as lines of delayed vblank.
> + * - Guardband = 1st line of delayed vblank
> + * - Common SDP Transmission line is set to 2nd line of delayed vblank.
> + */
> +
> + if (as_sdp)
> + crtc_state->cmn_sdp_tl.transmission_line =
> + intel_dp_emp_as_sdp_tl(crtc_state);
> + else
> + crtc_state->cmn_sdp_tl.transmission_line =
> + crtc_state->vrr.guardband - 1;
> +
> + /*
> + * Currently we are programming the default stagger values, but these
> + * can be optimized if required, based on number of SDPs enabled.
> + *
> + * Default values of the Transmission lines for SDPs other than AS SDP:
> + * VSC : CMN SDP Transmission line
> + * GMP : CMN SDP Transmission line
> + * PPS : CMN SDP Transmission line + 1
> + * VSC_EXT: CMN SDP Transmission line + 2
> + */
> + crtc_state->cmn_sdp_tl.gmp_stagger = GMP_STAGGER_DEFAULT;
> + crtc_state->cmn_sdp_tl.pps_stagger = PPS_STAGGER_DEFAULT;
> + crtc_state->cmn_sdp_tl.vsc_ext_stagger = VSC_EXT_STAGGER_DEFAULT;
> +}
> +
> static
> int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
> {
> @@ -7202,6 +7264,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
> return -EINVAL;
> }
>
> + intel_dp_cmn_sdp_tl_compute_config_late(crtc_state);
> +
> return 0;
> }
>
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-05 4:01 ` [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Ankit Nautiyal
@ 2026-03-06 12:02 ` Ville Syrjälä
2026-03-10 4:57 ` Nautiyal, Ankit K
2026-03-10 9:08 ` Ville Syrjälä
0 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjälä @ 2026-03-06 12:02 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, arun.r.murthy
On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
> Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
> value used when programming the double‑buffering point and transmission
> line for VRR packets.
> Also improve the documentation: the AS SDP transmission line corresponds
> to the T1 position, which maps to the start of the Vsync pulse.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> 3 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 86390553800d..9204a813639a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> return true;
> }
>
> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> +{
> + /*
> + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
> + * that corresponds to the start of the Vsync pulse.
> + */
> + return crtc_state->vrr.vsync_start;
> +}
Other parts of the code (eg. ALPM) still just directly use the
adjusted_mode timings to calculate the same stuff. So this doesn't
really seem to help us.
Feels like all of our abstractions around this SDP transmission line
stuff are way too low level, and thus the same information is
calculated in different ways in different parts of the code. There
should be a single place that defines the transmission line(s),
and everyone should just consult that stuff (regardless of whether
the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
the new stuff).
> +
> void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 24df234a43d3..abb2fcdea352 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -237,6 +237,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
> for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>
> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
> void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 00ca76dbdd6c..2b4e4e55d008 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -642,12 +642,12 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> * double buffering point and transmission line for VRR packets for
> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> * Since currently we support VRR only for DP/eDP, so this is programmed
> - * to for Adaptive Sync SDP to Vsync start.
> + * only for Adaptive Sync SDP.
> */
> if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> intel_de_write(display,
> EMP_AS_SDP_TL(display, cpu_transcoder),
> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> + EMP_AS_SDP_DB_TL(intel_dp_emp_as_sdp_tl(crtc_state)));
> }
>
> void
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state
2026-03-06 11:55 ` Ville Syrjälä
@ 2026-03-10 4:54 ` Nautiyal, Ankit K
0 siblings, 0 replies; 18+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-10 4:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, arun.r.murthy
On 3/6/2026 5:25 PM, Ville Syrjälä wrote:
> On Thu, Mar 05, 2026 at 09:31:15AM +0530, Ankit Nautiyal wrote:
>> Xe3p_lpd introduces new register bits to program a common SDP
>> Transmission Line, which the hardware uses to position various
>> SDPs. It also adds a separate control register to stagger the different
>> SDPs (VSC EXT, PPS, GMP).
>>
>> Add fields in struct intel_crtc_state to store the state of these new
>> registers. Add register readback and pipe config comparison for the new
>> fields.
>>
>> Also add a display version check (HAS_CMN_SDP_TL) to gate access to the
>> new registers.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
>> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
>> .../drm/i915/display/intel_display_device.h | 1 +
>> .../drm/i915/display/intel_display_types.h | 9 ++++++++
>> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
>> 6 files changed, 40 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 94ae583e907f..bdbd89600bee 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -4217,6 +4217,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>> intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
>> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
>> + intel_dp_cmn_sdp_transmission_line_get_config(pipe_config);
>>
>> intel_audio_codec_get_config(encoder, pipe_config);
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 27354585ba92..76eea9d23766 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5461,6 +5461,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>> }
>> PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
>>
>> + PIPE_CONF_CHECK_BOOL(cmn_sdp_tl.enable);
>> + PIPE_CONF_CHECK_I(cmn_sdp_tl.transmission_line);
>> + PIPE_CONF_CHECK_I(cmn_sdp_tl.vsc_ext_stagger);
>> + PIPE_CONF_CHECK_I(cmn_sdp_tl.pps_stagger);
>> + PIPE_CONF_CHECK_I(cmn_sdp_tl.gmp_stagger);
> This will make things fail every time until you add the actual
> code to program these. Ie. you are intentionally introducing
> broken bisection steps here.
Hmm I was wondering that since at this point in the commit we have not
written these fields, the readout will also be 0 and will always match.
However I now realize that GOP might have programmed these and perhaps
we will immediately start seeing mismatch.
In general when we add a new thing, that we want to track in crtc state,
what should be the best ordering of the patches, does the below makes sense?
- Introduce the new registers
- Add the new members to crtc_state. In the same patch add functions
to read from HW and fill the new member, and also add function to write
into the HW from the crtc_state. (Since at this point of time, nobody is
setting them, so there is effectively no writing yet).
- Write functions that configure the new member of crtc_state in the
(should be part of atomic check phase). Also add PIPE CONF check in same
patch.
>
>> +
>> PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
>> PIPE_CONF_CHECK_I(master_transcoder);
>> PIPE_CONF_CHECK_X(joiner_pipes);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index e84c190dcc4f..43e259761048 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -154,6 +154,7 @@ struct intel_display_platforms {
>> #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20)
>> #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl)
>> #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash)
>> +#define HAS_CMN_SDP_TL(__display) (DISPLAY_VER(__display) >= 35)
>> #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
>> #define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)
>> #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 8a2b37c7bccf..474d6e2ae34b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1298,6 +1298,15 @@ struct intel_crtc_state {
>> struct drm_dp_as_sdp as_sdp;
>> } infoframes;
>>
>> + struct {
>> + /* Common SDP Transmission line */
>> + bool enable;
>> + int transmission_line;
>> + int vsc_ext_stagger;
>> + int pps_stagger;
>> + int gmp_stagger;
>> + } cmn_sdp_tl;
>> +
>> u8 eld[MAX_ELD_BYTES];
>>
>> /* HDMI scrambling status */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 025e906b63a9..86390553800d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7287,3 +7287,24 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>
>> return true;
>> }
>> +
>> +void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_display *display = to_intel_display(crtc_state);
>> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> + u32 val;
>> +
>> + if (!HAS_CMN_SDP_TL(display))
>> + return;
>> +
>> + val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
>> +
>> + crtc_state->cmn_sdp_tl.enable = val & TRANSMISSION_LINE_ENABLE;
> Tracking the enable bit seems fairly pointless. If it's not set we could
> just skip the readout. I don't think we should ever want TL==0?
Makes sense, we can drop enable and just track the base transmission line.
Regards,
Ankit
>
>> + crtc_state->cmn_sdp_tl.transmission_line = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
>> +
>> + val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
>> +
>> + crtc_state->cmn_sdp_tl.vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
>> + crtc_state->cmn_sdp_tl.pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
>> + crtc_state->cmn_sdp_tl.gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index b0bbd5981f57..24df234a43d3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -237,4 +237,6 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>> for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>
>> +void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
>> +
>> #endif /* __INTEL_DP_H__ */
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-06 12:02 ` Ville Syrjälä
@ 2026-03-10 4:57 ` Nautiyal, Ankit K
2026-03-10 9:08 ` Ville Syrjälä
1 sibling, 0 replies; 18+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-10 4:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, arun.r.murthy
On 3/6/2026 5:32 PM, Ville Syrjälä wrote:
> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
>> Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
>> value used when programming the double‑buffering point and transmission
>> line for VRR packets.
>> Also improve the documentation: the AS SDP transmission line corresponds
>> to the T1 position, which maps to the start of the Vsync pulse.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
>> 3 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 86390553800d..9204a813639a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>> return true;
>> }
>>
>> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>> +{
>> + /*
>> + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
>> + * that corresponds to the start of the Vsync pulse.
>> + */
>> + return crtc_state->vrr.vsync_start;
>> +}
> Other parts of the code (eg. ALPM) still just directly use the
> adjusted_mode timings to calculate the same stuff. So this doesn't
> really seem to help us.
>
> Feels like all of our abstractions around this SDP transmission line
> stuff are way too low level, and thus the same information is
> calculated in different ways in different parts of the code. There
> should be a single place that defines the transmission line(s),
> and everyone should just consult that stuff (regardless of whether
> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
> the new stuff).
Yeah currently AS SDP itself is not used properly for different features.
In the series [1], I am trying to address that. Perhaps that will help
making things better for the EMP_AS_SDP_TL. (I am yet to send the new
version for this)
One more thing to note is that if AS SDP is sent, EMP_AS_SDP_TL is the
point where VSC SDP is also sent. I am not sure if we need to do
something in existing code for it yet.
[1] https://patchwork.freedesktop.org/series/161977/
Regards,
Ankit
>
>> +
>> void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
>> index 24df234a43d3..abb2fcdea352 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -237,6 +237,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>> for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>> for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>>
>> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>> void intel_dp_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
>>
>> #endif /* __INTEL_DP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 00ca76dbdd6c..2b4e4e55d008 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -642,12 +642,12 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>> * double buffering point and transmission line for VRR packets for
>> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
>> * Since currently we support VRR only for DP/eDP, so this is programmed
>> - * to for Adaptive Sync SDP to Vsync start.
>> + * only for Adaptive Sync SDP.
>> */
>> if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
>> intel_de_write(display,
>> EMP_AS_SDP_TL(display, cpu_transcoder),
>> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>> + EMP_AS_SDP_DB_TL(intel_dp_emp_as_sdp_tl(crtc_state)));
>> }
>>
>> void
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] drm/i915/dp: Enable Common SDP Transmission line
2026-03-06 11:56 ` Ville Syrjälä
@ 2026-03-10 5:01 ` Nautiyal, Ankit K
0 siblings, 0 replies; 18+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-10 5:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, arun.r.murthy
On 3/6/2026 5:26 PM, Ville Syrjälä wrote:
> On Thu, Mar 05, 2026 at 09:31:18AM +0530, Ankit Nautiyal wrote:
>> Enable the Common SDP Transmission line for the SDP packets.
>> We get the clear picture about the SDPs and guardband only in
>> intel_dp_sdp_compute_config_late() therefore we must configure the
>> crtc_state members related to Common SDP Transmission line at this
>> point.
>>
>> Currently, the stagger values are set as per the default policy of the
>> Hardware. This can be optimized later if we come up with a specific
>> driver policy to sequence the SDPs better.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
>> drivers/gpu/drm/i915/display/intel_dp.c | 64 ++++++++++++++++++++++++
>> 2 files changed, 67 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index bdbd89600bee..e1e95f18f0ed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2726,6 +2726,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>> /* 6.o Configure and enable FEC if needed */
>> intel_ddi_enable_fec(encoder, crtc_state);
>>
>> + intel_dp_cmn_sdp_transmission_line_enable(crtc_state);
>> +
>> /* 7.a 128b/132b SST. */
>> if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
>> /* VCPID 1, start slot 0 for 128b/132b, tu slots */
>> @@ -3113,6 +3115,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
>> DP_TP_CTL_ENABLE, 0);
>> }
>>
>> + intel_dp_cmn_sdp_transmission_line_disable(crtc_state);
>> intel_ddi_disable_fec(encoder, crtc_state);
>>
>> if (DISPLAY_VER(display) < 14)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 59a8fa5e5ba9..87d73d0239bc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7189,6 +7189,68 @@ void intel_dp_mst_resume(struct intel_display *display)
>> }
>> }
>>
>> +static
>> +void intel_dp_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_display *display = to_intel_display(crtc_state);
>> + bool as_sdp, gmp_sdp, pps_sdp, vsc_sdp, vsc_ext_sdp;
>> +
>> + if (!HAS_CMN_SDP_TL(display))
>> + return;
>> +
>> + as_sdp = crtc_state->infoframes.enable &
>> + intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>> +
>> + gmp_sdp = crtc_state->infoframes.enable &
>> + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
>> +
>> + pps_sdp = crtc_state->infoframes.enable &
>> + intel_hdmi_infoframe_enable(DP_SDP_PPS);
>> +
>> + vsc_sdp = crtc_state->infoframes.enable &
>> + intel_hdmi_infoframe_enable(DP_SDP_VSC);
>> +
>> + vsc_ext_sdp = crtc_state->infoframes.enable &
>> + (intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_VESA) |
>> + intel_hdmi_infoframe_enable(DP_SDP_VSC_EXT_CEA));
>> +
>> + if (!gmp_sdp && !pps_sdp && !vsc_sdp && !vsc_ext_sdp)
>> + return;
> I don't see why we wouldn't just always program this stuff.
Hmm..Yeah you are right, we can always program this stuff. By not
enabling, the transcoder will simply be ready to use its own logic.
I will drop this check and the variables to track the SDPs. Later at
some point when we want to optimize the staggering, then we might need
something like these.
Regards,
Ankit
>
>> +
>> + crtc_state->cmn_sdp_tl.enable = true;
>> +
>> + /*
>> + * When AS SDP is enabled :
>> + * - The common SDP Transmission Line matches the EMP SDP Transmission Line.
>> + *
>> + * When AS SDP is disabled:
>> + * - Bspec mentions the positions as lines of delayed vblank.
>> + * - Guardband = 1st line of delayed vblank
>> + * - Common SDP Transmission line is set to 2nd line of delayed vblank.
>> + */
>> +
>> + if (as_sdp)
>> + crtc_state->cmn_sdp_tl.transmission_line =
>> + intel_dp_emp_as_sdp_tl(crtc_state);
>> + else
>> + crtc_state->cmn_sdp_tl.transmission_line =
>> + crtc_state->vrr.guardband - 1;
>> +
>> + /*
>> + * Currently we are programming the default stagger values, but these
>> + * can be optimized if required, based on number of SDPs enabled.
>> + *
>> + * Default values of the Transmission lines for SDPs other than AS SDP:
>> + * VSC : CMN SDP Transmission line
>> + * GMP : CMN SDP Transmission line
>> + * PPS : CMN SDP Transmission line + 1
>> + * VSC_EXT: CMN SDP Transmission line + 2
>> + */
>> + crtc_state->cmn_sdp_tl.gmp_stagger = GMP_STAGGER_DEFAULT;
>> + crtc_state->cmn_sdp_tl.pps_stagger = PPS_STAGGER_DEFAULT;
>> + crtc_state->cmn_sdp_tl.vsc_ext_stagger = VSC_EXT_STAGGER_DEFAULT;
>> +}
>> +
>> static
>> int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
>> {
>> @@ -7202,6 +7264,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
>> return -EINVAL;
>> }
>>
>> + intel_dp_cmn_sdp_tl_compute_config_late(crtc_state);
>> +
>> return 0;
>> }
>>
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-06 12:02 ` Ville Syrjälä
2026-03-10 4:57 ` Nautiyal, Ankit K
@ 2026-03-10 9:08 ` Ville Syrjälä
2026-03-11 11:54 ` Nautiyal, Ankit K
1 sibling, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2026-03-10 9:08 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe, arun.r.murthy
On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
> > Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
> > value used when programming the double‑buffering point and transmission
> > line for VRR packets.
> > Also improve the documentation: the AS SDP transmission line corresponds
> > to the T1 position, which maps to the start of the Vsync pulse.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
> > drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> > 3 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 86390553800d..9204a813639a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> > return true;
> > }
> >
> > +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> > +{
> > + /*
> > + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
> > + * that corresponds to the start of the Vsync pulse.
> > + */
> > + return crtc_state->vrr.vsync_start;
> > +}
>
> Other parts of the code (eg. ALPM) still just directly use the
> adjusted_mode timings to calculate the same stuff. So this doesn't
> really seem to help us.
>
> Feels like all of our abstractions around this SDP transmission line
> stuff are way too low level, and thus the same information is
> calculated in different ways in different parts of the code. There
> should be a single place that defines the transmission line(s),
> and everyone should just consult that stuff (regardless of whether
> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
> the new stuff).
I think instead of tracking the low level stagger values directly, what
we want to track is just the transmission line itself for each type of
SDP. That seems like a form that is easier to use elsewhere in the code.
And to accommodate VRR I suppose we should use the "transmission line
is specified relative to the end of vblank/vtotal" convention for all
of these.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-10 9:08 ` Ville Syrjälä
@ 2026-03-11 11:54 ` Nautiyal, Ankit K
2026-03-11 12:04 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-11 11:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, arun.r.murthy
On 3/10/2026 2:38 PM, Ville Syrjälä wrote:
> On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote:
>> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
>>> Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
>>> value used when programming the double‑buffering point and transmission
>>> line for VRR packets.
>>> Also improve the documentation: the AS SDP transmission line corresponds
>>> to the T1 position, which maps to the start of the Vsync pulse.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
>>> 3 files changed, 12 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 86390553800d..9204a813639a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>> return true;
>>> }
>>>
>>> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + /*
>>> + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
>>> + * that corresponds to the start of the Vsync pulse.
>>> + */
>>> + return crtc_state->vrr.vsync_start;
>>> +}
>> Other parts of the code (eg. ALPM) still just directly use the
>> adjusted_mode timings to calculate the same stuff. So this doesn't
>> really seem to help us.
>>
>> Feels like all of our abstractions around this SDP transmission line
>> stuff are way too low level, and thus the same information is
>> calculated in different ways in different parts of the code. There
>> should be a single place that defines the transmission line(s),
>> and everyone should just consult that stuff (regardless of whether
>> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
>> the new stuff).
> I think instead of tracking the low level stagger values directly, what
> we want to track is just the transmission line itself for each type of
> SDP. That seems like a form that is easier to use elsewhere in the code.
Agreed storing TL will be easier, stagger values can be derived from that.
So we set the transmission line for the packets only if we plan to send
them right?
>
> And to accommodate VRR I suppose we should use the "transmission line
> is specified relative to the end of vblank/vtotal" convention for all
> of these.
Makes sense.
Regards,
Ankit
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-11 11:54 ` Nautiyal, Ankit K
@ 2026-03-11 12:04 ` Ville Syrjälä
2026-03-11 12:10 ` Nautiyal, Ankit K
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2026-03-11 12:04 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe, arun.r.murthy
On Wed, Mar 11, 2026 at 05:24:22PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/10/2026 2:38 PM, Ville Syrjälä wrote:
> > On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote:
> >> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
> >>> Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
> >>> value used when programming the double‑buffering point and transmission
> >>> line for VRR packets.
> >>> Also improve the documentation: the AS SDP transmission line corresponds
> >>> to the T1 position, which maps to the start of the Vsync pulse.
> >>>
> >>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
> >>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> >>> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
> >>> 3 files changed, 12 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> >>> index 86390553800d..9204a813639a 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> >>> @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
> >>> return true;
> >>> }
> >>>
> >>> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
> >>> +{
> >>> + /*
> >>> + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
> >>> + * that corresponds to the start of the Vsync pulse.
> >>> + */
> >>> + return crtc_state->vrr.vsync_start;
> >>> +}
> >> Other parts of the code (eg. ALPM) still just directly use the
> >> adjusted_mode timings to calculate the same stuff. So this doesn't
> >> really seem to help us.
> >>
> >> Feels like all of our abstractions around this SDP transmission line
> >> stuff are way too low level, and thus the same information is
> >> calculated in different ways in different parts of the code. There
> >> should be a single place that defines the transmission line(s),
> >> and everyone should just consult that stuff (regardless of whether
> >> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
> >> the new stuff).
> > I think instead of tracking the low level stagger values directly, what
> > we want to track is just the transmission line itself for each type of
> > SDP. That seems like a form that is easier to use elsewhere in the code.
>
> Agreed storing TL will be easier, stagger values can be derived from that.
>
> So we set the transmission line for the packets only if we plan to send
> them right?
I don't see why we wouldn't just always set them. And if we set one we
have to anyway set all of them since they're all derived from that one
pair of registers.
>
>
> >
> > And to accommodate VRR I suppose we should use the "transmission line
> > is specified relative to the end of vblank/vtotal" convention for all
> > of these.
>
> Makes sense.
>
>
> Regards,
>
> Ankit
>
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation
2026-03-11 12:04 ` Ville Syrjälä
@ 2026-03-11 12:10 ` Nautiyal, Ankit K
0 siblings, 0 replies; 18+ messages in thread
From: Nautiyal, Ankit K @ 2026-03-11 12:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe, arun.r.murthy
On 3/11/2026 5:34 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:24:22PM +0530, Nautiyal, Ankit K wrote:
>> On 3/10/2026 2:38 PM, Ville Syrjälä wrote:
>>> On Fri, Mar 06, 2026 at 02:02:09PM +0200, Ville Syrjälä wrote:
>>>> On Thu, Mar 05, 2026 at 09:31:16AM +0530, Ankit Nautiyal wrote:
>>>>> Add a helper, intel_dp_emp_as_sdp_tl(), to compute the EMP_AS_SDP_TL
>>>>> value used when programming the double‑buffering point and transmission
>>>>> line for VRR packets.
>>>>> Also improve the documentation: the AS SDP transmission line corresponds
>>>>> to the T1 position, which maps to the start of the Vsync pulse.
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
>>>>> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
>>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
>>>>> 3 files changed, 12 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> index 86390553800d..9204a813639a 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>>> @@ -7288,6 +7288,15 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
>>>>> return true;
>>>>> }
>>>>>
>>>>> +int intel_dp_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
>>>>> +{
>>>>> + /*
>>>>> + * EMP_AS_SDP_TL defines the T1 position : The default AS SDP position
>>>>> + * that corresponds to the start of the Vsync pulse.
>>>>> + */
>>>>> + return crtc_state->vrr.vsync_start;
>>>>> +}
>>>> Other parts of the code (eg. ALPM) still just directly use the
>>>> adjusted_mode timings to calculate the same stuff. So this doesn't
>>>> really seem to help us.
>>>>
>>>> Feels like all of our abstractions around this SDP transmission line
>>>> stuff are way too low level, and thus the same information is
>>>> calculated in different ways in different parts of the code. There
>>>> should be a single place that defines the transmission line(s),
>>>> and everyone should just consult that stuff (regardless of whether
>>>> the platform uses implicit transmission lines, EMP_AS_SDP_TL, or
>>>> the new stuff).
>>> I think instead of tracking the low level stagger values directly, what
>>> we want to track is just the transmission line itself for each type of
>>> SDP. That seems like a form that is easier to use elsewhere in the code.
>> Agreed storing TL will be easier, stagger values can be derived from that.
>>
>> So we set the transmission line for the packets only if we plan to send
>> them right?
> I don't see why we wouldn't just always set them. And if we set one we
> have to anyway set all of them since they're all derived from that one
> pair of registers.
Hmm alright, I will take care of this in the next revision.
(I will be Off for a few days, will come back to it in couple of weeks).
Thanks Ville for all the inputs.
Regards,
Ankit
>
>>
>>> And to accommodate VRR I suppose we should use the "transmission line
>>> is specified relative to the end of vblank/vtotal" convention for all
>>> of these.
>> Makes sense.
>>
>>
>> Regards,
>>
>> Ankit
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-03-11 12:11 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-05 4:01 [PATCH 0/5] Add support for Common SDP Transmission Line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 1/5] drm/i915/nvl: Add register definitions for common " Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 2/5] drm/i915/dp: Add fields to store CMN_SDP_TL register state in crtc_state Ankit Nautiyal
2026-03-06 11:55 ` Ville Syrjälä
2026-03-10 4:54 ` Nautiyal, Ankit K
2026-03-05 4:01 ` [PATCH 3/5] drm/i915/dp: Add helper for AS SDP TL and fix documentation Ankit Nautiyal
2026-03-06 12:02 ` Ville Syrjälä
2026-03-10 4:57 ` Nautiyal, Ankit K
2026-03-10 9:08 ` Ville Syrjälä
2026-03-11 11:54 ` Nautiyal, Ankit K
2026-03-11 12:04 ` Ville Syrjälä
2026-03-11 12:10 ` Nautiyal, Ankit K
2026-03-05 4:01 ` [PATCH 4/5] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line Ankit Nautiyal
2026-03-05 4:01 ` [PATCH 5/5] drm/i915/dp: Enable Common " Ankit Nautiyal
2026-03-06 11:56 ` Ville Syrjälä
2026-03-10 5:01 ` Nautiyal, Ankit K
2026-03-05 5:40 ` ✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line Patchwork
2026-03-06 4:34 ` ✗ i915.CI.Full: failure " Patchwork
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