From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, jeff.mcgee@intel.com
Subject: Re: [PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status
Date: 02 Mar 2015 23:28:11 -0800 [thread overview]
Message-ID: <acb6cf$ke7cif@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1425061352-29188-3-git-send-email-jeff.mcgee@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5863
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -7 278/278 271/278
ILK 308/308 308/308
SNB -1 284/284 283/284
IVB 380/380 380/380
BYT 294/294 294/294
HSW -2 387/387 385/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync CRASH(2)PASS(6) CRASH(2)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(2)PASS(5) CRASH(1)PASS(1)
*PNV igt_gem_userptr_blits_create-destroy-sync PASS(2) NRUN(1)PASS(1)
*PNV igt_gem_userptr_blits_minor-sync-interruptible PASS(2) DMESG_WARN(1)PASS(1)
PNV igt_gen3_render_linear_blits FAIL(3)PASS(5) FAIL(2)
PNV igt_gen3_render_mixed_blits FAIL(2)PASS(7) FAIL(2)
PNV igt_gem_fence_thrash_bo-write-verify-threaded-none FAIL(1)CRASH(1)PASS(3) CRASH(1)PASS(1)
*SNB igt_gem_fence_thrash_bo-write-verify-y PASS(3) DMESG_WARN(1)PASS(1)
*HSW igt_gem_bad_length PASS(2) DMESG_WARN(1)PASS(1)
*HSW igt_gem_storedw_loop_blt PASS(3) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(10) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-03-03 7:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-27 18:22 [PATCH 0/2] SSEU detection for CHV jeff.mcgee
2015-02-27 18:22 ` [PATCH 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info jeff.mcgee
2015-02-27 18:29 ` Ville Syrjälä
2015-02-27 18:22 ` [PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status jeff.mcgee
2015-02-27 18:36 ` Ville Syrjälä
2015-03-03 7:28 ` shuang.he [this message]
2015-02-27 20:12 ` [PATCH v2 1/2] drm/i915/chv: Determine CHV slice/subslice/EU info jeff.mcgee
2015-02-27 20:12 ` Ville Syrjälä
2015-03-03 1:33 ` Jeff McGee
2015-03-07 1:38 ` [PATCH 0/2] SSEU detection for CHV Jeff McGee
2015-03-09 8:40 ` Daniel Vetter
2015-03-09 16:41 ` Jeff McGee
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='acb6cf$ke7cif@fmsmga002.fm.intel.com' \
--to=shuang.he@intel.com \
--cc=ethan.gao@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jeff.mcgee@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox