From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, gaurav.k.singh@intel.com
Subject: Re: [PATCH] drm/i915: Changes for calculating dsi clk for CHT
Date: 03 Mar 2015 18:17:54 -0800 [thread overview]
Message-ID: <acb6cf$keml5o@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1425387453-24986-1-git-send-email-gaurav.k.singh@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5875
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -5 278/278 273/278
ILK 308/308 308/308
SNB -1 284/284 283/284
IVB 380/380 380/380
BYT 294/294 294/294
HSW -1 387/387 386/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync NO_RESULT(1)CRASH(5)NRUN(1)PASS(7) CRASH(1)PASS(1)
PNV igt_gem_userptr_blits_coherency-unsync NO_RESULT(1)CRASH(4)PASS(6) CRASH(2)
PNV igt_gen3_render_linear_blits FAIL(4)NRUN(1)DMESG_WARN(1)PASS(7) FAIL(2)
PNV igt_gen3_render_mixed_blits FAIL(7)PASS(9) FAIL(2)
PNV igt_gem_fence_thrash_bo-write-verify-threaded-none FAIL(2)CRASH(4)PASS(4) FAIL(1)CRASH(1)
*SNB igt_gem_fence_thrash_bo-write-verify-x PASS(2) DMESG_WARN(1)PASS(1)
*HSW igt_gem_storedw_loop_vebox PASS(2) DMESG_WARN(2)
*BDW igt_gem_gtt_hog PASS(18) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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prev parent reply other threads:[~2015-03-04 2:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-03 12:57 [PATCH] drm/i915: Changes for calculating dsi clk for CHT Gaurav K Singh
2015-03-04 2:17 ` shuang.he [this message]
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