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From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
	intel-gfx@lists.freedesktop.org, damien.lespiau@intel.com
Subject: Re: [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1
Date: 06 Mar 2015 17:32:37 -0800	[thread overview]
Message-ID: <acb6cf$kgca0h@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1425667853-5717-7-git-send-email-damien.lespiau@intel.com>

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5908
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -13              275/275              262/275
ILK                                  307/307              307/307
SNB                 -1              284/284              283/284
IVB                                  375/375              375/375
BYT                                  294/294              294/294
HSW                                  385/385              385/385
BDW                 -1              314/314              313/314
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_exec_params_DR1-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_DR4-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_no-bsd      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-master      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-root      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_2-spare-fences      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-copy      PASS(2)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      PASS(4)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_bad-flink      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_flink-lifetime      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_race_flink_close      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_gtt_cpu_tlb      PASS(2)      NRUN(1)PASS(1)
*SNB  igt_gem_exec_params_rel-constants-invalid-rel-gen5      PASS(2)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(5)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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  reply	other threads:[~2015-03-07  1:32 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-06 18:50 [PATCH 0/6] SKL post-enable power well hook (v2) Damien Lespiau
2015-03-06 18:50 ` [PATCH 1/6] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask Damien Lespiau
2015-03-09  8:50   ` Daniel Vetter
2015-03-06 18:50 ` [PATCH 2/6] drm/i915/skl: Introduce enable_requested and is_enabled in the power well code Damien Lespiau
2015-03-06 18:50 ` [PATCH 3/6] drm/i915/skl: Mirror what we do on HSW for the power well enable log message Damien Lespiau
2015-03-06 18:50 ` [PATCH 4/6] drm/i915/skl: Restore pipe interrupt registers after power well enabling Damien Lespiau
2015-03-06 18:50 ` [PATCH 5/6] drm/i915: Remove unused condition in hsw_power_well_post_enable() Damien Lespiau
2015-03-06 18:50 ` [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
2015-03-07  1:32   ` shuang.he [this message]
2015-03-06 19:28 ` [PATCH 0/6] SKL post-enable power well hook (v2) Paulo Zanoni
2015-03-09  9:00   ` Daniel Vetter

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