[PATCH 0/6] SKL post-enable power well hook (v2)

[PATCH 0/6] SKL post-enable power well hook (v2)

[Damien Lespiau]

Here's a new spin of the series, restoring interrupt registers and DDI
translation tables when re-enabling power-wells.

v2:
  - Don't run the post-enable hook when the power well is already enabled
  - Put the DDI patch with the rest of the serise

-- 
Damien


Damien Lespiau (6):
  drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
  drm/i915/skl: Introduce enable_requested and is_enabled in the power
    well code
  drm/i915/skl: Mirror what we do on HSW for the power well enable log
    message
  drm/i915/skl: Restore pipe interrupt registers after power well
    enabling
  drm/i915: Remove unused condition in hsw_power_well_post_enable()
  drm/i915/skl: Restore the DDI translation tables when enabling PW1

 drivers/gpu/drm/i915/i915_irq.c         | 19 +++++++++----
 drivers/gpu/drm/i915/intel_drv.h        |  3 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 50 ++++++++++++++++++++++++++++-----
 3 files changed, 59 insertions(+), 13 deletions(-)

-- 
1.8.3.1

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[PATCH 1/6] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

[Damien Lespiau]

While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         | 15 ++++++++++-----
 drivers/gpu/drm/i915/intel_drv.h        |  3 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 ++-
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9baecb7..d77a4b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3169,15 +3169,20 @@ static void gen8_irq_reset(struct drm_device *dev)
 	ibx_irq_reset(dev);
 }
 
-void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
+				     unsigned int pipe_mask)
 {
 	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
-			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
-	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
-			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
+	if (pipe_mask & 1 << PIPE_B)
+		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
+				  dev_priv->de_irq_mask[PIPE_B],
+				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
+	if (pipe_mask & 1 << PIPE_C)
+		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
+				  dev_priv->de_irq_mask[PIPE_C],
+				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ff79dca..c77128c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 }
 
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
-void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
+void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
+				     unsigned int pipe_mask);
 
 /* intel_crt.c */
 void intel_crt_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6d8e29a..35e0cb6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 
 	if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
-		gen8_irq_power_well_post_enable(dev_priv);
+		gen8_irq_power_well_post_enable(dev_priv,
+						1 << PIPE_C | 1 << PIPE_B);
 }
 
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
-- 
1.8.3.1

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[PATCH 2/6] drm/i915/skl: Introduce enable_requested and is_enabled in the power well code

[Damien Lespiau]

Just like what we do for HSW/BDW, having those variables makes it a bit
easier to parse the code.

Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 35e0cb6..8f34d38 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -294,7 +294,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 {
 	uint32_t tmp, fuse_status;
 	uint32_t req_mask, state_mask;
-	bool check_fuse_status = false;
+	bool is_enabled, enable_requested, check_fuse_status = false;
 
 	tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 	fuse_status = I915_READ(SKL_FUSE_STATUS);
@@ -325,15 +325,17 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 	}
 
 	req_mask = SKL_POWER_WELL_REQ(power_well->data);
+	enable_requested = tmp & req_mask;
 	state_mask = SKL_POWER_WELL_STATE(power_well->data);
+	is_enabled = tmp & state_mask;
 
 	if (enable) {
-		if (!(tmp & req_mask)) {
+		if (!enable_requested) {
 			I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 		}
 
-		if (!(tmp & state_mask)) {
+		if (!is_enabled) {
 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 				state_mask), 1))
 				DRM_ERROR("%s enable timeout\n",
@@ -341,7 +343,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 			check_fuse_status = true;
 		}
 	} else {
-		if (tmp & req_mask) {
+		if (enable_requested) {
 			I915_WRITE(HSW_PWR_WELL_DRIVER,	tmp & ~req_mask);
 			POSTING_READ(HSW_PWR_WELL_DRIVER);
 			DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
-- 
1.8.3.1

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[PATCH 3/6] drm/i915/skl: Mirror what we do on HSW for the power well enable log message

[Damien Lespiau]

Just to be more consistent with what we do on HSW.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8f34d38..46ffb25 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -332,10 +332,10 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 	if (enable) {
 		if (!enable_requested) {
 			I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
-			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 		}
 
 		if (!is_enabled) {
+			DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 			if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 				state_mask), 1))
 				DRM_ERROR("%s enable timeout\n",
-- 
1.8.3.1

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[PATCH 4/6] drm/i915/skl: Restore pipe interrupt registers after power well enabling

[Damien Lespiau]

The pipe interrupt registers are in the actual pipe power well, so we
need to restore them when re-enable the corresponding power well.

I've also copied what we do on HSW/BDW for VGA, even if the we haven't
enabled unclaimed registers just yet.

v2: Don't run skl_power_well_post_enable() if the power well is already
    enabled (Paulo)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c         |  4 ++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 31 +++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d77a4b6..92e1ee4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3175,6 +3175,10 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 
 	spin_lock_irq(&dev_priv->irq_lock);
+	if (pipe_mask & 1 << PIPE_A)
+		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
+				  dev_priv->de_irq_mask[PIPE_A],
+				  ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
 	if (pipe_mask & 1 << PIPE_B)
 		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
 				  dev_priv->de_irq_mask[PIPE_B],
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 46ffb25..87a449c 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -199,6 +199,34 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 						1 << PIPE_C | 1 << PIPE_B);
 }
 
+static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
+				       struct i915_power_well *power_well)
+{
+	struct drm_device *dev = dev_priv->dev;
+
+	/*
+	 * After we re-enable the power well, if we touch VGA register 0x3d5
+	 * we'll get unclaimed register interrupts. This stops after we write
+	 * anything to the VGA MSR register. The vgacon module uses this
+	 * register all the time, so if we unbind our driver and, as a
+	 * consequence, bind vgacon, we'll get stuck in an infinite loop at
+	 * console_unlock(). So make here we touch the VGA MSR register, making
+	 * sure vgacon can keep working normally without triggering interrupts
+	 * and error messages.
+	 */
+	if (power_well->data == SKL_DISP_PW_2) {
+		vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
+		outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
+		vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
+
+		gen8_irq_power_well_post_enable(dev_priv,
+						1 << PIPE_C | 1 << PIPE_B);
+	}
+
+	if (power_well->data == SKL_DISP_PW_1)
+		gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
+}
+
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 			       struct i915_power_well *power_well, bool enable)
 {
@@ -361,6 +389,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
 				DRM_ERROR("PG2 distributing status timeout\n");
 		}
 	}
+
+	if (enable && !is_enabled)
+		skl_power_well_post_enable(dev_priv, power_well);
 }
 
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
-- 
1.8.3.1

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[PATCH 5/6] drm/i915: Remove unused condition in hsw_power_well_post_enable()

[Damien Lespiau]

We don't use this function on gen9, no need for that test here.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 87a449c..8d3bad8 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -194,7 +194,7 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 	outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 
-	if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
+	if (IS_BROADWELL(dev))
 		gen8_irq_power_well_post_enable(dev_priv,
 						1 << PIPE_C | 1 << PIPE_B);
 }
-- 
1.8.3.1

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[PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1

[Damien Lespiau]

I was dumping the DDI translation tables to make sure my patch updating
the HDMI entry was doing the right thing when I noticed that the table
was showing reset values after DPMS.

And indeed, the DDI translation registers are in power well 1 on SKL,
and so we're losing their values when shutting down eDP.

Calling intel_prepare_ddi() on PW1 enabling re-programs the table.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8d3bad8..ec3675e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -223,8 +223,10 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 						1 << PIPE_C | 1 << PIPE_B);
 	}
 
-	if (power_well->data == SKL_DISP_PW_1)
+	if (power_well->data == SKL_DISP_PW_1) {
+		intel_prepare_ddi(dev);
 		gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
+	}
 }
 
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
-- 
1.8.3.1

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Re: [PATCH 0/6] SKL post-enable power well hook (v2)

[Paulo Zanoni]

2015-03-06 15:50 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> Here's a new spin of the series, restoring interrupt registers and DDI
> translation tables when re-enabling power-wells.
>
> v2:
>   - Don't run the post-enable hook when the power well is already enabled
>   - Put the DDI patch with the rest of the serise

For everything: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
> --
> Damien
>
>
> Damien Lespiau (6):
>   drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
>   drm/i915/skl: Introduce enable_requested and is_enabled in the power
>     well code
>   drm/i915/skl: Mirror what we do on HSW for the power well enable log
>     message
>   drm/i915/skl: Restore pipe interrupt registers after power well
>     enabling
>   drm/i915: Remove unused condition in hsw_power_well_post_enable()
>   drm/i915/skl: Restore the DDI translation tables when enabling PW1
>
>  drivers/gpu/drm/i915/i915_irq.c         | 19 +++++++++----
>  drivers/gpu/drm/i915/intel_drv.h        |  3 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 50 ++++++++++++++++++++++++++++-----
>  3 files changed, 59 insertions(+), 13 deletions(-)
>
> --
> 1.8.3.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni
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Re: [PATCH 6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5908
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -13              275/275              262/275
ILK                                  307/307              307/307
SNB                 -1              284/284              283/284
IVB                                  375/375              375/375
BYT                                  294/294              294/294
HSW                                  385/385              385/385
BDW                 -1              314/314              313/314
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_exec_params_DR1-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_DR4-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_no-bsd      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-master      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-root      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_2-spare-fences      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-copy      PASS(2)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      PASS(4)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_bad-flink      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_flink-lifetime      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_race_flink_close      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_gtt_cpu_tlb      PASS(2)      NRUN(1)PASS(1)
*SNB  igt_gem_exec_params_rel-constants-invalid-rel-gen5      PASS(2)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(5)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH 1/6] drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

[Daniel Vetter]

On Fri, Mar 06, 2015 at 06:50:48PM +0000, Damien Lespiau wrote:
> While we only need to restore pipe B/C interrupt registers on BDW when
> enabling the power well, skylake a bit more flexible and we'll also need
> to restore the pipe A registers as it has its own power well that can be
> toggled.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c         | 15 ++++++++++-----
>  drivers/gpu/drm/i915/intel_drv.h        |  3 ++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 ++-
>  3 files changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9baecb7..d77a4b6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3169,15 +3169,20 @@ static void gen8_irq_reset(struct drm_device *dev)
>  	ibx_irq_reset(dev);
>  }
>  
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
> +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> +				     unsigned int pipe_mask)
>  {
>  	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
> -			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
> -	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
> -			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
> +	if (pipe_mask & 1 << PIPE_B)
> +		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
> +				  dev_priv->de_irq_mask[PIPE_B],
> +				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
> +	if (pipe_mask & 1 << PIPE_C)
> +		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
> +				  dev_priv->de_irq_mask[PIPE_C],
> +				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
>  	spin_unlock_irq(&dev_priv->irq_lock);

Since this now takes a pipe mask I really think we should eventually move
this as a call into the gen8+ crtc enable code ...
-Daniel

>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ff79dca..c77128c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
>  }
>  
>  int intel_get_crtc_scanline(struct intel_crtc *crtc);
> -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
> +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> +				     unsigned int pipe_mask);
>  
>  /* intel_crt.c */
>  void intel_crt_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6d8e29a..35e0cb6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
>  	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
>  
>  	if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
> -		gen8_irq_power_well_post_enable(dev_priv);
> +		gen8_irq_power_well_post_enable(dev_priv,
> +						1 << PIPE_C | 1 << PIPE_B);
>  }
>  
>  static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 0/6] SKL post-enable power well hook (v2)

[Daniel Vetter]

On Fri, Mar 06, 2015 at 04:28:16PM -0300, Paulo Zanoni wrote:
> 2015-03-06 15:50 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> > Here's a new spin of the series, restoring interrupt registers and DDI
> > translation tables when re-enabling power-wells.
> >
> > v2:
> >   - Don't run the post-enable hook when the power well is already enabled
> >   - Put the DDI patch with the rest of the serise
> 
> For everything: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

All applied, thanks.
-Daniel

> 
> >
> > --
> > Damien
> >
> >
> > Damien Lespiau (6):
> >   drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
> >   drm/i915/skl: Introduce enable_requested and is_enabled in the power
> >     well code
> >   drm/i915/skl: Mirror what we do on HSW for the power well enable log
> >     message
> >   drm/i915/skl: Restore pipe interrupt registers after power well
> >     enabling
> >   drm/i915: Remove unused condition in hsw_power_well_post_enable()
> >   drm/i915/skl: Restore the DDI translation tables when enabling PW1
> >
> >  drivers/gpu/drm/i915/i915_irq.c         | 19 +++++++++----
> >  drivers/gpu/drm/i915/intel_drv.h        |  3 +-
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 50 ++++++++++++++++++++++++++++-----
> >  3 files changed, 59 insertions(+), 13 deletions(-)
> >
> > --
> > 1.8.3.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
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