From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor Date: 07 Apr 2015 08:41:11 -0700 Message-ID: References: <1428411693-27889-1-git-send-email-arun.siluvery@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 18B716E210 for ; Tue, 7 Apr 2015 08:41:15 -0700 (PDT) In-Reply-To: <1428411693-27889-1-git-send-email-arun.siluvery@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, ethan.gao@intel.com, intel-gfx@lists.freedesktop.org, arun.siluvery@linux.intel.com List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBJbnRlbCBHcmFwaGljcyBRQSBQUlRTIChQYXRjaCBSZWdyZXNzaW9uIFRlc3Qg U3lzdGVtIENvbnRhY3Q6IHNodWFuZy5oZUBpbnRlbC5jb20pClRhc2sgaWQ6IDYxMzkKLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLVN1bW1hcnktLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tClBsYXRmb3JtICAgICAgICAgIERlbHRhICAgICAgICAgIGRybS1p bnRlbC1uaWdodGx5ICAgICAgICAgIFNlcmllcyBBcHBsaWVkClBOViAgICAgICAgICAgICAgICAg LTUgICAgICAgICAgICAgIDI3Mi8yNzIgICAgICAgICAgICAgIDI2Ny8yNzIKSUxLICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIDMwMi8zMDIgICAgICAgICAgICAgIDMwMi8zMDIKU05C ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDMwMy8zMDMgICAgICAgICAgICAgIDMw My8zMDMKSVZCICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDMzOC8zMzggICAgICAg ICAgICAgIDMzOC8zMzgKQllUICAgICAgICAgICAgICAgICAtMSAgICAgICAgICAgICAgMjg3LzI4 NyAgICAgICAgICAgICAgMjg2LzI4NwpIU1cgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgMzYxLzM2MSAgICAgICAgICAgICAgMzYxLzM2MQpCRFcgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgMzA4LzMwOCAgICAgICAgICAgICAgMzA4LzMwOAotLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tRGV0YWlsZWQtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tClBsYXRmb3JtICBUZXN0ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBk cm0taW50ZWwtbmlnaHRseSAgICAgICAgICBTZXJpZXMgQXBwbGllZAoqUE5WICBpZ3RAZ2VtX2Zl bmNlX3RocmFzaEBiby13cml0ZS12ZXJpZnktdGhyZWFkZWQtbm9uZSAgICAgIFBBU1MoNSkgICAg ICBGQUlMKDEpUEFTUygxKQoqUE5WICBpZ3RAZ2VtX2ZlbmNlX3RocmFzaEBiby13cml0ZS12ZXJp ZnkteCAgICAgIFBBU1MoMikgICAgICBGQUlMKDEpUEFTUygxKQoqUE5WICBpZ3RAZ2VtX2ZlbmNl X3RocmFzaEBiby13cml0ZS12ZXJpZnkteSAgICAgIFBBU1MoMykgICAgICBGQUlMKDEpUEFTUygx KQogUE5WICBpZ3RAZ2VtX3RpbGVkX3ByZWFkX3B3cml0ZSAgICAgIEZBSUwoMylQQVNTKDEyKSAg ICAgIEZBSUwoMSlQQVNTKDEpCiBQTlYgIGlndEBnZW1fdXNlcnB0cl9ibGl0c0Bjb2hlcmVuY3kt c3luYyAgICAgIENSQVNIKDUpUEFTUyg5KSAgICAgIENSQVNIKDEpUEFTUygxKQoqQllUICBpZ3RA Z2VtX2V4ZWNfYmFkX2RvbWFpbnNAY29uZmxpY3Rpbmctd3JpdGUtZG9tYWluICAgICAgUEFTUygy MSkgICAgICBGQUlMKDEpUEFTUygxKQpOb3RlOiBZb3UgbmVlZCB0byBwYXkgbW9yZSBhdHRlbnRp b24gdG8gbGluZSBzdGFydCB3aXRoICcqJwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5m cmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2ludGVsLWdmeAo=