* [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor
@ 2015-04-07 13:01 Arun Siluvery
2015-04-07 14:03 ` Mika Kuoppala
2015-04-07 15:41 ` shuang.he
0 siblings, 2 replies; 4+ messages in thread
From: Arun Siluvery @ 2015-04-07 13:01 UTC (permalink / raw)
To: intel-gfx
According to Spec this is a reserved bit for Gen9+ and should not be set.
Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c3834fc..cfc73ea 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -265,7 +265,8 @@ static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
desc = GEN8_CTX_VALID;
desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
- desc |= GEN8_CTX_L3LLC_COHERENT;
+ if (IS_GEN8(ctx_obj->base.dev))
+ desc |= GEN8_CTX_L3LLC_COHERENT;
desc |= GEN8_CTX_PRIVILEGE;
desc |= lrca;
desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
--
2.3.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor
2015-04-07 13:01 [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor Arun Siluvery
@ 2015-04-07 14:03 ` Mika Kuoppala
2015-04-07 16:35 ` Daniel Vetter
2015-04-07 15:41 ` shuang.he
1 sibling, 1 reply; 4+ messages in thread
From: Mika Kuoppala @ 2015-04-07 14:03 UTC (permalink / raw)
To: Arun Siluvery, intel-gfx
Arun Siluvery <arun.siluvery@linux.intel.com> writes:
> According to Spec this is a reserved bit for Gen9+ and should not be set.
>
> Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 1c3834fc..cfc73ea 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -265,7 +265,8 @@ static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
>
> desc = GEN8_CTX_VALID;
> desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
> - desc |= GEN8_CTX_L3LLC_COHERENT;
> + if (IS_GEN8(ctx_obj->base.dev))
> + desc |= GEN8_CTX_L3LLC_COHERENT;
> desc |= GEN8_CTX_PRIVILEGE;
> desc |= lrca;
> desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
> --
> 2.3.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor
2015-04-07 14:03 ` Mika Kuoppala
@ 2015-04-07 16:35 ` Daniel Vetter
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2015-04-07 16:35 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
On Tue, Apr 07, 2015 at 05:03:32PM +0300, Mika Kuoppala wrote:
> Arun Siluvery <arun.siluvery@linux.intel.com> writes:
>
> > According to Spec this is a reserved bit for Gen9+ and should not be set.
> >
> > Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> > ---
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor
2015-04-07 13:01 [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor Arun Siluvery
2015-04-07 14:03 ` Mika Kuoppala
@ 2015-04-07 15:41 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2015-04-07 15:41 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, arun.siluvery
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6139
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -5 272/272 267/272
ILK 302/302 302/302
SNB 303/303 303/303
IVB 338/338 338/338
BYT -1 287/287 286/287
HSW 361/361 361/361
BDW 308/308 308/308
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt@gem_fence_thrash@bo-write-verify-threaded-none PASS(5) FAIL(1)PASS(1)
*PNV igt@gem_fence_thrash@bo-write-verify-x PASS(2) FAIL(1)PASS(1)
*PNV igt@gem_fence_thrash@bo-write-verify-y PASS(3) FAIL(1)PASS(1)
PNV igt@gem_tiled_pread_pwrite FAIL(3)PASS(12) FAIL(1)PASS(1)
PNV igt@gem_userptr_blits@coherency-sync CRASH(5)PASS(9) CRASH(1)PASS(1)
*BYT igt@gem_exec_bad_domains@conflicting-write-domain PASS(21) FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2015-04-07 13:01 [PATCH] drm/i915: Do not set L3-LLC Coherency bit in ctx descriptor Arun Siluvery
2015-04-07 14:03 ` Mika Kuoppala
2015-04-07 16:35 ` Daniel Vetter
2015-04-07 15:41 ` shuang.he
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