Re: [PATCH] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

Clint Taylor
2015-04-09T21:04:10Z

On 04/09/2015 01:20 PM, Ville Syrjälä wrote:
> On Thu, Apr 09, 2015 at 10:17:05AM -0700, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> Latest version of the "CHV DPIO programming notes" no longer requires writes
>> to TX DW 11 to fix a +2UI interpair skew issue. The current code from
>> April 2014 was actually causing additional skew issues between all
>> TMDS pairs.
>>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_hdmi.c | 5 -----
>> 1 file changed, 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 26222e6..3cef326 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1515,11 +1515,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>>
>> /* Program Tx latency optimal setting */
>> for (i = 0; i < 4; i++) {
>> - /* Set the latency optimal bit */
>> - data = (i == 1) ? 0x0 : 0x6;
>> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
>> - data << DPIO_FRC_LATENCY_SHFIT);
>> -
>
> On a huch I went and tried this same treatment on intel_dp.c and it
> fixes the remaining link training issues [1] I've been seeing \o/
> I still need to try with the other DP display that was having these
> problems, but that'll have to wait until tomorrow.
>
> So please respin this with the same change made to intel_dp.c (someone
> should really eliminate the code duplication we have going on there), and
> assuming my test with the other display goes as well I can then post
> some DPIO lane power gating patches which I've been holding back because
> they made the problem worse.
>

v2 respin has been sent. You saved me lots of time testing the same
change on DP. I will probably still put it on a scope to confirm the
improvement.

I didn't take on the hint of fixing the code duplication.

-Clint

> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-February/059877.html
>
>
>> /* Set the upar bit */
>> data = (i == 1) ? 0x0 : 0x1;
>> vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
>> --
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx