* [PATCH] drm/i915: Add the ddi get cdclk code for BXT.
@ 2015-06-10 20:18 Bob Paauwe
2015-06-14 11:45 ` shuang.he
2015-06-15 8:59 ` Ville Syrjälä
0 siblings, 2 replies; 9+ messages in thread
From: Bob Paauwe @ 2015-06-10 20:18 UTC (permalink / raw)
To: intel-gfx
The registers and process differ from other platforms.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c38c297..41464a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
return 24000;
}
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ uint32_t cdctl = I915_READ(CDCLK_CTL);
+ uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+
+ switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
+ return 576000;
+ else /* PLL freq = 1248MHz */
+ return 624000;
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ return 384000;
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ return 288000;
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ return 144000;
+ }
+
+ /* error case, assume higer PLL freq. */
+ return 624000;
+}
+
static int broadwell_get_display_clock_speed(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
if (IS_SKYLAKE(dev))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
+ else if (IS_BROXTON(dev))
+ dev_priv->display.get_display_clock_speed =
+ broxton_get_display_clock_speed;
else if (IS_BROADWELL(dev))
dev_priv->display.get_display_clock_speed =
broadwell_get_display_clock_speed;
--
2.1.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT.
2015-06-10 20:18 [PATCH] drm/i915: Add the ddi get cdclk code for BXT Bob Paauwe
@ 2015-06-14 11:45 ` shuang.he
2015-06-15 8:59 ` Ville Syrjälä
1 sibling, 0 replies; 9+ messages in thread
From: shuang.he @ 2015-06-14 11:45 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, bob.j.paauwe
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6564
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT 287/287 287/287
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT.
2015-06-10 20:18 [PATCH] drm/i915: Add the ddi get cdclk code for BXT Bob Paauwe
2015-06-14 11:45 ` shuang.he
@ 2015-06-15 8:59 ` Ville Syrjälä
2015-06-17 14:43 ` Imre Deak
1 sibling, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2015-06-15 8:59 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> The registers and process differ from other platforms.
>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c38c297..41464a5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> return 24000;
> }
>
> +static int broxton_get_display_clock_speed(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + uint32_t cdctl = I915_READ(CDCLK_CTL);
> + uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> +
You should return 19.2MHz if the DE PLL isn't enabled.
> + switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> + return 576000;
> + else /* PLL freq = 1248MHz */
> + return 624000;
> + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + return 384000;
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + return 288000;
> + case BXT_CDCLK_CD2X_DIV_SEL_4:
> + return 144000;
> + }
> +
> + /* error case, assume higer PLL freq. */
> + return 624000;
> +}
> +
> static int broadwell_get_display_clock_speed(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
> if (IS_SKYLAKE(dev))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> + else if (IS_BROXTON(dev))
> + dev_priv->display.get_display_clock_speed =
> + broxton_get_display_clock_speed;
> else if (IS_BROADWELL(dev))
> dev_priv->display.get_display_clock_speed =
> broadwell_get_display_clock_speed;
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT.
2015-06-15 8:59 ` Ville Syrjälä
@ 2015-06-17 14:43 ` Imre Deak
2015-06-18 16:38 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2) Matt Roper
0 siblings, 1 reply; 9+ messages in thread
From: Imre Deak @ 2015-06-17 14:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On ma, 2015-06-15 at 11:59 +0300, Ville Syrjälä wrote:
> On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> > The registers and process differ from other platforms.
> >
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c38c297..41464a5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> > return 24000;
> > }
> >
> > +static int broxton_get_display_clock_speed(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + uint32_t cdctl = I915_READ(CDCLK_CTL);
> > + uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> > +
>
> You should return 19.2MHz if the DE PLL isn't enabled.
Agreed with Ville, Bob could you resend the patch with this fixed?
> > + switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> > + case BXT_CDCLK_CD2X_DIV_SEL_1:
> > + if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> > + return 576000;
> > + else /* PLL freq = 1248MHz */
> > + return 624000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > + return 384000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_2:
> > + return 288000;
> > + case BXT_CDCLK_CD2X_DIV_SEL_4:
> > + return 144000;
> > + }
> > +
> > + /* error case, assume higer PLL freq. */
> > + return 624000;
> > +}
> > +
> > static int broadwell_get_display_clock_speed(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
> > if (IS_SKYLAKE(dev))
> > dev_priv->display.get_display_clock_speed =
> > skylake_get_display_clock_speed;
> > + else if (IS_BROXTON(dev))
> > + dev_priv->display.get_display_clock_speed =
> > + broxton_get_display_clock_speed;
> > else if (IS_BROADWELL(dev))
> > dev_priv->display.get_display_clock_speed =
> > broadwell_get_display_clock_speed;
> > --
> > 2.1.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2)
2015-06-17 14:43 ` Imre Deak
@ 2015-06-18 16:38 ` Matt Roper
2015-06-22 13:26 ` Ville Syrjälä
2015-06-23 21:14 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3) Bob Paauwe
0 siblings, 2 replies; 9+ messages in thread
From: Matt Roper @ 2015-06-18 16:38 UTC (permalink / raw)
To: intel-gfx
From: Bob Paauwe <bob.j.paauwe@intel.com>
The registers and process differ from other platforms.
v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ee7dbc..294c4e4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6689,6 +6689,34 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
return 24000;
}
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ uint32_t cdctl = I915_READ(CDCLK_CTL);
+ uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+ uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
+
+ if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
+ return 19200;
+
+ switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
+ return 576000;
+ else /* PLL freq = 1248MHz */
+ return 624000;
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ return 384000;
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ return 288000;
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ return 144000;
+ }
+
+ /* error case, assume higer PLL freq. */
+ return 624000;
+}
+
static int broadwell_get_display_clock_speed(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -14715,6 +14743,9 @@ static void intel_init_display(struct drm_device *dev)
if (IS_SKYLAKE(dev))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
+ else if (IS_BROXTON(dev))
+ dev_priv->display.get_display_clock_speed =
+ broxton_get_display_clock_speed;
else if (IS_BROADWELL(dev))
dev_priv->display.get_display_clock_speed =
broadwell_get_display_clock_speed;
--
1.8.5.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2)
2015-06-18 16:38 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2) Matt Roper
@ 2015-06-22 13:26 ` Ville Syrjälä
2015-06-23 21:14 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3) Bob Paauwe
1 sibling, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2015-06-22 13:26 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Jun 18, 2015 at 09:38:05AM -0700, Matt Roper wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> The registers and process differ from other platforms.
>
> v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3ee7dbc..294c4e4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6689,6 +6689,34 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> return 24000;
> }
>
> +static int broxton_get_display_clock_speed(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + uint32_t cdctl = I915_READ(CDCLK_CTL);
> + uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> + uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
> +
> + if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
> + return 19200;
> +
> + switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> + return 576000;
> + else /* PLL freq = 1248MHz */
> + return 624000;
> + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + return 384000;
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + return 288000;
> + case BXT_CDCLK_CD2X_DIV_SEL_4:
> + return 144000;
> + }
I'd try write this in a way that makes less assumptions about the
hardware state, so that it would also catch misprogramming.
Maybe something like this:
freq = 19200 * (pll_freq & BXT_DE_PLL_RATIO_MASK) / 2;
switch (...) {
case BXT_CDCLK_CD2X_DIV_SEL_1:
return freq;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
return freq * 3 / 2;
...
> +
> + /* error case, assume higer PLL freq. */
> + return 624000;
> +}
> +
> static int broadwell_get_display_clock_speed(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -14715,6 +14743,9 @@ static void intel_init_display(struct drm_device *dev)
> if (IS_SKYLAKE(dev))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> + else if (IS_BROXTON(dev))
> + dev_priv->display.get_display_clock_speed =
> + broxton_get_display_clock_speed;
> else if (IS_BROADWELL(dev))
> dev_priv->display.get_display_clock_speed =
> broadwell_get_display_clock_speed;
> --
> 1.8.5.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)
2015-06-18 16:38 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2) Matt Roper
2015-06-22 13:26 ` Ville Syrjälä
@ 2015-06-23 21:14 ` Bob Paauwe
2015-06-24 12:49 ` Ville Syrjälä
1 sibling, 1 reply; 9+ messages in thread
From: Bob Paauwe @ 2015-06-23 21:14 UTC (permalink / raw)
To: intel-gfx
The registers and process differ from other platforms. If the hardware
was programmed incorrectly, this will return invalid cdclk values, which
should then cause reprogramming of the hardware.
v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
v3: Make less assumptions about the hardware state (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c38c297..201826e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6687,6 +6687,34 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
return 24000;
}
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ uint32_t cdctl = I915_READ(CDCLK_CTL);
+ uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+ uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
+ int cdclk;
+
+ if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
+ return 19200;
+
+ cdclk = 19200 * pll_ratio / 2;
+
+ switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+ case BXT_CDCLK_CD2X_DIV_SEL_1:
+ return cdclk; /* 576MHz or 624MHz */
+ case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ return cdclk * 2 / 3; /* 384MHz */
+ case BXT_CDCLK_CD2X_DIV_SEL_2:
+ return cdclk / 2; /* 288MHz */
+ case BXT_CDCLK_CD2X_DIV_SEL_4:
+ return cdclk / 4; /* 144MHz */
+ }
+
+ /* error case, do as if DE PLL isn't enabled */
+ return 19200;
+}
+
static int broadwell_get_display_clock_speed(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -14649,6 +14677,9 @@ static void intel_init_display(struct drm_device *dev)
if (IS_SKYLAKE(dev))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
+ else if (IS_BROXTON(dev))
+ dev_priv->display.get_display_clock_speed =
+ broxton_get_display_clock_speed;
else if (IS_BROADWELL(dev))
dev_priv->display.get_display_clock_speed =
broadwell_get_display_clock_speed;
--
2.1.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)
2015-06-23 21:14 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3) Bob Paauwe
@ 2015-06-24 12:49 ` Ville Syrjälä
2015-06-24 13:11 ` Daniel Vetter
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2015-06-24 12:49 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
> The registers and process differ from other platforms. If the hardware
> was programmed incorrectly, this will return invalid cdclk values, which
> should then cause reprogramming of the hardware.
>
> v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
> v3: Make less assumptions about the hardware state (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c38c297..201826e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6687,6 +6687,34 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> return 24000;
> }
>
> +static int broxton_get_display_clock_speed(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + uint32_t cdctl = I915_READ(CDCLK_CTL);
> + uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> + uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
> + int cdclk;
> +
> + if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
> + return 19200;
> +
> + cdclk = 19200 * pll_ratio / 2;
> +
> + switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> + case BXT_CDCLK_CD2X_DIV_SEL_1:
> + return cdclk; /* 576MHz or 624MHz */
> + case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + return cdclk * 2 / 3; /* 384MHz */
> + case BXT_CDCLK_CD2X_DIV_SEL_2:
> + return cdclk / 2; /* 288MHz */
> + case BXT_CDCLK_CD2X_DIV_SEL_4:
> + return cdclk / 4; /* 144MHz */
> + }
> +
> + /* error case, do as if DE PLL isn't enabled */
> + return 19200;
> +}
> +
> static int broadwell_get_display_clock_speed(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -14649,6 +14677,9 @@ static void intel_init_display(struct drm_device *dev)
> if (IS_SKYLAKE(dev))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> + else if (IS_BROXTON(dev))
> + dev_priv->display.get_display_clock_speed =
> + broxton_get_display_clock_speed;
> else if (IS_BROADWELL(dev))
> dev_priv->display.get_display_clock_speed =
> broadwell_get_display_clock_speed;
> --
> 2.1.0
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3)
2015-06-24 12:49 ` Ville Syrjälä
@ 2015-06-24 13:11 ` Daniel Vetter
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2015-06-24 13:11 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jun 24, 2015 at 03:49:22PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 23, 2015 at 02:14:26PM -0700, Bob Paauwe wrote:
> > The registers and process differ from other platforms. If the hardware
> > was programmed incorrectly, this will return invalid cdclk values, which
> > should then cause reprogramming of the hardware.
> >
> > v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
> > v3: Make less assumptions about the hardware state (Ville)
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-06-24 13:09 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-06-10 20:18 [PATCH] drm/i915: Add the ddi get cdclk code for BXT Bob Paauwe
2015-06-14 11:45 ` shuang.he
2015-06-15 8:59 ` Ville Syrjälä
2015-06-17 14:43 ` Imre Deak
2015-06-18 16:38 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v2) Matt Roper
2015-06-22 13:26 ` Ville Syrjälä
2015-06-23 21:14 ` [PATCH] drm/i915: Add the ddi get cdclk code for BXT (v3) Bob Paauwe
2015-06-24 12:49 ` Ville Syrjälä
2015-06-24 13:11 ` Daniel Vetter
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