[PATCH 0/2] Fix min dbuf, 90/270 wm calcs

[PATCH 0/2] Fix min dbuf, 90/270 wm calcs

[Chandra Konduru]

This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270, 
swaps source width and height.

Chandra Konduru (2):
  drm/i915: Allocate min dbuf blocks per bspec
  drm/i915: In DBUF/WM calcs for 90/270, swap w & h

 drivers/gpu/drm/i915/intel_pm.c |   71 +++++++++++++++++++++++++++++++++++----
 1 file changed, 65 insertions(+), 6 deletions(-)

-- 
1.7.9.5

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[PATCH v4] drm/i915: Add support for SKL background color

[Chandra Konduru]

This patch adds support for Skylake display pipe background color.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 Documentation/DocBook/drm.tmpl       |   10 ++++-
 drivers/gpu/drm/i915/i915_reg.h      |   10 +++++
 drivers/gpu/drm/i915/intel_display.c |   73 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |    2 +
 include/drm/drm_crtc.h               |    3 ++
 5 files changed, 97 insertions(+), 1 deletion(-)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7d03a74..1f6f4f0 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2663,7 +2663,7 @@ void intel_crt_init(struct drm_device *dev)
 	<td valign="top" >TBD</td>
 	</tr>
 	<tr>
-	<td rowspan="21" valign="top" >i915</td>
+	<td rowspan="22" valign="top" >i915</td>
 	<td rowspan="2" valign="top" >Generic</td>
 	<td valign="top" >"Broadcast RGB"</td>
 	<td valign="top" >ENUM</td>
@@ -2687,6 +2687,14 @@ void intel_crt_init(struct drm_device *dev)
 	<td valign="top" >TBD</td>
 	</tr>
 	<tr>
+	<td rowspan="1" valign="top" >CRTC</td>
+	<td valign="top" >“background_color”</td>
+	<td valign="top" >Range</td>
+	<td valign="top" >Min=0, Max=0xFFFFFF</td>
+	<td valign="top" >CRTC</td>
+	<td valign="top" >Background color in 16bpc BGR (B-MSB, R-LSB)</td>
+	</tr>
+	<tr>
 	<td rowspan="17" valign="top" >SDVO-TV</td>
 	<td valign="top" >“mode”</td>
 	<td valign="top" >ENUM</td>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84b37d7..795b53f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6579,6 +6579,16 @@ enum kdiv {
 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
+/* Skylake pipe bottom color */
+#define _PIPE_BOTTOM_COLOR_A        0x70034
+#define _PIPE_BOTTOM_COLOR_B        0x71034
+#define _PIPE_BOTTOM_COLOR_C        0x72034
+#define PIPE_BOTTOM_GAMMA_ENABLE   (1 << 31)
+#define PIPE_BOTTOM_CSC_ENABLE     (1 << 30)
+#define PIPE_BOTTOM_COLOR_MASK     0x3FFFFFFF
+#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \
+	_PIPE_BOTTOM_COLOR_B, _PIPE_BOTTOM_COLOR_C)
+
 /* VLV MIPI registers */
 
 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d162dca..d4b7c0c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6951,6 +6951,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
 	uint16_t coeff = 0x7800; /* 1.0 */
+	uint32_t color;
 
 	/*
 	 * TODO: Check what kind of values actually come out of the pipe
@@ -6999,6 +7000,14 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
 
 		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
 	}
+
+	/* set csc for bottom color */
+	if (INTEL_INFO(dev)->gen >= 9) {
+		color = I915_READ(PIPE_BOTTOM_COLOR(pipe));
+		color |= PIPE_BOTTOM_CSC_ENABLE;
+		I915_WRITE(PIPE_BOTTOM_COLOR(pipe), color);
+		intel_crtc->background_color |= PIPE_BOTTOM_CSC_ENABLE;
+	}
 }
 
 static void haswell_set_pipeconf(struct drm_crtc *crtc)
@@ -8568,6 +8577,9 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 {
 	int end = (start + size > 256) ? 256 : start + size, i;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t color;
 
 	for (i = start; i < end; i++) {
 		intel_crtc->lut_r[i] = red[i] >> 8;
@@ -8576,6 +8588,14 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 	}
 
 	intel_crtc_load_lut(crtc);
+
+	if (INTEL_INFO(dev)->gen >= 9) {
+		/* set gamma for bottom color */
+		color = I915_READ(PIPE_BOTTOM_COLOR(intel_crtc->pipe));
+		color |= PIPE_BOTTOM_GAMMA_ENABLE;
+		I915_WRITE(PIPE_BOTTOM_COLOR(intel_crtc->pipe), color);
+		intel_crtc->background_color |= PIPE_BOTTOM_GAMMA_ENABLE;
+	}
 }
 
 /* VESA 640x480x72Hz mode to set on the pipe */
@@ -9350,6 +9370,12 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
 		kfree(work);
 	}
 
+	if (dev->mode_config.background_color_property) {
+		drm_property_destroy(crtc->dev,
+			dev->mode_config.background_color_property);
+		dev->mode_config.background_color_property = NULL;
+	}
+
 	drm_crtc_cleanup(crtc);
 
 	kfree(intel_crtc);
@@ -10131,6 +10157,33 @@ out_hang:
 	return ret;
 }
 
+static int intel_crtc_set_property(struct drm_crtc *crtc,
+	struct drm_property *property, uint64_t val)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int i;
+
+	if (INTEL_INFO(dev)->gen >= 9) {
+		if (property == dev->mode_config.background_color_property) {
+			uint64_t bottom;
+			bottom = intel_crtc->background_color & ~PIPE_BOTTOM_COLOR_MASK;
+
+			/* BGR 16bpc ==> RGB 10bpc */
+			for (i = 0; i < 3; i++)
+				bottom |=
+					((((val >> (i*16)) & 0xFFFF) * 0x3FF/0xFFFF) << ((2-i)*10));
+
+			I915_WRITE(PIPE_BOTTOM_COLOR(intel_crtc->pipe), (uint32_t) bottom);
+			intel_crtc->background_color = (uint32_t) bottom;
+		}
+		return 0;
+	}
+	return -EINVAL;
+}
+
+
 static struct drm_crtc_helper_funcs intel_helper_funcs = {
 	.mode_set_base_atomic = intel_pipe_set_base_atomic,
 	.load_lut = intel_crtc_load_lut,
@@ -11258,6 +11311,11 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 	if (dev_priv->display.modeset_global_resources)
 		dev_priv->display.modeset_global_resources(dev);
 
+	/* Set background color */
+	if (INTEL_INFO(dev)->gen >= 9)
+		I915_WRITE(PIPE_BOTTOM_COLOR(to_intel_crtc(crtc)->pipe),
+			to_intel_crtc(crtc)->background_color);
+
 	/* Set up the DPLL and any encoders state that needs to adjust or depend
 	 * on the DPLL.
 	 */
@@ -11760,6 +11818,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
 	.set_config = intel_crtc_set_config,
 	.destroy = intel_crtc_destroy,
 	.page_flip = intel_crtc_page_flip,
+	.set_property = intel_crtc_set_property,
 };
 
 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -12212,6 +12271,20 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 
 	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
+
+	/* background color = 24 bit : MSB BGR 8bpc LSB */
+	intel_crtc->background_color = 0;
+	if (INTEL_INFO(dev)->gen >= 9 &&
+		!dev->mode_config.background_color_property)
+		dev->mode_config.background_color_property =
+			drm_property_create_range(dev, 0, "background_color", 0,
+				0xFFFFFFFFFFFF);
+
+	if (dev->mode_config.background_color_property)
+		drm_object_attach_property(&intel_crtc->base.base,
+			dev->mode_config.background_color_property,
+			intel_crtc->background_color);
+
 	return;
 
 fail:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c2830d8..0185dbe 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -445,6 +445,8 @@ struct intel_crtc {
 
 	int scanline_offset;
 	struct intel_mmio_flip mmio_flip;
+
+	uint32_t background_color;
 };
 
 struct intel_plane_wm_parameters {
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 31344bf..27bcd01 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -827,6 +827,9 @@ struct drm_mode_config {
 	struct drm_property *plane_type_property;
 	struct drm_property *rotation_property;
 
+	/* crtc properties */
+	struct drm_property *background_color_property;
+
 	/* DVI-I properties */
 	struct drm_property *dvi_i_subconnector_property;
 	struct drm_property *dvi_i_select_subconnector_property;
-- 
1.7.9.5

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[PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec

[Chandra Konduru]

Properly allocate min blocks per hw requirements.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |   39 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..ea3e435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2679,6 +2679,41 @@ skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
 	return total_data_rate;
 }
 
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+	uint16_t min_alloc;
+
+	/* For packed formats, no y-plane, return 0 */
+	if (y_plane && !p->y_bytes_per_pixel)
+		return 0;
+
+
+	if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+	    p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+		uint32_t min_scanlines = 8;
+		uint8_t bytes_per_pixel =
+			y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+		switch (bytes_per_pixel) {
+		case 1:
+			min_scanlines = 32;
+			break;
+		case 2:
+			min_scanlines = 16;
+			break;
+		case 8:
+			WARN(1, "Unsupported pixel depth for rotation");
+		}
+		min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2) *
+			bytes_per_pixel), 512) * min_scanlines/4 + 3;
+	} else {
+		min_alloc = 8;
+	}
+
+	return min_alloc;
+}
+
 static void
 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 		      const struct intel_wm_config *config,
@@ -2719,9 +2754,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 		if (!p->enabled)
 			continue;
 
-		minimum[plane] = 8;
+		minimum[plane] = skl_dbuf_min_alloc(p, 0);    /* uv-plane/packed */
 		alloc_size -= minimum[plane];
-		y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+		y_minimum[plane] = skl_dbuf_min_alloc(p, 1);  /* y-plane */
 		alloc_size -= y_minimum[plane];
 	}
 
-- 
1.7.9.5

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[PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Chandra Konduru]

This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |   32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ea3e435..767313b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 	enum pipe pipe = intel_crtc->pipe;
 	struct drm_plane *plane;
 	struct drm_framebuffer *fb;
+	struct intel_plane_state *plane_state;
+	int src_w, src_h;
 	int i = 1; /* Index for sprite planes start */
 
 	p->active = intel_crtc->active;
@@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
 
 		fb = crtc->primary->state->fb;
+		plane_state = to_intel_plane_state(crtc->primary->state);
 		/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
 		if (fb) {
 			p->plane[0].enabled = true;
@@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 			p->plane[0].y_bytes_per_pixel = 0;
 			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
 		}
-		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
-		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+		if (drm_rect_width(&plane_state->src)) {
+			src_w = drm_rect_width(&plane_state->src) >> 16;
+			src_h = drm_rect_height(&plane_state->src) >> 16;
+		} else {
+			src_w = intel_crtc->config->pipe_src_w;
+			src_h = intel_crtc->config->pipe_src_h;
+		}
+
+		if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+			p->plane[0].horiz_pixels = src_h;
+			p->plane[0].vert_pixels = src_w;
+		} else {
+			p->plane[0].horiz_pixels = src_w;
+			p->plane[0].vert_pixels = src_h;
+		}
 		p->plane[0].rotation = crtc->primary->state->rotation;
 
 		fb = crtc->cursor->state->fb;
@@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	intel_plane->wm.enabled = enabled;
 	intel_plane->wm.scaled = scaled;
-	intel_plane->wm.horiz_pixels = sprite_width;
-	intel_plane->wm.vert_pixels = sprite_height;
+
+	if (intel_rotation_90_or_270(plane->state->rotation)) {
+		intel_plane->wm.horiz_pixels = sprite_height;
+		intel_plane->wm.vert_pixels = sprite_width;
+	} else {
+		intel_plane->wm.horiz_pixels = sprite_width;
+		intel_plane->wm.vert_pixels = sprite_height;
+	}
+
 	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
 
 	/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
-- 
1.7.9.5

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Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6564
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  284/284              284/284
HSW                                  380/380              380/380
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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[PATCH 0/2] Fix min dbuf, 90/270 wm calcs

[Chandra Konduru]

Resending with correct patches.

This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270, 
swaps source width and height.

Chandra Konduru (2):
  drm/i915: Allocate min dbuf blocks per bspec
  drm/i915: In DBUF/WM calcs for 90/270, swap w & h

 drivers/gpu/drm/i915/intel_pm.c |   71 +++++++++++++++++++++++++++++++++++----
 1 file changed, 65 insertions(+), 6 deletions(-)

-- 
1.7.9.5

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[PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Chandra Konduru]

This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |   32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ea3e435..767313b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 	enum pipe pipe = intel_crtc->pipe;
 	struct drm_plane *plane;
 	struct drm_framebuffer *fb;
+	struct intel_plane_state *plane_state;
+	int src_w, src_h;
 	int i = 1; /* Index for sprite planes start */
 
 	p->active = intel_crtc->active;
@@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
 
 		fb = crtc->primary->state->fb;
+		plane_state = to_intel_plane_state(crtc->primary->state);
 		/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
 		if (fb) {
 			p->plane[0].enabled = true;
@@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
 			p->plane[0].y_bytes_per_pixel = 0;
 			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
 		}
-		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
-		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+		if (drm_rect_width(&plane_state->src)) {
+			src_w = drm_rect_width(&plane_state->src) >> 16;
+			src_h = drm_rect_height(&plane_state->src) >> 16;
+		} else {
+			src_w = intel_crtc->config->pipe_src_w;
+			src_h = intel_crtc->config->pipe_src_h;
+		}
+
+		if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+			p->plane[0].horiz_pixels = src_h;
+			p->plane[0].vert_pixels = src_w;
+		} else {
+			p->plane[0].horiz_pixels = src_w;
+			p->plane[0].vert_pixels = src_h;
+		}
 		p->plane[0].rotation = crtc->primary->state->rotation;
 
 		fb = crtc->cursor->state->fb;
@@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	intel_plane->wm.enabled = enabled;
 	intel_plane->wm.scaled = scaled;
-	intel_plane->wm.horiz_pixels = sprite_width;
-	intel_plane->wm.vert_pixels = sprite_height;
+
+	if (intel_rotation_90_or_270(plane->state->rotation)) {
+		intel_plane->wm.horiz_pixels = sprite_height;
+		intel_plane->wm.vert_pixels = sprite_width;
+	} else {
+		intel_plane->wm.horiz_pixels = sprite_width;
+		intel_plane->wm.vert_pixels = sprite_height;
+	}
+
 	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
 
 	/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
-- 
1.7.9.5

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Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Daniel Vetter]

On Fri, Jun 26, 2015 at 06:53:49AM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
> 
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>

Do we have an igt which provokes underruns and hence can test this
automatically? Very tall/narrow buffers should do it I think.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c |   32 ++++++++++++++++++++++++++++----
>  1 file changed, 28 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ea3e435..767313b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  	enum pipe pipe = intel_crtc->pipe;
>  	struct drm_plane *plane;
>  	struct drm_framebuffer *fb;
> +	struct intel_plane_state *plane_state;
> +	int src_w, src_h;
>  	int i = 1; /* Index for sprite planes start */
>  
>  	p->active = intel_crtc->active;
> @@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
>  
>  		fb = crtc->primary->state->fb;
> +		plane_state = to_intel_plane_state(crtc->primary->state);
>  		/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
>  		if (fb) {
>  			p->plane[0].enabled = true;
> @@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  			p->plane[0].y_bytes_per_pixel = 0;
>  			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
>  		}
> -		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> -		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> +
> +		if (drm_rect_width(&plane_state->src)) {
> +			src_w = drm_rect_width(&plane_state->src) >> 16;
> +			src_h = drm_rect_height(&plane_state->src) >> 16;
> +		} else {
> +			src_w = intel_crtc->config->pipe_src_w;
> +			src_h = intel_crtc->config->pipe_src_h;
> +		}
> +
> +		if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
> +			p->plane[0].horiz_pixels = src_h;
> +			p->plane[0].vert_pixels = src_w;
> +		} else {
> +			p->plane[0].horiz_pixels = src_w;
> +			p->plane[0].vert_pixels = src_h;
> +		}
>  		p->plane[0].rotation = crtc->primary->state->rotation;
>  
>  		fb = crtc->cursor->state->fb;
> @@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	intel_plane->wm.enabled = enabled;
>  	intel_plane->wm.scaled = scaled;
> -	intel_plane->wm.horiz_pixels = sprite_width;
> -	intel_plane->wm.vert_pixels = sprite_height;
> +
> +	if (intel_rotation_90_or_270(plane->state->rotation)) {
> +		intel_plane->wm.horiz_pixels = sprite_height;
> +		intel_plane->wm.vert_pixels = sprite_width;
> +	} else {
> +		intel_plane->wm.horiz_pixels = sprite_width;
> +		intel_plane->wm.vert_pixels = sprite_height;
> +	}
> +
>  	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
>  
>  	/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Konduru, Chandra]

> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>

Do we have an igt which provokes underruns and hence can test this
automatically? Very tall/narrow buffers should do it I think.
-Daniel

Yes. Right now kms_rotation_crc is the case we have, but I'm also
triggering something via kms_nv12 too.
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Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6564
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  284/284              284/284
HSW                                  380/380              380/380
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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