Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

Daniel Vetter
2015-08-26T09:16:34Z

On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> In order to flush the results from in-batch pipecontrol writes (used for
> example in glQuery) before declaring the batch complete (and so declaring
> the query results coherent), we need to set the FlushEnable bit in our
> flushing pipecontrol. The FlushEnable bit "waits until all previous
> writes of immediate data from post-sync circles are complete before
> executing the next command".
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: stable@vger.kernel.org

Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
bugzilla or why is this cc: stable?
-Daniel

> ---
> drivers/gpu/drm/i915/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 01cf0ca21990..e0c19d75b196 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
>
> if (invalidate_domains) {
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c2392f6c4204..551af7399ca1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> if (flush_domains) {
> flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> }
> if (invalidate_domains) {
> flags |= PIPE_CONTROL_TLB_INVALIDATE;
> --
> 2.5.0
>
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--
Daniel Vetter
Software Engineer, Intel Corporation