From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2 3/5] drm/i915/cnl+: Verify combo PHY HW state during PHY uninit Date: Wed, 7 Nov 2018 20:46:09 +0000 Message-ID: References: <20181106160621.23057-1-imre.deak@intel.com> <20181106160621.23057-4-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1089797008==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5304889650 for ; Wed, 7 Nov 2018 20:46:11 +0000 (UTC) In-Reply-To: <20181106160621.23057-4-imre.deak@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Deak, Imre" Cc: "Zanoni, Paulo R" , "Vivi, Rodrigo" List-Id: intel-gfx@lists.freedesktop.org --===============1089797008== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-r3WstfdUAfcsnMWqa+LR" --=-r3WstfdUAfcsnMWqa+LR Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2018-11-06 at 18:06 +0200, Imre Deak wrote: > Verify on CNL, ICL that the combo PHY HW state stayed intact after > PHY > initialization. >=20 > v2: > - Print 'Port X' as we do elsewhere instead of 'Port-X'. (Jose) >=20 > Cc: Paulo Zanoni > Cc: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jos=C3=A9 Roberto de Souza > Cc: Jos=C3=A9 Roberto de Souza > Cc: Rodrigo Vivi > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_combo_phy.c | 103 > ++++++++++++++++++++++++++++++++- > 1 file changed, 101 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_combo_phy.c > b/drivers/gpu/drm/i915/intel_combo_phy.c > index 8dd0a3c68f01..83132d763e34 100644 > --- a/drivers/gpu/drm/i915/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/intel_combo_phy.c > @@ -34,8 +34,8 @@ static const struct cnl_procmon { > * registers, that's why we call the ICL macros even though the > function has CNL > * on its name. > */ > -static void cnl_set_procmon_ref_values(struct drm_i915_private > *dev_priv, > - enum port port) > +static const struct cnl_procmon * > +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum > port port) > { > const struct cnl_procmon *procmon; > u32 val; > @@ -62,6 +62,17 @@ static void cnl_set_procmon_ref_values(struct > drm_i915_private *dev_priv, > break; > } > =20 > + return procmon; > +} > + > +static void cnl_set_procmon_ref_values(struct drm_i915_private > *dev_priv, > + enum port port) > +{ > + const struct cnl_procmon *procmon; > + u32 val; > + > + procmon =3D cnl_get_procmon_ref_values(dev_priv, port); > + > val =3D I915_READ(ICL_PORT_COMP_DW1(port)); > val &=3D ~((0xff << 16) | 0xff); > val |=3D procmon->dw1; > @@ -71,6 +82,63 @@ static void cnl_set_procmon_ref_values(struct > drm_i915_private *dev_priv, > I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10); > } > =20 > +static bool check_phy_reg(struct drm_i915_private *dev_priv, > + enum port port, i915_reg_t reg, u32 mask, > + u32 expected_val) > +{ > + u32 val =3D I915_READ(reg); > + > + if ((val & mask) !=3D expected_val) { > + DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state > mismatch: " > + "current %08x mask %08x expected > %08x\n", > + port_name(port), > + reg.reg, val, mask, expected_val); > + return false; > + } > + > + return true; > +} > + > +static bool cnl_verify_procmon_ref_values(struct drm_i915_private > *dev_priv, > + enum port port) > +{ > + const struct cnl_procmon *procmon; > + bool ret; > + > + procmon =3D cnl_get_procmon_ref_values(dev_priv, port); > + > + ret =3D check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port), > + (0xff << 16) | 0xff, procmon->dw1); > + ret &=3D check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port), > + -1U, procmon->dw9); > + ret &=3D check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port), > + -1U, procmon->dw10); > + > + return ret; > +} > + > +static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) > +{ > + return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && > + (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); > +} > + > +static bool cnl_combo_phy_verify_state(struct drm_i915_private > *dev_priv) > +{ > + enum port port =3D PORT_A; > + bool ret; > + > + if (!cnl_combo_phy_enabled(dev_priv)) > + return false; > + > + ret =3D cnl_verify_procmon_ref_values(dev_priv, port); > + > + ret &=3D check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5, > + CL_POWER_DOWN_ENABLE, > CL_POWER_DOWN_ENABLE); > + > + return ret; > +} > + > void cnl_combo_phys_init(struct drm_i915_private *dev_priv) > { > u32 val; > @@ -95,11 +163,38 @@ void cnl_combo_phys_uninit(struct > drm_i915_private *dev_priv) > { > u32 val; > =20 > + if (!cnl_combo_phy_verify_state(dev_priv)) > + DRM_WARN("Combo PHY HW state changed unexpectedly.\n"); > + > val =3D I915_READ(CHICKEN_MISC_2); > val |=3D CNL_COMP_PWR_DOWN; > I915_WRITE(CHICKEN_MISC_2, val); > } > =20 > +static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + return !(I915_READ(ICL_PHY_MISC(port)) & > + ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && > + (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT); > +} > + > +static bool icl_combo_phy_verify_state(struct drm_i915_private > *dev_priv, > + enum port port) > +{ > + bool ret; > + > + if (!icl_combo_phy_enabled(dev_priv, port)) > + return false; > + > + ret =3D cnl_verify_procmon_ref_values(dev_priv, port); > + > + ret &=3D check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port), > + CL_POWER_DOWN_ENABLE, > CL_POWER_DOWN_ENABLE); > + > + return ret; > +} > + > void icl_combo_phys_init(struct drm_i915_private *dev_priv) > { > enum port port; > @@ -130,6 +225,10 @@ void icl_combo_phys_uninit(struct > drm_i915_private *dev_priv) > for (port =3D PORT_A; port <=3D PORT_B; port++) { > u32 val; > =20 > + if (!icl_combo_phy_verify_state(dev_priv, port)) > + DRM_WARN("Port %c combo PHY HW state changed > unexpectedly\n", > + port_name(port)); > + > val =3D I915_READ(ICL_PHY_MISC(port)); > val |=3D ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > I915_WRITE(ICL_PHY_MISC(port), val); --=-r3WstfdUAfcsnMWqa+LR Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlvjTw8ACgkQVenbO/mO Wkl2Jwf+L5DQ50+syelVjDisfHD6b00uwFCO7ol0RMw16qI5JhTyFZxG95zvL30S zYCNptacERnU5kpIxW77J1OxnC/T3WGXI8LmZ3oMY9Pjlo6XkKVeYsDmLOSm1LCD 0+7J/5kyQJ6Gz5QaHAtzxexI19zcm0M11LqZI0emgSdbUkKbef7HmB2juFGmvwmo sZ9rb1tful9PxNqXA8u4SVK54wENT9wE1Lk25nHykrR6mdAS64aAYU7Wxn4ttirw miteVhxb91w34YP8Px6k8ztEmt9z81ffKeAoufl1iy+OoB9aA9gZ8XntKLsr/xbF 5Ubp0idH6io0Ibvqio+k0JGD47SiMw== =b4Wp -----END PGP SIGNATURE----- --=-r3WstfdUAfcsnMWqa+LR-- --===============1089797008== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1089797008==--