From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/3] drm/i915: Ivybridge still has fences! Date: Sun, 23 Oct 2011 12:23:14 +0100 Message-ID: References: <1318189923-4609-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 1741E9E76C for ; Sun, 23 Oct 2011 04:23:20 -0700 (PDT) In-Reply-To: <1318189923-4609-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter , stable@kernel.org List-Id: intel-gfx@lists.freedesktop.org Regardless of the outcome of Jesse's request for an if-ladder, the substance of the patches look sound. However, I remain unconvinced that there are 32 fence registers on IVB. Daniel's evidence is based upon the size of the register map (and not on the BSPEC explicitly stating a change to 32 ;-), but most tellingly the bitfields for fence-number in other registers have not been updated - so we can only safely allocated the first 16 anyway... (For instance, FBC_CTL). -Chris -- Chris Wilson, Intel Open Source Technology Centre