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From: "Lis, Tomasz" <tomasz.lis@intel.com>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: bartosz.dunajski@intel.com
Subject: Re: [PATCH v4] drm/i915: Add IOCTL Param to control data port coherency.
Date: Wed, 11 Jul 2018 13:20:42 +0200	[thread overview]
Message-ID: <af9f627d-2bb4-af4d-9c3c-c24da1154c71@intel.com> (raw)
In-Reply-To: <1c7685b7-a1bf-37a0-d3d7-19e5c0847317@intel.com>



On 2018-07-10 20:03, Lis, Tomasz wrote:
>
>
> On 2018-07-09 18:28, Tvrtko Ursulin wrote:
>>
>> On 09/07/2018 14:20, Tomasz Lis wrote:
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.h 
>>> b/drivers/gpu/drm/i915/intel_lrc.h
>>> index 1593194..f6965ae 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.h
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.h
>>> [...]
>>> +/*
>>> + * When data port level coherency is enabled, the GPU will update 
>>> memory
>>> + * buffers shared with CPU, by forcing internal cache units to send 
>>> memory
>>> + * writes to real RAM faster. Keeping such coherency has 
>>> performance cost.
>>
>> Is this comment correct? Is it actually sending memory writes to 
>> _RAM_, or just the coherency mode enabled, even if only targetting 
>> CPU or shared cache, which adds a cost?
> I'm not sure whether there are further coherency modes to choose how 
> "deep" coherency goes. The use case of OCL Team is to see gradual 
> changes in the buffers on CPU side while the execution progresses. 
> Write to RAM is needed to achieve that. And that limits performance by 
> using RAM bandwidth.

It was pointed out to me that last level cache is shared between CPU and 
GPU on non-atoms. Which means my argument was invalid, an most likely 
the coherency option does not enforce RAM write. I will update the comment.
-Tomasz

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  reply	other threads:[~2018-07-11 11:20 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-19 12:37 [RFC v1] Data port coherency control for UMDs Tomasz Lis
2018-03-19 12:37 ` [RFC v1] drm/i915: Add Exec param to control data port coherency Tomasz Lis
2018-03-19 12:43   ` Chris Wilson
2018-03-19 14:14     ` Lis, Tomasz
2018-03-19 14:26       ` Chris Wilson
2018-03-20 17:23         ` Lis, Tomasz
2018-05-04  9:24           ` Joonas Lahtinen
2018-03-20 18:43       ` Oscar Mateo
2018-03-21 10:16         ` Chris Wilson
2018-03-21 19:42           ` Oscar Mateo
2018-03-27 17:41             ` Lis, Tomasz
2018-03-30 17:29   ` [PATCH " Tomasz Lis
2018-03-31 19:07     ` kbuild test robot
2018-04-11 15:46   ` [PATCH v2] " Tomasz Lis
2018-06-20 15:03   ` [PATCH v1] Second implementation of Data Port Coherency Tomasz Lis
2018-06-20 15:03     ` [PATCH v1] drm/i915: Add IOCTL Param to control data port coherency Tomasz Lis
2018-06-21  6:39       ` Joonas Lahtinen
2018-06-21 13:47         ` Lis, Tomasz
2018-07-18 13:03           ` Joonas Lahtinen
2018-06-21  7:05       ` Chris Wilson
2018-06-21 13:47         ` Lis, Tomasz
2018-06-21  7:31       ` Dunajski, Bartosz
2018-06-21  8:48         ` Joonas Lahtinen
2018-06-22 16:40           ` Dunajski, Bartosz
2018-07-18 13:12             ` Joonas Lahtinen
2018-07-18 13:27               ` Dunajski, Bartosz
2018-07-09 13:20   ` [PATCH v4] " Tomasz Lis
2018-07-09 13:48     ` Lionel Landwerlin
2018-07-09 14:03       ` Lis, Tomasz
2018-07-09 14:24         ` Lionel Landwerlin
2018-07-09 15:21           ` Lis, Tomasz
2018-07-09 16:28     ` Tvrtko Ursulin
2018-07-09 16:37       ` Chris Wilson
2018-07-10 17:32         ` Lis, Tomasz
2018-07-11  9:28           ` Tvrtko Ursulin
2018-07-10 18:03       ` Lis, Tomasz
2018-07-11 11:20         ` Lis, Tomasz [this message]
2018-07-12 15:10   ` [PATCH v5] " Tomasz Lis
2018-07-13 10:40     ` Tvrtko Ursulin
2018-07-13 17:44       ` Lis, Tomasz
2018-10-09 18:06   ` [PATCH v6] " Tomasz Lis
2018-10-10  7:29     ` Tvrtko Ursulin
2018-10-12 15:02   ` [PATCH v8] " Tomasz Lis
2018-10-15 12:52     ` Tvrtko Ursulin
2018-10-16 13:59     ` Joonas Lahtinen
2018-03-19 13:53 ` [RFC v1] Data port coherency control for UMDs Joonas Lahtinen
2018-03-19 16:09   ` Lis, Tomasz
2018-03-20 15:15   ` Dunajski, Bartosz
2018-03-21 10:02     ` Joonas Lahtinen
2018-03-26  9:46       ` Dunajski, Bartosz
2018-03-29  7:42         ` Joonas Lahtinen
2018-03-30  9:00           ` Dunajski, Bartosz
2018-04-04  9:18             ` Joonas Lahtinen
2018-04-11  9:15               ` Dunajski, Bartosz
2018-03-19 14:18 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency Patchwork
2018-03-19 14:34 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-19 16:48 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-30 18:14 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev2) Patchwork
2018-03-30 18:30 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-30 19:59 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-11 16:12 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev3) Patchwork
2018-04-11 16:29 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-06-20 15:45 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev4) Patchwork
2018-06-20 16:00 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-20 21:01 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-09 13:57 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev5) Patchwork
2018-07-09 13:58 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-09 14:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-09 20:04 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-12 15:18 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev6) Patchwork
2018-07-12 15:19 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-12 15:34 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-09 18:27 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev7) Patchwork
2018-10-09 18:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-09 18:52 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-09 21:44 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-10-12 15:14 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add Exec param to control data port coherency. (rev8) Patchwork
2018-10-12 15:15 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-12 15:34 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-12 18:27 ` ✗ Fi.CI.IGT: failure " Patchwork

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