From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH v2 1/5] drm/i915/icl: Fix combo PHY uninit Date: Wed, 7 Nov 2018 20:37:59 +0000 Message-ID: References: <20181106160621.23057-1-imre.deak@intel.com> <20181106160621.23057-2-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1037389226==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A7636E491 for ; Wed, 7 Nov 2018 20:38:01 +0000 (UTC) In-Reply-To: <20181106160621.23057-2-imre.deak@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Deak, Imre" Cc: "rodrigo.vivi@intel.c" , "Zanoni, Paulo R" List-Id: intel-gfx@lists.freedesktop.org --===============1037389226== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-+kOHFOQXL7ZoF1CQHFq3" --=-+kOHFOQXL7ZoF1CQHFq3 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2018-11-06 at 18:06 +0200, Imre Deak wrote: > BSpec says to clear the comp init HW flag too during combo PHY > uninit, > so do that. The lack of this could badly interact with the PHY reinit > after a DC6/9 transition at least, where (after a follow-up patch > fixing > the init code) we'd skip the initialization incorrectly due to this > flag > being set. >=20 > BSpec: 21257 > Cc: Paulo Zanoni > Cc: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jos=C3=A9 Roberto de Souza > Cc: Jos=C3=A9 Roberto de Souza > Cc: Rodrigo Vivi Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 6c453366cd24..a7eea8423580 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3668,6 +3668,10 @@ void icl_display_core_uninit(struct > drm_i915_private *dev_priv) > val =3D I915_READ(ICL_PHY_MISC(port)); > val |=3D ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; > I915_WRITE(ICL_PHY_MISC(port), val); > + > + val =3D I915_READ(ICL_PORT_COMP_DW0(port)); > + val &=3D ~COMP_INIT; > + I915_WRITE(ICL_PORT_COMP_DW0(port), val); > } > } > =20 --=-+kOHFOQXL7ZoF1CQHFq3 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlvjTRkACgkQVenbO/mO WknrTQgAuMtNwKCJU7oG0dE5t4hpWPWs7/UkDkifjfTCLLGFxnQj+IO5TRFy953n ksJjc14XLcSbILTC4Gz6Ec2Vlhy4h9rQ5rZMW2U8YDXdYKYJVp1CGcuGMH3CmKjR ecXpFGL+4l9Fr9F2+fhX/CWntCT0ylWopNA4djoxRtv7Uiv0r+Uta02NTa8owIh3 IH3yYs0awliaqD2/JrBKDHDrWm0EJDW5nJxeSu/8q1Seck6N4pWtLTo4UPhr1GsA aEfgjmRxhr/uJ8C6hNt+xR+jHnvvo+4c0Pisiova8ujmexE/7CqZyqukiX+2GEYv CWk5YT54EyBxjDYYQVN9Am306GsYxA== =YoSq -----END PGP SIGNATURE----- --=-+kOHFOQXL7ZoF1CQHFq3-- --===============1037389226== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1037389226==--