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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"Manna,  Animesh" <animesh.manna@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 3/4] drm/i915/alpm: Replace hardcoded LFPS cycle with proper calculation
Date: Thu, 28 Aug 2025 09:39:03 +0000	[thread overview]
Message-ID: <b33c00334f8f7c22e28e72fa2220245108198541.camel@intel.com> (raw)
In-Reply-To: <DS0PR11MB8049AF52A8708C528B4215F0F93BA@DS0PR11MB8049.namprd11.prod.outlook.com>

On Thu, 2025-08-28 at 07:35 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf
> > Of Jouni
> > Högander
> > Sent: Wednesday, August 13, 2025 12:36 PM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Hogander, Jouni <jouni.hogander@intel.com>
> > Subject: [PATCH 3/4] drm/i915/alpm: Replace hardcoded LFPS cycle
> > with
> > proper calculation
> > 
> > Currently LFPS is hadcoded for different port clocks. Replace this
> > with proper
> > calculation.
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 90 ++++++++++---------
> > ----
> >  1 file changed, 38 insertions(+), 52 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index ae556a885c2a..b2123305f128 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -58,58 +58,43 @@ static int get_silence_period_symbols(const
> > struct
> > intel_crtc_state *crtc_state)
> >  		1000 / 1000;
> >  }
> > 
> > -/*
> > - * See Bspec: 71632 for the table
> > - *
> > - * Half cycle duration:
> > - *
> > - * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
> > - * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
> > - *
> > - * Link rates 5.4 - 8.1
> > - * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
> > - * LFPS Period chosen is the mid-point of the min:max values from
> > the table
> > - * FLOOR( LFPS Period in Symbol clocks /
> > - * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) )
> > - */
> > -static bool _lnl_get_lfps_half_cycle(int link_rate, int
> > *lfps_half_cycle)
> > +static int get_lfps_cycle_min_max_time(const struct
> > intel_crtc_state
> > *crtc_state,
> > +				       int *min, int *max)
> >  {
> > -	switch (link_rate) {
> > -	case 162000:
> > -		*lfps_half_cycle = 5;
> > -		break;
> > -	case 216000:
> > -		*lfps_half_cycle = 7;
> > -		break;
> > -	case 243000:
> > -		*lfps_half_cycle = 8;
> > -		break;
> > -	case 270000:
> > -		*lfps_half_cycle = 9;
> > -		break;
> > -	case 324000:
> > -		*lfps_half_cycle = 11;
> > -		break;
> > -	case 432000:
> > -		*lfps_half_cycle = 15;
> > -		break;
> > -	case 540000:
> > -		*lfps_half_cycle = 12;
> > -		break;
> > -	case 648000:
> > -		*lfps_half_cycle = 15;
> > -		break;
> > -	case 675000:
> > -		*lfps_half_cycle = 15;
> > -		break;
> > -	case 810000:
> > -		*lfps_half_cycle = 19;
> > -		break;
> > -	default:
> > -		*lfps_half_cycle = -1;
> > -		return false;
> > +	if (crtc_state->port_clock < 540000) {
> > +		*min = 65 * LFPS_CYCLE_COUNT;
> > +		*max = 75 * LFPS_CYCLE_COUNT;
> > +	} else if (crtc_state->port_clock <= 810000) {
> > +		*min = 140;
> > +		*max = 800;
> > +	} else {
> > +		*min = *max = -1;
> > +		return -1;
> >  	}
> > -	return true;
> > +
> > +	return 0;
> > +}
> > +
> > +static int get_lfps_cycle_time(const struct intel_crtc_state
> > +*crtc_state) {
> > +	int tlfps_cycle_min, tlfps_cycle_max, ret;
> > +
> > +	ret = get_lfps_cycle_min_max_time(crtc_state,
> > &tlfps_cycle_min,
> > +					  &tlfps_cycle_max);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return tlfps_cycle_min +  (tlfps_cycle_max -
> > tlfps_cycle_min) / 2; }
> > +
> > +static int get_lfps_half_cycle_clocks(const struct
> > intel_crtc_state
> > +*crtc_state) {
> > +	int lfps_cycle_time = get_lfps_cycle_time(crtc_state);
> > +
> > +	if (lfps_cycle_time < 0)
> > +		return -1;
> > +
> > +	return lfps_cycle_time * crtc_state->port_clock / 1000 /
> > 1000 / 20;
> 
> What 20 means above? if it is derived from LFPS cycle count then good
> to use LFPS_CYCLE_COUNT macro.

You are right. It's 2 * LFPS cycle count. I will fix this.

BR,

Jouni Högander

> 
> Regards,
> Animesh
> 
> >  }
> > 
> >  /*
> > @@ -161,8 +146,9 @@ _lnl_compute_aux_less_alpm_params(struct
> > intel_dp *intel_dp,
> >  	aux_less_wake_lines =
> > intel_usecs_to_scanlines(&crtc_state-
> > > hw.adjusted_mode,
> >  						      
> > aux_less_wake_time);
> >  	silence_period = get_silence_period_symbols(crtc_state);
> > -	if (!_lnl_get_lfps_half_cycle(crtc_state->port_clock,
> > -				      &lfps_half_cycle))
> > +
> > +	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
> > +	if (lfps_half_cycle < 0)
> >  		return false;
> > 
> >  	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK
> > > > 
> > --
> > 2.43.0
> 


  reply	other threads:[~2025-08-28  9:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-13  7:06 [PATCH 0/4] ALPM LFPS and silence period calculation Jouni Högander
2025-08-13  7:06 ` [PATCH 1/4] drm/i915/alpm: Calculate silence period Jouni Högander
2025-08-28  6:39   ` Manna, Animesh
2025-08-13  7:06 ` [PATCH 2/4] drm/i915/alpm: Add own define for LFPS count Jouni Högander
2025-08-28  7:00   ` Manna, Animesh
2025-08-13  7:06 ` [PATCH 3/4] drm/i915/alpm: Replace hardcoded LFPS cycle with proper calculation Jouni Högander
2025-08-28  7:35   ` Manna, Animesh
2025-08-28  9:39     ` Hogander, Jouni [this message]
2025-08-13  7:06 ` [PATCH 4/4] drm/i915/alpm: Use actual lfps cycle and silence periods in wake time Jouni Högander
2025-08-28  7:54   ` Manna, Animesh
2025-08-28  9:48     ` Hogander, Jouni
2025-08-13  8:21 ` ✓ i915.CI.BAT: success for ALPM LFPS and silence period calculation Patchwork
2025-08-13  9:52 ` ✗ i915.CI.Full: failure " Patchwork

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