From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 883D4C433F5 for ; Thu, 9 Dec 2021 17:01:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA3CA10E629; Thu, 9 Dec 2021 16:54:39 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C413F10E121; Thu, 9 Dec 2021 15:15:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639062901; x=1670598901; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=i4VTU44a7vwNBDgQOwjIJ8qx7a6awh3B2AlbEsl7LaM=; b=bB/TFh01e9RaGZ/svyw14gKojT8MfLRjkDKifDNCW+DNOhg59rIl7MIB KYb4KrHNMZbVbID055lCMbbi71IdGRFBAy6x4ylJFkG+i+jTSgP7kFF1Q zXL+gZdPjQVtQK7etfeIqxsJk8fUI8q5ZrUgoZCGBHmo9YheWtTj8WeLs akQAfbgGOJ6b+CA4cctXCDiokFY9h04vC9Oq7RqVI0NNH7weq8yRiZicW 8vI9pouworYQuUa96iJliaBOwAKvmb9o0QstKHgSscu9mWa8ERBf5f9KL xA79eoTcivxDOxxAMZoHdhY9lK3vBLHynmw2O0SQiQNWu3yWDtuBaS7mA g==; X-IronPort-AV: E=McAfee;i="6200,9189,10192"; a="298909088" X-IronPort-AV: E=Sophos;i="5.88,192,1635231600"; d="scan'208";a="298909088" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2021 07:15:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,192,1635231600"; d="scan'208";a="680357558" Received: from irsmsx601.ger.corp.intel.com ([163.33.146.7]) by orsmga005.jf.intel.com with ESMTP; 09 Dec 2021 07:15:00 -0800 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by irsmsx601.ger.corp.intel.com (163.33.146.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Thu, 9 Dec 2021 15:14:58 +0000 Received: from fmsmsx611.amr.corp.intel.com ([10.18.126.91]) by fmsmsx611.amr.corp.intel.com ([10.18.126.91]) with mapi id 15.01.2308.020; Thu, 9 Dec 2021 07:14:57 -0800 From: "Chery, Nanley G" To: "Lisovskiy, Stanislav" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [PATCH 1/2] drm/i915: Introduce new Tile 4 format Thread-Index: AQHX7OohHRHIyXgnbE247GMp18/vBqwqQl1Q Date: Thu, 9 Dec 2021 15:14:56 +0000 Message-ID: References: <20211209104711.14790-1-stanislav.lisovskiy@intel.com> In-Reply-To: <20211209104711.14790-1-stanislav.lisovskiy@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.132] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Introduce new Tile 4 format X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "dri-devel@lists.freedesktop.org" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Lisovskiy, Stanislav > Sent: Thursday, December 9, 2021 5:47 AM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Lisovskiy, Stanislav > ; Saarinen, Jani = ; C, > Ramalingam ; ville.syrjala@linux.intel.com; Deak, > Imre ; Chery, Nanley G > Subject: [PATCH 1/2] drm/i915: Introduce new Tile 4 format >=20 We want this patch to be 2/2, right? That way, we expose public kernel supp= ort for the format after the kernel gains internal support for it.=20 With that fixed, this patch is: Acked-by: Nanley Chery Alternatively, you could apply the ack to the prior combined patch if you'd= like. -Nanley > This tiling layout uses 4KB tiles in a row-major layout. It has the same = shape as > Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It only d= iffers from > Tile Y at the 256B granularity in between. At this granularity, Tile Y ha= s a shape > of 16B x 32 rows, but this tiling has a shape of 64B x 8 rows. >=20 > Signed-off-by: Stanislav Lisovskiy > --- > include/uapi/drm/drm_fourcc.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) >=20 > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.= h > index 7f652c96845b..a146c6df1066 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -565,6 +565,17 @@ extern "C" { > */ > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC > fourcc_mod_code(INTEL, 8) >=20 > +/* > + * Intel Tile 4 layout > + * > + * This is a tiled layout using 4KB tiles in a row-major layout. It has > +the same > + * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x > +4). It > + * only differs from Tile Y at the 256B granularity in between. At this > + * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling > +has a shape > + * of 64B x 8 rows. > + */ > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) > + > /* > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks > * > -- > 2.24.1.485.gad05a3d8e5