From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B69D9C0015E for ; Mon, 24 Jul 2023 08:38:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0F7310E286; Mon, 24 Jul 2023 08:38:30 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 503A710E283; Mon, 24 Jul 2023 08:38:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690187908; x=1721723908; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to; bh=r3DsYCItZr9dOUWVeoZviHNZIHxyJFBYtsMfC4iDvqU=; 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boundary="------------Bx0kO8zl2zG0y267RUhKYFod" Message-ID: Date: Mon, 24 Jul 2023 10:38:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das , Andrzej Hajda References: <20230721161514.818895-1-andi.shyti@linux.intel.com> <20230721161514.818895-3-andi.shyti@linux.intel.com> From: Nirmoy Das In-Reply-To: <20230721161514.818895-3-andi.shyti@linux.intel.com> Subject: Re: [Intel-gfx] [PATCH v8 2/9] drm/i915: Add the gen12_needs_ccs_aux_inv helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , dri-evel , linux-stable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is a multi-part message in MIME format. --------------Bx0kO8zl2zG0y267RUhKYFod Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/21/2023 6:15 PM, Andi Shyti wrote: > We always assumed that a device might either have AUX or FLAT > CCS, but this is an approximation that is not always true, e.g. > PVC represents an exception. > > Set the basis for future finer selection by implementing a > boolean gen12_needs_ccs_aux_inv() function that tells whether aux > invalidation is needed or not. > > Currently PVC is the only exception to the above mentioned rule. > > Signed-off-by: Andi Shyti > Cc: Matt Roper > Cc: Jonathan Cavitt > Cc: # v5.8+ |Reviewed-by: Nirmoy Das | > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 563efee055602..460c9225a50fc 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -165,6 +165,18 @@ static u32 preparser_disable(bool state) > return MI_ARB_CHECK | 1 << 8 | state; > } > > +static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine) > +{ > + if (IS_PONTEVECCHIO(engine->i915)) > + return false; > + > + /* > + * so far platforms supported by i915 having > + * flat ccs do not require AUX invalidation > + */ > + return !HAS_FLAT_CCS(engine->i915); > +} > + > u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg) > { > u32 gsi_offset = gt->uncore->gsi_offset; > @@ -267,7 +279,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > else if (engine->class == COMPUTE_CLASS) > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > - if (!HAS_FLAT_CCS(rq->engine->i915)) > + if (gen12_needs_ccs_aux_inv(rq->engine)) > count = 8 + 4; > else > count = 8; > @@ -285,7 +297,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); > > - if (!HAS_FLAT_CCS(rq->engine->i915)) { > + if (gen12_needs_ccs_aux_inv(rq->engine)) { > /* hsdes: 1809175790 */ > cs = gen12_emit_aux_table_inv(rq->engine->gt, cs, > GEN12_CCS_AUX_INV); > @@ -307,7 +319,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) > if (mode & EMIT_INVALIDATE) { > cmd += 2; > > - if (!HAS_FLAT_CCS(rq->engine->i915) && > + if (gen12_needs_ccs_aux_inv(rq->engine) && > (rq->engine->class == VIDEO_DECODE_CLASS || > rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) { > aux_inv = rq->engine->mask & --------------Bx0kO8zl2zG0y267RUhKYFod Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


On 7/21/2023 6:15 PM, Andi Shyti wrote:
We always assumed that a device might either have AUX or FLAT
CCS, but this is an approximation that is not always true, e.g.
PVC represents an exception.

Set the basis for future finer selection by implementing a
boolean gen12_needs_ccs_aux_inv() function that tells whether aux
invalidation is needed or not.

Currently PVC is the only exception to the above mentioned rule.

Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: <stable@vger.kernel.org> # v5.8+

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 563efee055602..460c9225a50fc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -165,6 +165,18 @@ static u32 preparser_disable(bool state)
 	return MI_ARB_CHECK | 1 << 8 | state;
 }
 
+static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
+{
+	if (IS_PONTEVECCHIO(engine->i915))
+		return false;
+
+	/*
+	 * so far platforms supported by i915 having
+	 * flat ccs do not require AUX invalidation
+	 */
+	return !HAS_FLAT_CCS(engine->i915);
+}
+
 u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
 {
 	u32 gsi_offset = gt->uncore->gsi_offset;
@@ -267,7 +279,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		else if (engine->class == COMPUTE_CLASS)
 			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
-		if (!HAS_FLAT_CCS(rq->engine->i915))
+		if (gen12_needs_ccs_aux_inv(rq->engine))
 			count = 8 + 4;
 		else
 			count = 8;
@@ -285,7 +297,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
 
-		if (!HAS_FLAT_CCS(rq->engine->i915)) {
+		if (gen12_needs_ccs_aux_inv(rq->engine)) {
 			/* hsdes: 1809175790 */
 			cs = gen12_emit_aux_table_inv(rq->engine->gt, cs,
 						      GEN12_CCS_AUX_INV);
@@ -307,7 +319,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 	if (mode & EMIT_INVALIDATE) {
 		cmd += 2;
 
-		if (!HAS_FLAT_CCS(rq->engine->i915) &&
+		if (gen12_needs_ccs_aux_inv(rq->engine) &&
 		    (rq->engine->class == VIDEO_DECODE_CLASS ||
 		     rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
 			aux_inv = rq->engine->mask &
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