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Before guardband optimization, guradband was same as >> vblank length so EMP_AS_SDP_TL set with vrr.sync_start was falling in >> this region and it was not giving an issue. >> >> Now with optimized guardband, this is falling outside the SCL + >> guardband region and since the same transmission line is used by VSC SDP >> also, this results in PSR timeout issues. >> >> Further restrictions on the position of the transmission line: >> For DP/eDP, if there is a set context latency (SCL) window, then it >> cannot be the first line of SCL >> For DP/eDP, if there is no SCL window, then it cannot be the first line of >> the Delayed V. Blank >> >> Fix the EMP_AS_SDP_TL to VTOTAL - (delayed vblank_start - SCL + 1) >> Internally the HW computes the value as VTOTAL - EMP_AS_SDP_TL. >> >> Fixes: e1123e617e51 ("drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP") >> Cc: Ankit Nautiyal >> Cc: Jouni Högander >> Signed-off-by: Ankit Nautiyal >> --- >> drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++--- >> 1 file changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c >> index 92fb72b56f16..dd81d2133aba 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vrr.c >> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c >> @@ -655,18 +655,24 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state >> { >> struct intel_display *display = to_intel_display(crtc_state); >> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; >> + int transmission_line; >> >> /* >> * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming >> * double buffering point and transmission line for VRR packets for >> * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. >> * Since currently we support VRR only for DP/eDP, so this is programmed >> - * to for Adaptive Sync SDP to Vsync start. >> + * for Adaptive Sync SDP. >> */ >> - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) >> + if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) { >> + transmission_line = adjusted_mode->crtc_vtotal - (adjusted_mode->crtc_vblank_start - >> + crtc_state->set_context_latency + >> + 1); >> intel_de_write(display, >> EMP_AS_SDP_TL(display, cpu_transcoder), >> - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); >> + EMP_AS_SDP_DB_TL(transmission_line)); >> + } > Pretty sure we are expected to send it at vsync_start. Hmm.. then do we need to move vsync_start too similar to vblank_start for optimized guardband? If we do not move vsync_start, and set the transmission line to vsync_start, it will never fall in the region SCL + guardband with a reduced guardband. Meaning effectively the guardband will be full vblank length. Regards, Ankit >> } >> >> static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state) >> -- >> 2.45.2