From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 5/5] drm/i915/gmbus: Reset the controller on initialisation Date: Tue, 05 Apr 2011 22:26:55 +0100 Message-ID: References: <1301995458-2699-1-git-send-email-chris@chris-wilson.co.uk> <1301995458-2699-6-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 24E709E734 for ; Tue, 5 Apr 2011 14:26:59 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Keith Packard , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 05 Apr 2011 13:59:58 -0700, Keith Packard wrote: > On Tue, 5 Apr 2011 10:24:18 +0100, Chris Wilson wrote: > > Toggle the Software Clear Interrupt bit which resets the controller to > > clear any prior BUS_ERROR condition before we begin to use the > > controller in earnest. > > We do this in two places now, do we want to share the code? > > > + int reg_offset; > > + > > + reg_offset = 0; > > if (HAS_PCH_SPLIT(dev)) > > - I915_WRITE(PCH_GMBUS0, 0); > > - else > > - I915_WRITE(GMBUS0, 0); > > + reg_offset = PCH_GMBUS0 - GMBUS0; > > + > > + /* First reset the controller by toggling the Sw Clear Interrupt. */ > > + I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); > > + I915_WRITE(GMBUS1 + reg_offset, 0); > > + > > + /* Then mark the controller as disabled. */ > > + I915_WRITE(GMBUS0 + reg_offset, 0); > > That's really ugly register addressing, but it looks like a common idiom > in this file... I'd change the lot for a cleaner method, the best I thought of was a change of names for the constants/variables. IMO, static void i915_gmbus_write(struct drm_device *dev, int reg, int value) { struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(reg + (HAS_PCH_SPLIT(dev) ? PCH_GMBUS0 : GMBUS0), value); } expands to something dreadful. But with a #define GMBUS_WRITE(reg, value) i915_gmbus_write(dev, reg, value) we go from I915_WRITE(GMBUS0 + reg_offset, 0); to GMBUS_WRITE(0, 0); I would still prefer GMBUS_WRITE(GMBUS0, 0); though. As the patch only addresses a theoretical bug, we can punt the meat of the patch till later and attack the stylistic points first. (Obviously through -next.) -Chris -- Chris Wilson, Intel Open Source Technology Centre