From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Date: Wed, 13 Apr 2011 21:15:19 +0100 Message-ID: References: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> <1302640318-23165-27-git-send-email-chris@chris-wilson.co.uk> <20110413193702.GH3660@viiv.ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 44C5D9E989 for ; Wed, 13 Apr 2011 13:15:22 -0700 (PDT) In-Reply-To: <20110413193702.GH3660@viiv.ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 13 Apr 2011 21:37:03 +0200, Daniel Vetter wrote: > On Tue, Apr 12, 2011 at 09:31:54PM +0100, Chris Wilson wrote: > > We only want to mark the transition from unfenced GPU access by an > > execbuffer, so that we are forced to flush any pending writes through > > the fence before updating the register. > > The idea behind this change sounds good. Whilst I have you in agreement, what do I need to do get your r-b on the simple bug fix first? ;-) > But it completely kills the > optimization to not unnecessarily stall for fences when the fence isn't in > use anymore because we reset fenced_gpu_access = false only when moving to > the inactive list. And when flushing the fence, which is equally late. I'm following you so far... > What about moving > > fenced_gpu_access = false > > from flush_fence to process_flushing_list (and replace the one in > flush_fence with an WARN_ON(fenced_gpu_access) after the flush_ring)? And I'm still with you. Sounds good. -Chris -- Chris Wilson, Intel Open Source Technology Centre