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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SJ0PR11MB6813.namprd11.prod.outlook.com (2603:10b6:a03:47f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.11; Fri, 23 Jan 2026 11:33:59 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%3]) with mapi id 15.20.9542.010; Fri, 23 Jan 2026 11:33:58 +0000 Message-ID: Date: Fri, 23 Jan 2026 17:03:51 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 6/8] drm/i915/psr: Wait for idle only after possible send push To: "Hogander, Jouni" , "intel-xe@lists.freedesktop.org" , "intel-gfx@lists.freedesktop.org" References: <20251223105120.21505-1-jouni.hogander@intel.com> <20251223105120.21505-7-jouni.hogander@intel.com> <904618e8-d4e5-4775-bc42-69cf7a7d2c34@intel.com> <3e45764d418ec570574bd8af6e4c33aeef7b2b8d.camel@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <3e45764d418ec570574bd8af6e4c33aeef7b2b8d.camel@intel.com> Content-Type: text/plain; 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Due to this move wait for idle to be done after possible >>> send push >>> is done. >>> >>> This should be ok for Frame Change event triggered by register >>> write as >>> well. Wait for idle is needed only for corner case where PSR is >>> transitioning into DEEP_SLEEP when Frame Change event is triggered. >>> It just >>> has to be before wait for vblank. Otherwise we may have vblank >>> before PSR >>> enters DEEP_SLEEP and still using old frame buffers for first frame >>> after >>> wake up. >>> >>> Signed-off-by: Jouni Högander >>> --- >>>   drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++++--- >>>   1 file changed, 10 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c >>> b/drivers/gpu/drm/i915/display/intel_display.c >>> index c7ca4f53b8b8..1aca4802b7d5 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>> @@ -7333,9 +7333,6 @@ static void intel_atomic_dsb_finish(struct >>> intel_atomic_state *state, >>>    intel_psr_trigger_frame_change_event(new_crtc_stat >>> e->dsb_commit, >>>         state, crtc); >>> >>> - intel_psr_wait_for_idle_dsb(new_crtc_state- >>>> dsb_commit, >>> -     new_crtc_state); >>> - >>>    if (new_crtc_state->use_dsb) >>>    intel_dsb_vblank_evade(state, >>> new_crtc_state->dsb_commit); >>> >>> @@ -7375,6 +7372,16 @@ static void intel_atomic_dsb_finish(struct >>> intel_atomic_state *state, >>> >>>    intel_vrr_send_push(new_crtc_state->dsb_commit, >>> new_crtc_state); >>> >>> + /* >>> + * Wait for idle is needed for corner case where >>> PSR HW >>> + * is transitioning into DEEP_SLEEP/SRDENT_OFF >>> when >>> + * new Frame Change event comes in. It is ok to do >>> it >>> + * here for both Frame Change mecanisms (trans s/mecanisms/mechanism >>> push >>> + * and register write). >>> + */ >>> + intel_psr_wait_for_idle_dsb(new_crtc_state- >>>> dsb_commit, >>> +     new_crtc_state); >>> + >> If I understand correctly: >> >> For Fixed RR case: >> Suppose we are in PSR: >> Skip_wait_en is set. >> The portion around the Send Push will be like: >> >> >> -dsb_wait_vblank will no longer wait for the undelayed vblank (we are >> in >> PSR and skip_wait_en is set) >> -we send push -> to trigger frame change event for PSR HW. >> >> -After this PSR HW is supposed to receive the event and may be in >> transition period so we wait for idle dsb.(which internally makes >> sure >> that we are out of PSR) >> >> -We are not sure whether we are in active or in vblank region at this >> point of time so we want to use dsb_wait_vblank. The skip_wait_en >> will >> now not come in picture since we have made sure that we are not in >> PSR >> in previous step. >> >> Then other steps will be similar to what we have been doing. >> >> Is my understanding correct? >> >> What happens when Panel Replay is in picture, given we can have PR >> enable with Variable Refresh Rate timings. > I don't know how having VRR enabled would impact this sequence? send > push triggers "Frame Change" event -> possible PR active is exited -> > wait for vblank -> wait_for_delayed_vblank -> check push is sent. > > Do you have something specific in your mind? Hmm yes you are right, as you have mentioned with skip_wait_en chicken bit will make DSB jump the wait when Panel Replay is enabled. Lets say we have VRR : ON and Panel Replay enabled. -dsb_wait_vblank will no longer wait for the undelayed vblank (we are in PR and skip_wait_en is set) -we send push with send push bit and the frame change bit set. This will now happen earlier than the case where Panel Replay was not in picture, perhaps can be in active region. This will also result in frame change event for PSR/PR HW. -we then call intel_psr_wait_for_idle_dsb() that will make sure PR is out from deep sleep state. -We now wait for undelayed vblank which DSB will not jump because HW is not in Panel Replay active mode. -Then wait for delayed vblank, and check push sent etc should work as before. Only thing to check now is DC balance thing done by DMC FW, but I guess since HW is not in Panel Replay active state, it would not expect anything different than the non Panel Replay situation. In all, theoretically sequence looks alright to me. There are a few nitpicks in commit message and comment. Otherwise the patch LGTM. Reviewed-by: Ankit Nautiyal > > BR, > Jouni Högander > >> >> Regards, >> >> Ankit >> >>>    /* >>>    * In case PSR uses trans push as a "frame change" >>> event and >>>    * VRR is not in use we need to wait vblank. >>> Othervise we may