From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush Date: Thu, 18 Oct 2012 12:21:17 +0100 Message-ID: References: <1350553794-5534-1-git-send-email-daniel.vetter@ffwll.ch> <1350553794-5534-3-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A8A69EB0F for ; Thu, 18 Oct 2012 04:21:38 -0700 (PDT) In-Reply-To: <1350553794-5534-3-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Thu, 18 Oct 2012 11:49:51 +0200, Daniel Vetter wrote: > Comment says for eaglelake/cantiga, but it's listed in the ilk table, > too. So apply it to both. > > Signed-off-by: Daniel Vetter Looks harmless due to the massive number of other p/c errata and that pipelined render cache flushes have never been relied upon. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre