From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Date: Tue, 23 Oct 2012 12:42:07 +0100 Message-ID: References: <1350583639-773-1-git-send-email-jbarnes@virtuousgeek.org> <1350583639-773-7-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 177379F500 for ; Tue, 23 Oct 2012 05:12:49 -0700 (PDT) In-Reply-To: <1350583639-773-7-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes wrote: > "If ENABLED, PIPE_CONTROL command will flush the in flight data written > out by render engine to Global Observation point on flush done. Also > Requires stall bit ([20] of DW1) set." That quotation doesn't make sense in the context of TLB invalidation, and the programming guide here very carefully avoids the mention of requiring any stall bit set for the post-sync op of TLB invalidation. Maybe quote chapter and verse as well? -Chris -- Chris Wilson, Intel Open Source Technology Centre