From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: render p-state support for Sandybridge Date: Fri, 10 Dec 2010 09:37:00 +0000 Message-ID: References: <20101209150046.23bef984@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A58C9E733 for ; Fri, 10 Dec 2010 01:37:03 -0800 (PST) In-Reply-To: <20101209150046.23bef984@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 9 Dec 2010 15:00:46 -0800, Jesse Barnes wrote: > Note: this patch is just for comments/testing, it should not be > integrated at this time. So that's what drps stands for: dynamic render P-states! Jesse, at the very least shouldn't we apply the s/HAS_PCH_SPLIT/IS_GEN5/ in order not to be poking gen5 registers on gen6? -Chris -- Chris Wilson, Intel Open Source Technology Centre