From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT Date: Thu, 30 Dec 2010 18:06:20 +0000 Message-ID: References: <1293701795.5595.7.camel@zwerg> <1293703796.5729.2.camel@zwerg> <0d30dc$kjsbet@orsmga001.jf.intel.com> <1293708204.6744.2.camel@zwerg> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 009AF9E738 for ; Thu, 30 Dec 2010 10:06:23 -0800 (PST) In-Reply-To: <1293708204.6744.2.camel@zwerg> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Alexey Fisher Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Ok, understood my mistake, that line was indeed incorrect. Thanks, -Chris commit dc3bfebcf77d943b7e8495d30d0ee3d01b3042a5 Author: Chris Wilson Date: Thu Dec 30 18:02:21 2010 +0000 drm/i915: Don't skip ring flushes if only invalidating Commit 15056d2 tried to optimize away a flush if there were no outstanding writes on a ring (in order to prevent a too-early-flush during ring init). However, this has the unfortunate side-effect of eliminating the texture cache invalidation, and so causing rendering artefacts. Reported-by: Alexey Fisher Signed-off-by: Chris Wilson -- Chris Wilson, Intel Open Source Technology Centre