From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB673C11F68 for ; Fri, 2 Jul 2021 12:08:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7516961425 for ; Fri, 2 Jul 2021 12:08:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7516961425 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57E3488052; Fri, 2 Jul 2021 12:08:29 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1187A6E154; Fri, 2 Jul 2021 12:08:28 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10032"; a="196010109" X-IronPort-AV: E=Sophos;i="5.83,317,1616482800"; d="scan'208";a="196010109" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2021 05:08:25 -0700 X-IronPort-AV: E=Sophos;i="5.83,317,1616482800"; d="scan'208";a="455931353" Received: from juanniex-mobl.ger.corp.intel.com (HELO [10.213.253.90]) ([10.213.253.90]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2021 05:08:24 -0700 To: Matt Roper , intel-gfx@lists.freedesktop.org References: <20210701202427.1547543-1-matthew.d.roper@intel.com> <20210701202427.1547543-6-matthew.d.roper@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Fri, 2 Jul 2021 13:08:22 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210701202427.1547543-6-matthew.d.roper@intel.com> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 01/07/2021 21:23, Matt Roper wrote: > From: Venkata Sandeep Dhanalakota > > In Gen12 there are various fuse combinations and in each configuration > vdbox engine may be connected to SFC depending on which engines are > available, so we need to set the SFC capability based on fuse value from > the hardware. Even numbered phyical instance always have SFC, odd physical > numbered physical instances have SFC only if previous even instance is > fused off. Just a few nits. > Bspec: 48028 > Cc: Tvrtko Ursulin > Cc: Daniele Ceraolo Spurio > Signed-off-by: Venkata Sandeep Dhanalakota > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 ++++++++++++++++++----- > 1 file changed, 24 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 151870d8fdd3..4ab2c9abb943 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -442,6 +442,28 @@ void intel_engines_free(struct intel_gt *gt) > } > } > > +static inline Inline is not desired here. > +bool vdbox_has_sfc(struct drm_i915_private *i915, unsigned int physical_vdbox, > + unsigned int logical_vdbox, u16 vdbox_mask) > +{ I'd be tempted to prefix the function name with gen11_ so it is clearer it does not apply to earlier gens. Because if looking just at the diff out of context below, one can wonder if there is a functional change or not. There isn't, because there is a bailout for gen < 11 early in init_engine_mask(), but perhaps gen11 function name prefix would make this a bit more self-documenting. > + /* > + * In Gen11, only even numbered logical VDBOXes are hooked > + * up to an SFC (Scaler & Format Converter) unit. > + * In Gen12, Even numbered phyical instance always are connected physical > + * to an SFC. Odd numbered physical instances have SFC only if > + * previous even instance is fused off. > + */ > + if (GRAPHICS_VER(i915) == 12) { > + return (physical_vdbox % 2 == 0) || > + !(BIT(physical_vdbox - 1) & vdbox_mask); > + } else if (GRAPHICS_VER(i915) == 11) { > + return logical_vdbox % 2 == 0; > + } Not need for curlies on these branches. > + > + MISSING_CASE(GRAPHICS_VER(i915)); > + return false; > +} > + > /* > * Determine which engines are fused off in our particular hardware. > * Note that we have a catch-22 situation where we need to be able to access > @@ -493,13 +515,9 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > continue; > } > > - /* > - * In Gen11, only even numbered logical VDBOXes are > - * hooked up to an SFC (Scaler & Format Converter) unit. > - * In TGL each VDBOX has access to an SFC. > - */ > - if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0) > + if (vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask)) > gt->info.vdbox_sfc_access |= BIT(i); > + logical_vdbox++; > } > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", > vdbox_mask, VDBOX_MASK(gt)); > Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx