Re: [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts)

Tvrtko Ursulin
2021-07-02T12:43:08Z

On 01/07/2021 21:23, Matt Roper wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Xe_HP can have a lot of extra media engines. This patch adds the
> interrupt handler support for them.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index c13462274fe8..b2de83be4d97 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -184,7 +184,13 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
> + intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
> + intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0);
> + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> + intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0);
>
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> @@ -218,8 +224,13 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
> intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
> intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
> + intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask);
> + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
> + intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask);
> intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);

Poor 0-1 sandwiched between 4-7 and 2-3. ;) With hopefully order restored:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

> -
> + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> + intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask);
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS itself
> * is enabled/disabled.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d4546e871833..cb1716b6ce72 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8076,7 +8076,10 @@ enum {
> #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
> #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
> #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
> +#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
> +#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
> #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
> +#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
> #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
> #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
>