Re: [Intel-gfx] [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC

Lucas De Marchi
2021-07-01T22:19:20Z

On Thu, Jul 01, 2021 at 01:23:39PM -0700, Matt Roper wrote:
>From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
>
>In Gen12 there are various fuse combinations and in each configuration
>vdbox engine may be connected to SFC depending on which engines are
>available, so we need to set the SFC capability based on fuse value from
>the hardware. Even numbered phyical instance always have SFC, odd
>numbered physical instances have SFC only if previous even instance is
>fused off.
>
>Bspec: 48028

considering that in TGL we have physical instances 0 and 2 (both even),
we can use this logic, so it's correct correct for GRAPHICS_VER(i915) == 12.
Although I wonder ifwe should be using MEDIA_VER(i915) here.

>Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 ++++++++++++++++++-----
> 1 file changed, 24 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>index 151870d8fdd3..4ab2c9abb943 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>@@ -442,6 +442,28 @@ void intel_engines_free(struct intel_gt *gt)
> }
> }
>
>+static inline
>+bool vdbox_has_sfc(struct drm_i915_private *i915, unsigned int physical_vdbox,
>+ unsigned int logical_vdbox, u16 vdbox_mask)
>+{
>+ /*
>+ * In Gen11, only even numbered logical VDBOXes are hooked
>+ * up to an SFC (Scaler & Format Converter) unit.
>+ * In Gen12, Even numbered phyical instance always are connected
>+ * to an SFC. Odd numbered physical instances have SFC only if
>+ * previous even instance is fused off.
>+ */
>+ if (GRAPHICS_VER(i915) == 12) {
>+ return (physical_vdbox % 2 == 0) ||
>+ !(BIT(physical_vdbox - 1) & vdbox_mask);
>+ } else if (GRAPHICS_VER(i915) == 11) {
>+ return logical_vdbox % 2 == 0;
>+ }
>+
>+ MISSING_CASE(GRAPHICS_VER(i915));
>+ return false;
>+}
>+
> /*
> * Determine which engines are fused off in our particular hardware.
> * Note that we have a catch-22 situation where we need to be able to access
>@@ -493,13 +515,9 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> continue;
> }
>
>- /*
>- * In Gen11, only even numbered logical VDBOXes are
>- * hooked up to an SFC (Scaler & Format Converter) unit.
>- * In TGL each VDBOX has access to an SFC.
>- */
>- if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
>+ if (vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
> gt->info.vdbox_sfc_access |= BIT(i);
>+ logical_vdbox++;
> }
> drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> vdbox_mask, VDBOX_MASK(gt));
>--
>2.25.4
>
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