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Wed, 6 Apr 2022 10:16:56 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Wed, 6 Apr 2022 10:16:55 -0700 Received: from fmsmsx611.amr.corp.intel.com ([10.18.126.91]) by fmsmsx611.amr.corp.intel.com ([10.18.126.91]) with mapi id 15.01.2308.027; Wed, 6 Apr 2022 10:16:55 -0700 From: "Srivatsa, Anusha" To: "De Marchi, Lucas" Thread-Topic: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions Thread-Index: AQHYSREPDOLLoNL0skGRZsHFIgKPeqziEeYAgAEN4vA= Date: Wed, 6 Apr 2022 17:16:55 +0000 Message-ID: References: <20220405171429.3149199-1-anusha.srivatsa@intel.com> <20220405180242.naisj5g2edrhrfsi@ldmartin-desk2> In-Reply-To: <20220405180242.naisj5g2edrhrfsi@ldmartin-desk2> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.6.401.20 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.22.254.132] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: De Marchi, Lucas > Sent: Tuesday, April 5, 2022 11:03 AM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restriction= s >=20 > On Tue, Apr 05, 2022 at 10:14:29AM -0700, Anusha Srivatsa wrote: > >Bspec has added some steps that check for DMC MMIO range before > >programming them. > > > >v2: Fix for CI failure for v1 > > > >Cc: Lucas De Marchi > >Signed-off-by: Anusha Srivatsa > >--- > > drivers/gpu/drm/i915/display/intel_dmc.c | 42 > ++++++++++++++++++++++++ > > 1 file changed, 42 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c > >b/drivers/gpu/drm/i915/display/intel_dmc.c > >index 257cf662f9f4..05d8e90854ec 100644 > >--- a/drivers/gpu/drm/i915/display/intel_dmc.c > >+++ b/drivers/gpu/drm/i915/display/intel_dmc.c > >@@ -103,6 +103,18 @@ MODULE_FIRMWARE(BXT_DMC_PATH); > > #define DMC_V1_MAX_MMIO_COUNT 8 > > #define DMC_V3_MAX_MMIO_COUNT 20 > > #define DMC_V1_MMIO_START_RANGE 0x80000 > >+#define TGL_MAIN_MMIO_START 0x8F000 > >+#define TGL_MAIN_MMIO_END 0x8FFFF > >+#define TGL_PIPEA_MMIO_START 0x92000 > >+#define TGL_PIPEA_MMIO_END 0x93FFF > >+#define TGL_PIPEB_MMIO_START 0x96000 > >+#define TGL_PIPEB_MMIO_END 0x97FFF > >+#define TGL_PIPEC_MMIO_START 0x9A000 > >+#define TGL_PIPEC_MMIO_END 0x9BFFF > >+#define TGL_PIPED_MMIO_START 0x9E000 > >+#define TGL_PIPED_MMIO_END 0x9FFFF > >+#define ADLP_PIPE_MMIO_START 0x5F000 > >+#define ADLP_PIPE_MMIO_END 0x5FFFF > > > > struct intel_css_header { > > /* 0x09 for DMC */ > >@@ -374,6 +386,30 @@ static void dmc_set_fw_offset(struct intel_dmc > *dmc, > > } > > } > > > >+static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, const > >+u32 *mmioaddr, > >+u32 mmio_count) > >+{ > >+ struct drm_i915_private *i915 =3D container_of(dmc, typeof(*i915), > dmc); > >+ int i; > >+ > >+ if (IS_DG2(i915) || IS_ALDERLAKE_P(i915)) { > >+ for (i =3D 0; i < mmio_count; i++) { > >+ if (!((mmioaddr[i] >=3D TGL_MAIN_MMIO_START && > mmioaddr[i] <=3D TGL_MAIN_MMIO_END) || > >+ (mmioaddr[i] >=3D ADLP_PIPE_MMIO_START && > mmioaddr[i] <=3D ADLP_PIPE_MMIO_END))) > >+ return false; > >+ } > >+ } else if (IS_TIGERLAKE(i915) || IS_DG1(i915) || > IS_ALDERLAKE_S(i915)) > >+ for (i =3D 0; i < mmio_count; i++) { > >+ if (!((mmioaddr[i] >=3D TGL_MAIN_MMIO_START && > mmioaddr[i] <=3D TGL_MAIN_MMIO_END) || > >+ (mmioaddr[i] >=3D TGL_PIPEA_MMIO_START && > mmioaddr[i] <=3D TGL_PIPEA_MMIO_END) || > >+ (mmioaddr[i] >=3D TGL_PIPEB_MMIO_START && > mmioaddr[i] <=3D TGL_PIPEB_MMIO_END) || > >+ (mmioaddr[i] >=3D TGL_PIPEC_MMIO_START && > mmioaddr[i] <=3D TGL_PIPEC_MMIO_END) || > >+ (mmioaddr[i] >=3D TGL_PIPED_MMIO_START && > mmioaddr[i] <=3D TGL_PIPEC_MMIO_END))) > >+ return false; >=20 > wonder if we should check for each pipe DMC range independently rather > than just checking all the ranges. Can convert this to a switch case in that scenario. "If it is PIPE A then = it must be within this range". But it will be 2 switches one for DG2 and AD= LP and one for TGL and the rest which have individual ranges for every pipe= .=20 > >+ } > >+ return true; > >+} > >+ > > static u32 parse_dmc_fw_header(struct intel_dmc *dmc, > > const struct intel_dmc_header_base > *dmc_header, > > size_t rem_size, u8 dmc_id) > >@@ -443,6 +479,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc > *dmc, > > return 0; > > } > > > >+ if (dmc_header->header_ver =3D=3D 3) { >=20 > this also needs to be done for ver 2 For v2 though there has been no update about the start range. As in this mm= io range is different from the RAM_MMIO_START range. Anusha=20 =20 > Lucas De Marchi