[PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Imre Deak]

As described in the code comment, I couldn't set the minimum RPS
frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
Fix this by clamping the minimum value to the first one that was
accepted on my machine. This fixes at least the pm_rpm basic-api and
min-max-config subtests.

Testcase: igt/pm_rps
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45c786f..7a1112f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 
 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
-	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
+	u32 val;
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
+	/*
+	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
+	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
+	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
+	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
+	 * to make sure it matches what Punit accepts.
+	 */
+	return max_t(u32, val, 0xc0);
 }
 
 /* Check that the pctx buffer wasn't move under us. */
-- 
1.8.4

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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  364/364              364/364
ILK                 -2              366/366              364/366
SNB                                  450/450              450/450
IVB              +17                 481/498              498/498
BYT                                  289/289              289/289
HSW                                  564/564              564/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt_kms_flip_flip-vs-dpms-interruptible      PASS(2, M37M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_rcs-flip-vs-panning      PASS(2, M37M26)      DMESG_WARN(1, M26)
 IVB  igt_kms_3d      DMESG_WARN(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-128x128-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-128x128-random      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-128x128-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-256x256-offscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-256x256-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-256x256-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-64x64-offscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-64x64-onscreen      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-64x64-random      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-64x64-sliding      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_cursor_crc_cursor-size-change      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_fence_pin_leak      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_rotation_crc_primary-rotation      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
 IVB  igt_kms_rotation_crc_sprite-rotation      NSPT(1, M34)PASS(10, M4M34M21)      PASS(1, M21)
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Daniel Vetter]

On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> As described in the code comment, I couldn't set the minimum RPS
> frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> Fix this by clamping the minimum value to the first one that was
> accepted on my machine. This fixes at least the pm_rpm basic-api and
> min-max-config subtests.
> 
> Testcase: igt/pm_rps
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Isn't there a bugzilla for this, too?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 45c786f..7a1112f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>  
>  static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>  {
> -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> +	u32 val;
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> +	/*
> +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
> +	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
> +	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
> +	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
> +	 * to make sure it matches what Punit accepts.
> +	 */
> +	return max_t(u32, val, 0xc0);
>  }
>  
>  /* Check that the pctx buffer wasn't move under us. */
> -- 
> 1.8.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Imre Deak]

On Fri, 2014-12-05 at 21:58 +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > As described in the code comment, I couldn't set the minimum RPS
> > frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> > Fix this by clamping the minimum value to the first one that was
> > accepted on my machine. This fixes at least the pm_rpm basic-api and
> > min-max-config subtests.
> > 
> > Testcase: igt/pm_rps
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> 
> Isn't there a bugzilla for this, too?

I didn't check this:/ There are some that may be fixed, or at least
partially fixed. I just list all pm_rps bugs here, they are all worth
rechecking imo, although the non-VLV/CHV ones are less likely to be
related:

Reference: https://bugs.freedesktop.org/show_bug.cgi?id=80704
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=86654
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=86363
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=84896
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=77869


> -Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 45c786f..7a1112f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> >  
> >  static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  {
> > -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > +	u32 val;
> > +
> > +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > +	/*
> > +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
> > +	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
> > +	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
> > +	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
> > +	 * to make sure it matches what Punit accepts.
> > +	 */
> > +	return max_t(u32, val, 0xc0);
> >  }
> >  
> >  /* Check that the pctx buffer wasn't move under us. */
> > -- 
> > 1.8.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Imre Deak]

On Fri, 2014-12-05 at 23:16 +0200, Imre Deak wrote:
> On Fri, 2014-12-05 at 21:58 +0100, Daniel Vetter wrote:
> > On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > > As described in the code comment, I couldn't set the minimum RPS
> > > frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> > > Fix this by clamping the minimum value to the first one that was
> > > accepted on my machine. This fixes at least the pm_rpm basic-api and
> > > min-max-config subtests.
> > > 
> > > Testcase: igt/pm_rps
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > Isn't there a bugzilla for this, too?
> 
> I didn't check this:/ There are some that may be fixed, or at least
> partially fixed. I just list all pm_rps bugs here, they are all worth
> rechecking imo, although the non-VLV/CHV ones are less likely to be
> related:
> 
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=80704
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=86654
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=86363
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=84896
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=77869

Sorry, I meant the above for the 3 igt patches actually. For this
particular one I haven't found any ticket.

> 
> 
> > -Daniel
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> > >  1 file changed, 11 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 45c786f..7a1112f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> > >  
> > >  static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> > >  {
> > > -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > > +	u32 val;
> > > +
> > > +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > > +	/*
> > > +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
> > > +	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
> > > +	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
> > > +	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
> > > +	 * to make sure it matches what Punit accepts.
> > > +	 */
> > > +	return max_t(u32, val, 0xc0);
> > >  }
> > >  
> > >  /* Check that the pctx buffer wasn't move under us. */
> > > -- 
> > > 1.8.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 


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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Ville Syrjälä]

On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> As described in the code comment, I couldn't set the minimum RPS
> frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> Fix this by clamping the minimum value to the first one that was
> accepted on my machine. This fixes at least the pm_rpm basic-api and
> min-max-config subtests.
> 
> Testcase: igt/pm_rps
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 45c786f..7a1112f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>  
>  static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
>  {
> -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> +	u32 val;
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> +	/*
> +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
> +	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
> +	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
> +	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
> +	 * to make sure it matches what Punit accepts.
> +	 */
> +	return max_t(u32, val, 0xc0);

Matches what I see on this ffrd as well. But this too has czclk==266.
Would be interesting to see what happens with other czclks. Anyone
have a byt w/ 1333 memory?

>  }
>  
>  /* Check that the pctx buffer wasn't move under us. */
> -- 
> 1.8.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Ville Syrjälä]

On Fri, Dec 05, 2014 at 11:23:29PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > As described in the code comment, I couldn't set the minimum RPS
> > frequency on my BYT-M B0 to the minimum allowed as reported by Punit.
> > Fix this by clamping the minimum value to the first one that was
> > accepted on my machine. This fixes at least the pm_rpm basic-api and
> > min-max-config subtests.
> > 
> > Testcase: igt/pm_rps
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> >  1 file changed, 11 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 45c786f..7a1112f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
> >  
> >  static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
> >  {
> > -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > +	u32 val;
> > +
> > +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
> > +	/*
> > +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
> > +	 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
> > +	 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
> > +	 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
> > +	 * to make sure it matches what Punit accepts.
> > +	 */
> > +	return max_t(u32, val, 0xc0);
> 
> Matches what I see on this ffrd as well. But this too has czclk==266.
> Would be interesting to see what happens with other czclks. Anyone
> have a byt w/ 1333 memory?

I guess we never found a 333 SKU. Since the patch is at least correct
for every VLV machine I've ever seen, I think we can go with it.

Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> >  }
> >  
> >  /* Check that the pctx buffer wasn't move under us. */
> > -- 
> > 1.8.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH] drm/i915: vlv: clamp minimum RPS frequency to what Punit allows

[Imre Deak]

On ma, 2015-12-07 at 16:40 +0200, Ville Syrjälä wrote:
> On Fri, Dec 05, 2014 at 11:23:29PM +0200, Ville Syrjälä wrote:
> > On Thu, Dec 04, 2014 at 06:39:35PM +0200, Imre Deak wrote:
> > > As described in the code comment, I couldn't set the minimum RPS
> > > frequency on my BYT-M B0 to the minimum allowed as reported by
> > > Punit.
> > > Fix this by clamping the minimum value to the first one that was
> > > accepted on my machine. This fixes at least the pm_rpm basic-api
> > > and
> > > min-max-config subtests.
> > > 
> > > Testcase: igt/pm_rps
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
> > >  1 file changed, 11 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 45c786f..7a1112f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5039,7 +5039,17 @@ static int valleyview_rps_rpe_freq(struct
> > > drm_i915_private *dev_priv)
> > >  
> > >  static int valleyview_rps_min_freq(struct drm_i915_private
> > > *dev_priv)
> > >  {
> > > -	return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) &
> > > 0xff;
> > > +	u32 val;
> > > +
> > > +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) &
> > > 0xff;
> > > +	/*
> > > +	 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the
> > > minimum value
> > > +	 * for the minimum frequency in GPLL mode is 0xc1.
> > > Contrary to this on
> > > +	 * a BYT-M B0 the above register contains 0xbf. Moreover
> > > when setting
> > > +	 * a frequency Punit will not allow values below 0xc0.
> > > Clamp it 0xc0
> > > +	 * to make sure it matches what Punit accepts.
> > > +	 */
> > > +	return max_t(u32, val, 0xc0);
> > 
> > Matches what I see on this ffrd as well. But this too has
> > czclk==266.
> > Would be interesting to see what happens with other czclks. Anyone
> > have a byt w/ 1333 memory?
> 
> I guess we never found a 333 SKU. Since the patch is at least correct
> for every VLV machine I've ever seen, I think we can go with it.
> 
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks, I pushed the patch to dinq. The igt/pm_rps subtest that failed
because of this issue doesn't fail any more due to a change in the
driver that caches the current frequency that was last set. But the
actual frequency is something that we also want to check eventually, so
this fix is needed for that. I updated the commit message accordingly
while merging it.

> > >  }
> > >  
> > >  /* Check that the pctx buffer wasn't move under us. */
> > > -- 
> > > 1.8.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> 
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