Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015227452

Tvrtko Ursulin
2022-01-28T08:44:31Z

On 27/01/2022 19:48, Matt Roper wrote:
> Note that the bspec doesn't list the bit we're programming here (bit 11)
> as being present on DG2, but we've confirmed with the hardware team that
> this is a documentation mistake and the bit does indeed exist on all
> Xe_HP-based platforms.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 748b2daf043f..065dc1c2bb71 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2045,6 +2045,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;

For a rainy day, look above i915 = engine->i915..

> + if (IS_DG2(engine->i915)) {

engine->i915

> + /* Wa_14015227452:dg2 */
> + wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
> + }
> +
> if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {

engine->i915

:)

Regards,

Tvrtko

> /* Wa_14013392000:dg2_g11 */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2e4dd9db63fe..38c23dd36300 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8927,6 +8927,7 @@ enum {
>
> #define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
> #define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
> +#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
> #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> #define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
>