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* [RFC PATCH 00/39] drm/i915/display: Add MTL+ platforms to support dpll framework
@ 2025-10-01  8:28 Mika Kahola
  2025-10-01  8:28 ` [RFC PATCH 01/39] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros Mika Kahola
                   ` (40 more replies)
  0 siblings, 41 replies; 57+ messages in thread
From: Mika Kahola @ 2025-10-01  8:28 UTC (permalink / raw)
  To: intel-gfx, intel-xe; +Cc: Mika Kahola

This series introduces support for the DPLL framework on MTL+ platforms.
It begins with a set of cleanups and helper refactors, then gradually
adds the necessary infrastructure for dpll framework, followed by
extensions to support additional platforms. The final patch enables the
DPLL framework for MTL+.

The patches are organized as follows:

* Fixes and refactoring
* Tracking additional PLL/PHY HW state in the PLL SW state
* Align the Cx0 PHY PLL state compute/readout and enabling functions on MTL+
  as expected by the PLL manager
* Add the Cx0 PHY PLL manager/PLL hooks for MTL+
* Enable the PLL manager for MTL+ platforms

Note:
This series does not include the following features that would
require attention as a follow up series

* Add support for:
  - CMTG
  - C20 PHY PLL on port B
* Decouple PLL code from encoders for better isolation of PLL code internals

Imre Deak (22):
  drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE
    field macros
  drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag
    macro
  drm/i915/display: Sanitize
    PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro
  drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL
    flag macro
  drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming
  drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming
  drm/i915/display: Add missing clock to C10 PHY state compute/HW
    readout
  drm/i915/display: Factor out C10 msgbus access start/end helpers
  drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
  drm/i915/display: Sanitize calculating C20 PLL state from tables
  drm/i915/display: Track the C20 PHY VDR state in the PLL state
  drm/i915/display: Move definition of Cx0 PHY functions earlier
  drm/i915/display: Add macro to get DDI port width from a register
    value
  drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL
    state
  drm/i915/display: Sanitize C10 PHY PLL SSC register setup
  drm/i915/display: Read out the Cx0 PHY SSC enabled state
  drm/i915/display: Determine Cx0 PLL DP mode from PLL state
  drm/i915/display: Determine Cx0 PLL port clock from PLL state
  drm/i915/display: Zero Cx0 PLL state before compute and HW readout
  drm/i915/display: Print additional Cx0 PLL HW state
  drm/i915/display: PLL verify debug state print
  drm/i915/display: Add Thunderbolt support

Mika Kahola (17):
  drm/i915/display: Rename TBT functions to be ICL specific
  drm/i915/display: Remove state verification
  drm/i915/display: PLL information for MTL+
  drm/i915/display: Update C10/C20 state calculation
  drm/i915/display: Compute plls for MTL+ platform
  drm/i915/display: MTL+ .get_dplls
  drm/i915/display: MTL+ .put_dplls
  drm/i915/display: Add .update_active_dpll
  drm/i915/display: Add .update_dpll_ref_clks
  drm/i915/display: Add .dump_hw_state
  drm/i915/display: Add .compare_hw_state
  drm/i915/display: Add .get_hw_state to MTL+ platforms
  drm/i915/display: Add .get_freq to MTL+ platforms
  drm/i915/display: Add .crtc_get_dpll hook
  drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
  drm/i915/display: Get configuration for C10 and C20
  drm/i915/display: Enable dpll framework for MTL+

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 897 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  25 +-
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  76 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  32 -
 .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 297 +++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 .../drm/i915/display/intel_snps_hdmi_pll.c    |   2 +
 11 files changed, 884 insertions(+), 494 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 57+ messages in thread

end of thread, other threads:[~2025-10-20 10:51 UTC | newest]

Thread overview: 57+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-01  8:28 [RFC PATCH 00/39] drm/i915/display: Add MTL+ platforms to support dpll framework Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 01/39] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros Mika Kahola
2025-10-01  8:52   ` Jani Nikula
2025-10-01  8:57     ` Raag Jadav
2025-10-01  9:57       ` Jani Nikula
2025-10-01 10:01         ` Kahola, Mika
2025-10-01  8:28 ` [RFC PATCH 02/39] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 03/39] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE " Mika Kahola
2025-10-01  8:49   ` Jani Nikula
2025-10-01  8:28 ` [RFC PATCH 04/39] drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL " Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 05/39] drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 06/39] drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 07/39] drm/i915/display: Add missing clock to C10 PHY state compute/HW readout Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 08/39] drm/i915/display: Rename TBT functions to be ICL specific Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 09/39] drm/i915/display: Factor out C10 msgbus access start/end helpers Mika Kahola
2025-10-01  8:55   ` Jani Nikula
2025-10-01  8:28 ` [RFC PATCH 10/39] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 11/39] drm/i915/display: Sanitize calculating C20 PLL state from tables Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 12/39] drm/i915/display: Track the C20 PHY VDR state in the PLL state Mika Kahola
2025-10-01  9:03   ` Jani Nikula
2025-10-01  8:28 ` [RFC PATCH 13/39] drm/i915/display: Move definition of Cx0 PHY functions earlier Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 14/39] drm/i915/display: Add macro to get DDI port width from a register value Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 15/39] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state Mika Kahola
2025-10-01  9:13   ` Jani Nikula
2025-10-01 12:09     ` Imre Deak
2025-10-01  8:28 ` [RFC PATCH 16/39] drm/i915/display: Sanitize C10 PHY PLL SSC register setup Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 17/39] drm/i915/display: Read out the Cx0 PHY SSC enabled state Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 18/39] drm/i915/display: Determine Cx0 PLL DP mode from PLL state Mika Kahola
2025-10-01  9:16   ` Jani Nikula
2025-10-16 18:04     ` Ville Syrjälä
2025-10-20 10:51       ` Jani Nikula
2025-10-01  8:28 ` [RFC PATCH 19/39] drm/i915/display: Determine Cx0 PLL port clock " Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 20/39] drm/i915/display: Zero Cx0 PLL state before compute and HW readout Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 21/39] drm/i915/display: Print additional Cx0 PLL HW state Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 22/39] drm/i915/display: Remove state verification Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 23/39] drm/i915/display: PLL information for MTL+ Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 24/39] drm/i915/display: Update C10/C20 state calculation Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 25/39] drm/i915/display: Compute plls for MTL+ platform Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 26/39] drm/i915/display: MTL+ .get_dplls Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 27/39] drm/i915/display: MTL+ .put_dplls Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 28/39] drm/i915/display: Add .update_active_dpll Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 29/39] drm/i915/display: Add .update_dpll_ref_clks Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 30/39] drm/i915/display: Add .dump_hw_state Mika Kahola
2025-10-01  9:33   ` Jani Nikula
2025-10-02  9:12     ` Kahola, Mika
2025-10-01  8:28 ` [RFC PATCH 31/39] drm/i915/display: Add .compare_hw_state Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 32/39] drm/i915/display: Add .get_hw_state to MTL+ platforms Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 33/39] drm/i915/display: Add .get_freq " Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 34/39] drm/i915/display: Add .crtc_get_dpll hook Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 35/39] drm/i915/display: PLL verify debug state print Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 36/39] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 37/39] drm/i915/display: Get configuration for C10 and C20 Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 38/39] drm/i915/display: Add Thunderbolt support Mika Kahola
2025-10-01  8:28 ` [RFC PATCH 39/39] drm/i915/display: Enable dpll framework for MTL+ Mika Kahola
2025-10-01 10:50 ` ✓ i915.CI.BAT: success for drm/i915/display: Add MTL+ platforms to support dpll framework Patchwork
2025-10-07  0:17 ` ✗ i915.CI.Full: failure " Patchwork
2025-10-07 11:17   ` Kahola, Mika

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