From: Jani Nikula <jani.nikula@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [CI] drm/i915/display: change pipe allocation order for discrete platforms
Date: Thu, 02 Apr 2026 12:43:57 +0300 [thread overview]
Message-ID: <c14a06980bbea7ab14b070b4840a92dc593a0fa7@intel.com> (raw)
In-Reply-To: <acqYWkrs5b3MOrnO@intel.com>
On Mon, 30 Mar 2026, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Mar 30, 2026 at 02:37:47PM +0300, Jani Nikula wrote:
>> On Mon, 16 Mar 2026, Jani Nikula <jani.nikula@intel.com> wrote:
>> > When big joiner is enabled, it reserves the adjacent pipe as the
>> > secondary pipe. This happens without the user space knowing, and
>> > subsequent attempts at using the CRTC with that pipe will fail. If the
>> > user space does not have a coping mechanism, i.e. trying another CRTC,
>> > this leads to a black screen.
>> >
>> > Try to reduce the impact of the problem on discrete platforms by mapping
>> > the CRTCs to pipes in order A, C, B, and D. If the user space reserves
>> > CRTCs in order, this should trick it to using pipes that are more likely
>> > to be available for and after joining.
>> >
>> > Limit this to discrete platforms, which have four pipes, and no eDP, a
>> > combination that should benefit the most with least drawbacks.
>>
>> Ville, I think it's time to review and, pretty soon, merge this.
>>
>> Our IGT changes to deconflate CRTCs and pipes have been merged, and
>> there's the removal of invalid igt_crtc_t at [1] left. The trybot CI
>> results on i915 for swapping pipes B and C on all platforms, not just
>> discrete like here, didn't break anything either anymore [2].
>>
>> I'm contemplating slapping Cc: stable on this too.
>>
>> There's the FIXME on the CRTC index warning.
>
> IIRC we already concluded that the WARN is unnecessary. I'd have to
> look through the previous mails to see what I actually said there.
>
>> With the A+C and B+D
>> pairing there's no issue, the CRTC indexes remain in that order. But can
>> we ever really end up with B+C pairing?
>
> It might be rare if userspace picks crtcs in order. But IIRC we had
> bugs where it was clear userspace was just picking random crtcs willy
> nilly. IIRC it was sway doing it, and I think I even proposed a
> uapi documentation update to suggest using crtcs in order. Can't
> remember that happened to that one.
>
> But I think we still want the "walk the crtcs in pipe order" change,
> mainly to keep the more optimal commit sequence. Also I'm not quite
> 100% convinced we don't have some subtle assumption somewhere about
> the order.
You mean convert all for_each_intel_crtc*() iterators to pipe order?
BR,
Jani.
>
> BTW I just realized that DG2 may also get a slight extra benefit from
> the reordering because A+C has twice the dbuf space compared to A+B.
--
Jani Nikula, Intel
next prev parent reply other threads:[~2026-04-02 9:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-16 12:18 [CI] drm/i915/display: change pipe allocation order for discrete platforms Jani Nikula
2026-03-17 8:55 ` ✓ i915.CI.BAT: success for drm/i915/display: change pipe allocation order for discrete platforms (rev4) Patchwork
2026-03-17 15:52 ` ✗ i915.CI.Full: failure " Patchwork
2026-03-30 11:37 ` [CI] drm/i915/display: change pipe allocation order for discrete platforms Jani Nikula
2026-03-30 15:35 ` Ville Syrjälä
2026-04-02 9:43 ` Jani Nikula [this message]
2026-04-02 10:18 ` Ville Syrjälä
2026-04-02 13:33 ` Ville Syrjälä
-- strict thread matches above, loose matches on Subject: below --
2026-02-06 12:37 Jani Nikula
2026-02-09 15:10 ` Jani Nikula
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