[PATCH 0/8] drm-intel-collector - update

[PATCH 0/8] drm-intel-collector - update

[Rodrigo Vivi]

This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector

Here goes the update list in order for better reviewers assignment:

Patch     drm/i915: Remove pinned check from madvise_ioctl - Reviewer:
Patch     drm/i915: Remove unneeded check on execlist ringbuf alloc - Reviewer:
Patch     drm/i915: Support for higher DSI clk - Reviewer:
Patch     drm/i915: Changes required to enable DSI Video Mode on CHT - Reviewer:
Patch     drm/i915: Remove duplicated intel_fbc_update calls. - Reviewer:
Patch     drm/i915: Attach a PSR property on eDP - Reviewer:
Patch     drm/i915/skl: Disallow tiling changes during page flip - Reviewer:
Patch     drm/i915/skl: Select DDIA lane capability based upon vbt - Reviewer:

2 rounds of collector: Finished discussions from Mar 27 to Apr 10 and from Apr 10 to Apr 23.

Rodrigo.


Chris Wilson (1):
  drm/i915: Remove pinned check from madvise_ioctl

Gaurav K Singh (2):
  drm/i915: Support for higher DSI clk
  drm/i915: Changes required to enable DSI Video Mode on CHT

Mika Kuoppala (1):
  drm/i915: Remove unneeded check on execlist ringbuf alloc

Rodrigo Vivi (2):
  drm/i915: Remove duplicated intel_fbc_update calls.
  drm/i915: Attach a PSR property on eDP

Tvrtko Ursulin (1):
  drm/i915/skl: Disallow tiling changes during page flip

sonika.jindal@intel.com (1):
  drm/i915/skl: Select DDIA lane capability based upon vbt

 Documentation/DocBook/drm.tmpl       | 10 +++++++-
 drivers/gpu/drm/i915/i915_drv.h      |  2 ++
 drivers/gpu/drm/i915/i915_gem.c      |  6 -----
 drivers/gpu/drm/i915/intel_bios.c    |  4 +++
 drivers/gpu/drm/i915/intel_bios.h    |  1 +
 drivers/gpu/drm/i915/intel_ddi.c     |  8 ++++++
 drivers/gpu/drm/i915/intel_display.c | 29 +++++++++++++---------
 drivers/gpu/drm/i915/intel_dp.c      |  1 +
 drivers/gpu/drm/i915/intel_drv.h     |  2 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c | 47 +++++++++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.c     | 29 ++++++++++------------
 drivers/gpu/drm/i915/intel_psr.c     | 47 ++++++++++++++++++++++++++++++++++++
 12 files changed, 138 insertions(+), 48 deletions(-)

-- 
2.1.0

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[PATCH 1/8] drm/i915: Remove pinned check from madvise_ioctl

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

We don't need to incur the overhead of checking whether the object is
pinned prior to changing its madvise. If the object is pinned, the
madvise will not take effect until it is unpinned and so we cannot free
the pages being pointed at by hardware. Marking a pinned object with
allocated pages as DONTNEED will not trigger any undue warnings. The check
is therefore superfluous, and by removing it we can remove a linear walk
over all the vma the object has.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f128ed8..6c6b184 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4419,11 +4419,6 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 		goto unlock;
 	}
 
-	if (i915_gem_obj_is_pinned(obj)) {
-		ret = -EINVAL;
-		goto out;
-	}
-
 	if (obj->pages &&
 	    obj->tiling_mode != I915_TILING_NONE &&
 	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
@@ -4442,7 +4437,6 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 
 	args->retained = obj->madv != __I915_MADV_PURGED;
 
-out:
 	drm_gem_object_unreference(&obj->base);
 unlock:
 	mutex_unlock(&dev->struct_mutex);
-- 
2.1.0

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[PATCH 2/8] drm/i915: Remove unneeded check on execlist ringbuf alloc

[Rodrigo Vivi]

From: Mika Kuoppala <mika.kuoppala@linux.intel.com>

We just allocated the intel_ringbuffer with kzalloc. There
is no chance of the ringbuf->obj being other than NULL
so remove the redudant check.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0fa9209..83a529c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1927,25 +1927,22 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
 	ringbuf->last_retired_head = -1;
 	intel_ring_update_space(ringbuf);
 
-	if (ringbuf->obj == NULL) {
-		ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+	ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+	if (ret) {
+		DRM_DEBUG_DRIVER(
+			"Failed to allocate ringbuffer obj %s: %d\n",
+			ring->name, ret);
+		goto error_free_rbuf;
+	}
+
+	if (is_global_default_ctx) {
+		ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
 		if (ret) {
-			DRM_DEBUG_DRIVER(
-				"Failed to allocate ringbuffer obj %s: %d\n",
+			DRM_ERROR(
+				"Failed to pin and map ringbuffer %s: %d\n",
 				ring->name, ret);
-			goto error_free_rbuf;
+			goto error_destroy_rbuf;
 		}
-
-		if (is_global_default_ctx) {
-			ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
-			if (ret) {
-				DRM_ERROR(
-					"Failed to pin and map ringbuffer %s: %d\n",
-					ring->name, ret);
-				goto error_destroy_rbuf;
-			}
-		}
-
 	}
 
 	ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
-- 
2.1.0

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[PATCH 3/8] drm/i915: Support for higher DSI clk

[Rodrigo Vivi]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

For MIPI panels requiring higher DSI clk, values needs to be added
in lfsr_converts table for getting the correct values of pll ctrl
and dividor values which gets programmed in cck regs, otherwise DSI
PLL does not get locked leading to no display on the MIPI panel.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 3622d0b..471336d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -46,8 +46,8 @@ struct dsi_mnp {
 static const u32 lfsr_converts[] = {
 	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
 	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
-	106, 53, 282, 397, 354, 227, 113, 56, 284, 142,		/* 81 - 90 */
-	71, 35							/* 91 - 92 */
+	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
+	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
 };
 
 #ifdef DSI_CLK_FROM_RR
-- 
2.1.0

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[PATCH 4/8] drm/i915: Changes required to enable DSI Video Mode on CHT

[Rodrigo Vivi]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 43 +++++++++++++++++++++++++++---------
 1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 471336d..5e44c9b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
 
 #endif
 
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
+static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
+			u32 dsi_clk, struct dsi_mnp *dsi_mnp)
 {
 	u32 m, n, p;
 	u32 ref_clk;
@@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
 	u32 calc_m;
 	u32 calc_p;
 	u32 m_seed;
+	u32 m_start;
+	u32 m_limit;
+	u32 n_limit;
+	u32 p_limit;
 
 	/* dsi_clk is expected in KHZ */
 	if (dsi_clk < 300000 || dsi_clk > 1150000) {
@@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
 		return -ECHRNG;
 	}
 
-	ref_clk = 25000;
+	if (IS_CHERRYVIEW(dev_priv->dev)) {
+		ref_clk = 100000;
+		m_start = 70;
+		m_limit = 96;
+		n_limit = 4;
+		p_limit = 6;
+	} else if (IS_VALLEYVIEW(dev_priv->dev)) {
+		ref_clk = 25000;
+		m_start = 62;
+		m_limit = 92;
+		n_limit = 1;
+		p_limit = 6;
+	} else {
+		DRM_ERROR("Unsupported device\n");
+		return -ENODEV;
+	}
 	target_dsi_clk = dsi_clk;
 	error = 0xFFFFFFFF;
 	tmp_error = 0xFFFFFFFF;
 	calc_m = 0;
 	calc_p = 0;
 
-	for (m = 62; m <= 92; m++) {
-		for (p = 2; p <= 6; p++) {
+	for (m = m_start; m <= m_limit; m++) {
+		for (p = 2; p <= p_limit; p++) {
 			/* Find the optimal m and p divisors
 			   with minimal error +/- the required clock */
-			calc_dsi_clk = (m * ref_clk) / p;
+			calc_dsi_clk = (m * ref_clk) / (p * n_limit);
 			if (calc_dsi_clk == target_dsi_clk) {
 				calc_m = m;
 				calc_p = p;
@@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
 	}
 
 	m_seed = lfsr_converts[calc_m - 62];
-	n = 1;
+	n = n_limit;
 	dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
-	dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
-		m_seed << DSI_PLL_M1_DIV_SHIFT;
-
+	if (IS_CHERRYVIEW(dev_priv->dev))
+		dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
+				m_seed << DSI_PLL_M1_DIV_SHIFT;
+	else
+		dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+				m_seed << DSI_PLL_M1_DIV_SHIFT;
 	return 0;
 }
 
@@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
 				    intel_dsi->lane_count);
 
-	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
+	ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
 	if (ret) {
 		DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
 		return;
-- 
2.1.0

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[PATCH 5/8] drm/i915: Remove duplicated intel_fbc_update calls.

[Rodrigo Vivi]

With frontbuffer tracking taking care of fbc
we were duplicating fbc update call  on these cases here.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 12 ------------
 drivers/gpu/drm/i915/intel_drv.h     |  1 -
 2 files changed, 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 240092a..489a134 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4784,10 +4784,6 @@ intel_post_enable_primary(struct drm_crtc *crtc)
 	 */
 	hsw_enable_ips(intel_crtc);
 
-	mutex_lock(&dev->struct_mutex);
-	intel_fbc_update(dev);
-	mutex_unlock(&dev->struct_mutex);
-
 	/*
 	 * Gen2 reports pipe underruns whenever all planes are disabled.
 	 * So don't enable underrun reporting before at least some planes
@@ -13058,8 +13054,6 @@ intel_check_primary_plane(struct drm_plane *plane,
 		intel_crtc->atomic.fb_bits |=
 			INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
 
-		intel_crtc->atomic.update_fbc = true;
-
 		if (intel_wm_need_update(plane, &state->base))
 			intel_crtc->atomic.update_wm = true;
 	}
@@ -13185,12 +13179,6 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc)
 
 	intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
 
-	if (intel_crtc->atomic.update_fbc) {
-		mutex_lock(&dev->struct_mutex);
-		intel_fbc_update(dev);
-		mutex_unlock(&dev->struct_mutex);
-	}
-
 	if (intel_crtc->atomic.post_enable_primary)
 		intel_post_enable_primary(crtc);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ea3368e..d205f2f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -490,7 +490,6 @@ struct intel_crtc_atomic_commit {
 	/* Sleepable operations to perform after commit */
 	unsigned fb_bits;
 	bool wait_vblank;
-	bool update_fbc;
 	bool post_enable_primary;
 	unsigned update_sprite_watermarks;
 };
-- 
2.1.0

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[PATCH 6/8] drm/i915: Attach a PSR property on eDP

[Rodrigo Vivi]

Let userspace know the status of Panel Self-Refresh by virtue of a
property on the appropriate connector.

v2: Only attach the property if the driver is capable of PSR.
v3: Add docbook courtesy of Damien.
v4: Mark the initial value as 'unsupported' - it will be determined
    correctly when we later read the DCPD from the panel.
v5: Done by Rodrigo:
    	 - Add disabled state to match all cases
	 - Attach it anyway to eDP since it is started as unsupported
	 - Change prop name to PSR
	 - Add enum to make states more clear
	 - Rebased on intel_psr.c changing func name and fixing states
v6: Done by Rodrigo:
    	 - Revert name to Panel Self-Refresh
	 - Only report Enable/Disable since Active/Exit change so rapidily
	   triggering many uevents as Chris pointed out.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v4)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v6)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 Documentation/DocBook/drm.tmpl   | 10 ++++++++-
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_dp.c  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 47 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7c68ecc..72380a1 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2834,7 +2834,7 @@ void intel_crt_init(struct drm_device *dev)
 	<td valign="top" >TBD</td>
 	</tr>
 	<tr>
-	<td rowspan="21" valign="top" >i915</td>
+	<td rowspan="22" valign="top" >i915</td>
 	<td rowspan="2" valign="top" >Generic</td>
 	<td valign="top" >"Broadcast RGB"</td>
 	<td valign="top" >ENUM</td>
@@ -2986,6 +2986,14 @@ void intel_crt_init(struct drm_device *dev)
 	<td valign="top" >TBD</td>
 	</tr>
 	<tr>
+	<td valign="top" >eDP</td>
+	<td valign="top" >“Panel Self-Refresh”</td>
+	<td valign="top" >ENUM | IMMUTABLE</td>
+	<td valign="top" >{ "Unsupported", "Idle", "Active" }</td>
+	<td valign="top" >Connector</td>
+	<td valign="top" >Whether the eDP panel supports using self-refresh, which is a power saving mode for static displays as the panel is able to read from its own buffer rather than require the host to send the same frame on every vertical refresh, and whether it is idle or active</td>
+	</tr>
+	<tr>
 	<td rowspan="2" valign="top" >CDV gma-500</td>
 	<td rowspan="2" valign="top" >Generic</td>
 	<td valign="top" >"Broadcast RGB"</td>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1321956..54703bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -906,6 +906,7 @@ struct i915_psr {
 	unsigned busy_frontbuffer_bits;
 	bool psr2_support;
 	bool aux_frame_sync;
+	struct drm_property *property;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eca82cf..1a09322 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5045,6 +5045,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 	intel_dp->color_range_auto = true;
 
 	if (is_edp(intel_dp)) {
+		intel_attach_psr_property(connector);
 		drm_mode_create_scaling_mode_property(connector->dev);
 		drm_object_attach_property(
 			&connector->base,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d205f2f..066f2ab 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1301,6 +1301,7 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
+void intel_attach_psr_property(struct drm_connector *connector);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ee0fa5..0432bab 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,6 +56,50 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+enum psr_state {
+	PSR_UNSUPPORTED = -1,
+	PSR_DISABLED,
+	PSR_ENABLED,
+};
+
+static const struct drm_prop_enum_list psr_names[] = {
+	{ PSR_UNSUPPORTED, "Unsupported" },
+	{ PSR_DISABLED, "Disabled" },
+	{ PSR_ENABLED, "Enabled" },
+};
+
+void intel_attach_psr_property(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_property *prop;
+
+	prop = dev_priv->psr.property;
+	if (prop == NULL) {
+		prop = drm_property_create_enum(dev,
+						DRM_MODE_PROP_ENUM |
+						DRM_MODE_PROP_IMMUTABLE,
+						"Panel Self-Refresh",
+						psr_names,
+						ARRAY_SIZE(psr_names));
+		if (prop == NULL)
+			return;
+
+		dev_priv->psr.property = prop;
+	}
+
+	drm_object_attach_property(&connector->base, prop, PSR_UNSUPPORTED);
+}
+
+static void intel_psr_set_property(struct intel_connector *connector,
+				   uint64_t val)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
+	drm_object_property_set_value(&connector->base.base,
+				      dev_priv->psr.property, val);
+}
+
 static bool is_edp_psr(struct intel_dp *intel_dp)
 {
 	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
@@ -423,6 +467,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	}
 
 	dev_priv->psr.enabled = intel_dp;
+	intel_psr_set_property(intel_dp->attached_connector, PSR_ENABLED);
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
@@ -499,6 +544,8 @@ void intel_psr_disable(struct intel_dp *intel_dp)
 		vlv_psr_disable(intel_dp);
 
 	dev_priv->psr.enabled = NULL;
+	intel_psr_set_property(intel_dp->attached_connector, PSR_DISABLED);
+
 	mutex_unlock(&dev_priv->psr.lock);
 
 	cancel_delayed_work_sync(&dev_priv->psr.work);
-- 
2.1.0

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[PATCH 7/8] drm/i915/skl: Disallow tiling changes during page flip

[Rodrigo Vivi]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It would require watermark reprogramming which we do not want to do.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 489a134..a2b7259 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10896,6 +10896,15 @@ void intel_check_page_flip(struct drm_device *dev, int pipe)
 	spin_unlock(&dev->event_lock);
 }
 
+static bool intel_is_y_tiled(uint64_t fb_modifier)
+{
+	if (fb_modifier == I915_FORMAT_MOD_Y_TILED ||
+	    fb_modifier == I915_FORMAT_MOD_Yf_TILED)
+		return true;
+
+	return false;
+}
+
 static int intel_crtc_page_flip(struct drm_crtc *crtc,
 				struct drm_framebuffer *fb,
 				struct drm_pending_vblank_event *event,
@@ -11025,6 +11034,14 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 						  + intel_crtc->dspaddr_offset;
 
 	if (mmio_flip) {
+		/* Temporarily embedding knowledge of disallowed tiling mode
+		 * transition which would require watermark reprogramming.
+		 */
+		if (intel_is_y_tiled(old_fb->modifier[0]) !=
+		    intel_is_y_tiled(fb->modifier[0])) {
+			ret = -EINVAL;
+			goto cleanup_unpin;
+		}
 		ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
 					    page_flip_flags);
 		if (ret)
-- 
2.1.0

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[PATCH 8/8] drm/i915/skl: Select DDIA lane capability based upon vbt

[Rodrigo Vivi]

From: "sonika.jindal@intel.com" <sonika.jindal@intel.com>

Currently, if bios fails to drive an edp panel due to any reason,
the ddi buffer will not be enabled. And the DDIA lane capability
will remain 0. This leads to assumption of DDIA x2 which means DDIA
supports 2 lanes and DDIE supports 2 lanes. For some higher resolution
panel which needs 4 lanes, we end up using only 2 lanes which doesn't
let the modeset go through because of limited data rate avalaible.

So, set the DDIA lane capability correctly if port E is being used
by any child device or not.

Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   | 1 +
 drivers/gpu/drm/i915/intel_bios.c | 4 ++++
 drivers/gpu/drm/i915/intel_bios.h | 1 +
 drivers/gpu/drm/i915/intel_ddi.c  | 8 ++++++++
 4 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54703bf..8757093 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1406,6 +1406,7 @@ struct intel_vbt_data {
 	union child_device_config *child_dev;
 
 	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
+	unsigned int ddi_e_used;
 };
 
 enum intel_ddb_partitioning {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index cee596d..39ecab6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1124,6 +1124,9 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
 			dev_priv->vbt.dsi.port = p_child->common.dvo_port;
 		}
 
+		if (p_child->common.dvo_port == DVO_PORT_DPE)
+			dev_priv->vbt.ddi_e_used = 1;
+
 		child_dev_ptr = dev_priv->vbt.child_dev + count;
 		count++;
 		memcpy((void *)child_dev_ptr, (void *)p_child,
@@ -1174,6 +1177,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 		info->supports_hdmi = info->supports_dvi;
 		info->supports_dp = (port != PORT_E);
 	}
+	dev_priv->vbt.ddi_e_used = 0;
 }
 
 static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index af0b476..dd85812 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -764,6 +764,7 @@ int intel_parse_bios(struct drm_device *dev);
 #define DVO_PORT_DPC	8
 #define DVO_PORT_DPD	9
 #define DVO_PORT_DPA	10
+#define DVO_PORT_DPE	11
 #define DVO_PORT_MIPIA	21
 #define DVO_PORT_MIPIB	22
 #define DVO_PORT_MIPIC	23
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 807e15d..d2f2684 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2742,6 +2742,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	struct intel_encoder *intel_encoder;
 	struct drm_encoder *encoder;
 	bool init_hdmi, init_dp;
+	int val;
 
 	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
@@ -2772,6 +2773,13 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
 	intel_encoder->get_config = intel_ddi_get_config;
 
 	intel_dig_port->port = port;
+
+	val = I915_READ(DDI_BUF_CTL(port));
+	if (IS_SKYLAKE(dev) && port == PORT_A
+		&& !(val & DDI_BUF_CTL_ENABLE)
+		&& !dev_priv->vbt.ddi_e_used)
+		I915_WRITE(DDI_BUF_CTL(port), val | DDI_A_4_LANES);
+
 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
 					  (DDI_BUF_PORT_REVERSAL |
 					   DDI_A_4_LANES);
-- 
2.1.0

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Re: [PATCH 8/8] drm/i915/skl: Select DDIA lane capability based upon vbt

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6383
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                 -1              314/314              313/314
IVB                                  338/338              338/338
BYT                                  286/286              286/286
BDW                 -1              320/320              319/320
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 SNB  igt@pm_rpm@dpms-mode-unset-non-lpsp      DMESG_WARN(13)PASS(1)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
*BDW  igt@gem_gtt_cpu_tlb      PASS(2)      DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_display.c:#assert_plane[i915]()@WARNING:.* at .* assert_plane
assertion_failure@assertion failure
WARNING:at_drivers/gpu/drm/drm_irq.c:#drm_wait_one_vblank[drm]()@WARNING:.* at .* drm_wait_one_vblank+0x
Note: You need to pay more attention to line start with '*'
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